TW201608645A - 用於在一半導體記憶體裝置中形成一金屬罩的方法 - Google Patents

用於在一半導體記憶體裝置中形成一金屬罩的方法 Download PDF

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TW201608645A
TW201608645A TW104113584A TW104113584A TW201608645A TW 201608645 A TW201608645 A TW 201608645A TW 104113584 A TW104113584 A TW 104113584A TW 104113584 A TW104113584 A TW 104113584A TW 201608645 A TW201608645 A TW 201608645A
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慕拉里克里斯南 布拉克里斯南
邊在龍
葛瑞薩卡 達瑪拉
李紅旗
呂瑾
夏安 拉瑪林根
小永 蘇
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Abstract

本發明之例示性實施例係關於一種用於製造一半導體記憶體裝置之方法，該方法包括選擇性沈積一材料以在一凹入式胞結構上形成一罩，以便預防該胞結構內部之組件在氧化或腐蝕環境中降級。

Description

用於在一半導體記憶體裝置中形成一金屬罩的方法 相關申請案之交叉參考
本申請案主張2014年5月21日申請之美國優先專利申請案US14/283539之權利，該案之全部內容以引用的方式併入本文中。
本發明之某些實施例係關於形成一半導體裝置。更明確言之，本發明之實施例係關於一種用於在一半導體記憶體裝置中形成一金屬罩的方法。
最近，對非揮發性記憶體晶片之儲存容量及功率消耗之需求已迅速增長。小型化及高速半導體元件之開發正以一類似速度進行。阻變記憶體裝置正在更頻繁地使用以替換快閃記憶體裝置。一可變電阻式記憶體裝置採用一可變電阻元件作為一儲存元件。可變電阻式記憶體裝置包含但不限於：電阻式隨機存取記憶體(ReRAM)、導電橋隨機存取記憶體(CBRAM)、相變隨機存取記憶體(PCRAM)及類似者。在一典型電阻式記憶體裝置中，胞材料使用一習知方法(諸如化學氣相沈積(CVD)、物理氣相沈積(PVD)或電鍍)而沈積於一基板上。胞材料可為同質或非同質，例如，由多個層組成。基板(包含底端電極)可為同質或非同質，例如，金屬接觸件與一介電質之一組合。一導電金屬層沈積於胞材料上，充當頂端電極。通常，當某一電壓施加於頂端電 極時，舉例而言，胞材料電阻從一高電阻狀態改變至一低電阻狀態。
然而，使用光阻劑遮蔽與電漿蝕刻很難製造此一記憶體胞結構，因為胞材料趨向於複雜且，舉例而言，可由多種過渡金屬元件組成。因此，此等先進胞材料無法藉由商業上可用之乾式蝕刻方法來輕易圖案化。相應地，一鑲嵌程序通常用來製造胞結構，其中一厚層(充當一模板層)沈積於一基板上且經圖案化具有敞開溝渠，胞材料將沈積於該等敞開溝渠中。接著沈積胞材料之一厚塗層，該厚塗層明顯過度填充該模板中之溝渠。透過化學-機械平坦化(CMP)移除模板層上方之過多胞材料(被稱為覆蓋層)，且該模板層曝露。經由一化學方法、一濕潤帶或一乾燥帶而選擇性移除或挖掘該模板層，且製造隔離胞結構。
然而，在挖掘期間，由於乾式/濕式化學反應，胞材料之頂端透過氧化或腐蝕而被影響或損壞。此使頂端電極導電性與胞材料效能降級。
因此，此項技術中需要一種根據本發明之例示性實施例之用於形成一半導體記憶體裝置且不使用胞材料降級之方法。
如若干圖之至少一者中所示及/或結合該至少一者所描述、如在申請專利範圍中更全面陳述，實質上提供一種用於在一半導體記憶體裝置中形成一金屬罩的方法。
可藉由連同附圖一起檢視本發明之下列詳細描述而瞭解本發明之此等及其他特徵與優點。
100‧‧‧半導體記憶體裝置
102‧‧‧基板
104‧‧‧模板層
105‧‧‧溝渠
108‧‧‧活性胞材料
110‧‧‧第一金屬層
112‧‧‧第一接觸件
114‧‧‧第二接觸件
200‧‧‧凹槽
202‧‧‧胞結構
300‧‧‧罩
400‧‧‧側壁膜
圖1描繪根據本發明之例示性實施例之一製程中之一第一步驟。
圖2描繪根據本發明之例示性實施例之製程中之一第二步驟。
圖3描繪根據本發明之例示性實施例之製程中之一第三步驟。
圖4描繪根據本發明之例示性實施例之製程中之一第四步驟。
某些實施方案可見於一記憶體胞結構中之一選擇性形成的金屬罩中。根據一實施例，一記憶體胞可使用一鑲嵌程序來形成。即，一模板層經圖案化及經蝕刻以形成溝渠，活性胞材料與第一金屬層經沈積在溝渠中形成結構，且接著溝渠中之結構藉由一化學-機械平坦化(CMP)而隔離。清潔並使用包括第二金屬之一罩來選擇性覆蓋經曝露之第一金屬表面。第二金屬具有一些抗氧化性及/或耐腐蝕性。藉由電漿增強氧化(稱為挖掘)或藉由化學溶解來選擇性移除模板層。在模板層移除期間，藉由罩層來保護活性胞材料之頂端表面與頂端電極。記憶體胞可為電阻式隨機存取記憶體(ReRAM)、導電橋隨機存取記憶體(CB-RAM)胞、相變記憶體(PCRAM)或類似者。
圖1至圖4描繪根據本發明之例示性實施例之用於在一半導體記憶體裝置100中形成一金屬罩的一方法。
圖1描繪裝置100之一製程中之一第一步驟。一鑲嵌程序之結果係圖1中所展示之結構，其中一基板102具有一第一接觸件112與一第二接觸件114(底端電極接觸件(BEC))。此項技術之一般技術者應認識到，基板102可含有一單一接觸件或複數個接觸件，此取決於所得裝置100之使用且本發明並不限制該裝置100僅具有兩個接觸件。金屬接觸件112與114係電可導，充當底端電極，且透過一基板層102製造，該基板層102含有介電材料(諸如氧化矽、氮化矽或類似者)。此介電層102將活性胞材料108與活性半導體基礎材料(圖1中未展示，但為此項技術之一般技術者所熟知)分離。活性半導體基礎材料可為一電晶體之一端子，舉例而言，一閘極端子。在一些實施例中，此一電晶體係用於放大或切換電子信號之一金屬氧化物半導體場效應電晶體(MOSFET)。一模板層104位於基板102頂上。在鑲嵌程序期間，一溝 渠105形成於模板層104中。胞材料108沈積於溝渠105上並與溝渠105對齊。一第一金屬層110形成於胞材料108之上以填充溝渠105。該第一金屬層110將形成頂端電極。在一些實施例中，銅經選擇作為第一金屬層110以達成一低電阻胞金屬線。在其他實施例中，金屬層110可為Cu、Au、Ta、Ru、Pt、W、Ti、聚酯(Poly)或類似者。模板層104可由碳、多晶矽、氧化矽或類似者組成。
圖2描繪根據本發明之例示性實施例之製程中之一第二步驟。化學-機械平坦化(CMP)經執行以移除第一金屬層110之塊體與胞材料108之一部分。經平坦化第一金屬層110與胞材料108形成胞結構202，胞結構202從模板層104之平面凹入。根據一實施例，CMP程序使用傳統CMP研磨劑，諸如膠狀矽石、煙霧矽石或膠狀礬土。在CMP期間，藉由機械動作及/或化學改質移除第一金屬層110與胞材料108。當藉由CMP曝露模板層104時，晶圓表面與拋光襯墊之間之摩擦可明顯改變，且一基於摩擦之端點程序控制方法變得可行。類似地，當藉由CMP曝露模板層104時，晶圓表面光學反射強度可明顯改變，且此使一基於光學摩擦之端點程序控制方法可行。在擷取程序跡線(諸如摩擦跡線或光學反射跡線)之變化之後，過度拋光開始。過度拋光導致胞材料108退至模板層104之平面下方，留下一凹槽200。該凹槽200之深度主要由過度拋光時間來判定。過度拋光亦充分曝露模板層104之表面使得隨後將使用一挖掘方法來消耗該模板層104之表面。在CMP之後，一濕式清潔程序經執行以移除任何氧化表面金屬並曝露溝渠105中之第一金屬層110之一全新表面。該全新表面幫助在圖3中描述的隨後階段處在凹槽200中選擇性沈積罩材料。在一些實施例中，待沈積於凹槽200中之罩材料係W或Ti，該兩種材料比銅(即，第一金屬層110)或活性胞材料108具有更強的耐腐蝕性。在模板層104經挖掘之後，當一濕式清潔程序應用於晶圓上以便移除電漿增強挖掘期間所產 生之各種聚合物殘餘物時，胞結構202更加穩定。根據一些實施例，一基於電漿之乾式蝕刻方法選擇性移除模板層104，而胞材料108保留。在一些情況中，當模板層104經挖掘時，可產生高活性化學物種，在胞結構202之表面上產生固體副產品。根據一實施例，藉由使用一些酸性或鹼性水溶液之一濕式清潔方法選擇性移除此等副產品。通常此程序被稱為蝕刻後清潔，為此項技術之一般技術者所熟知。銅對此清潔敏感。W與Ti不受此濕式清潔影響。
圖3描繪根據本發明之例示性實施例之製程中之一第三步驟。一材料經選擇性沈積作為第一金屬層110之全新表面上之凹槽200中之一罩300，以保護胞結構202，且明確言之以保護第一金屬層110而不受任何化學反應的影響，當模板層104經選擇性移除時可引起化學反應。罩300僅沈積於凹槽200中且不沈積於模板層104上。在罩300形成之後，模板層104仍然曝露。在一些實施例中，罩300可使用W、Ti、Co或類似者來形成，能夠經選擇性沈積於第一金屬層110之上。作為一實例，根據一實施例，元素鎢之選擇性沈積係藉由使用氣態WF6與SiH4作為沈積前驅體之化學氣相沈積而在一沈積腔室內進行，該等沈積前驅體在沈積期間饋送至腔室。惰性及/或其他氣體可在沈積期間饋送至腔室。在此實施例中，在沈積期間，基板溫度係從大約250℃至350℃，腔室壓力係從大約1毫托至100毫托，腔室之WF6流率係從大約10sccm至1,000sccm，且腔室之SiH4流率係從大約5sccm至50sccm。一實例惰性氣體流率(例如，Ar)係大約0sccm至1,000sccm。此項技術之一般技術者將認識到此等範圍並非明確要求且其他範圍可用於本發明之實施方案中。
一W罩或Ti罩在一濕式清潔期間具有耐腐蝕性，其進一步預防對第一金屬層110(例如，Cu層)之腐蝕。在一些實施例中，罩300係使用材料(諸如SiN、SiOx)及高k介電質(諸如HfOx、AlOx、ZrOx及類似者) 之一選擇性介電罩。根據例示性實施例，選擇性金屬或選擇性介電質係藉由化學氣相沈積(CVD)、原子層沈積(ALD)、選擇性無電電鍍或類似者之一者而沈積。在一些實施例中，可犧牲罩300，即，在模板層104挖掘之後，該罩300可藉由乾式蝕刻技術而選擇性移除。
圖4描繪根據本發明之例示性實施例之製程中之一第四步驟。經由一乾燥程序或一濕潤程序而選擇性移除模板層104。根據例示性實施例，若模板層104為碳，則含氧電漿用於挖掘程序。若模板層為多晶矽，則可使用含F電漿乾式蝕刻來執行挖掘。在另一實施例中，其中模板層104係由氧化矽構成，一含HF水溶液用於挖掘程序。此項技術之一般技術者將認識到挖掘程序將符合用於形成模板層104之材料。由於第一金屬層110上罩300之形成，故可預防胞結構202中之金屬層110之頂端表面在挖掘期間被氧化或腐蝕且與其中銅層未經保護之挖掘程序相比該頂端表面被很好地保留。然而，活性胞材料108之側壁部分可被氧化或化學改質，其被展示為圖4中之側壁膜。該側壁膜400成為一障壁以使內部胞結構108及110與外界各種化學反應隔離。雖然已參考某些實施例描述本發明，但熟悉此項技術者應瞭解可作出各種改變且可用等效物替代，而不背離本發明之範疇。另外，可作出許多修改以使一特定情形或材料適於本發明之教示，而不背離其範疇。因此，希望本發明並不限於所揭示之特定實施例，而是本發明將包含落於隨附申請專利範圍之範疇內之所有實施例。
102‧‧‧基板
104‧‧‧模板層
108‧‧‧活性胞材料
110‧‧‧第一金屬層
112‧‧‧第一接觸件
114‧‧‧第二接觸件
202‧‧‧胞結構
300‧‧‧罩

Claims (14)

  1. 一種用於製造一半導體記憶體裝置之方法，其包括：選擇性沈積一材料以在一凹入式胞結構上形成一罩，以便預防該胞結構內部之組件在氧化或腐蝕環境中降級。
  2. 如請求項1之方法，其中選擇性沈積該罩材料進一步包括：使用化學氣相沈積、原子層沈積或選擇性無電電鍍之一者來進行沈積。
  3. 如請求項1之方法，其進一步包括使用一乾式蝕刻方法來移除該罩。
  4. 如請求項1之方法，其進一步包括：在對用於形成該凹入式胞結構之該材料執行一化學-機械平坦化之後，執行該選擇性沈積。
  5. 如請求項4之方法，其中該凹入式胞結構包括一低電阻頂端電極與活性胞材料，且該胞結構係形成於一模板層中之一溝渠中。
  6. 如請求項5之方法，其中該選擇性罩係使用W、Ti或Co之一者形成之一金屬罩。
  7. 如請求項5之方法，其進一步包括：在選擇性沈積該材料而形成該罩之前，先執行一化學-機械平坦化(CMP)程序以形成該凹入式胞結構。
  8. 如請求項7之方法，其中該罩係由W、TiN、TaN、Ta或TiW之一者形成之一金屬罩。
  9. 如請求項7之方法，其中該罩係由SiN、SiOx、HfOx、AlOx或ZrOx之一者形成之一介電罩。
  10. 一種裝置，其包括：一凹入式胞結構，其形成於一基板頂上之一溝渠中，該溝渠 藉由一鑲嵌程序而產生；及一罩，其形成於該凹入式胞結構之上以保護該凹入式胞結構使其免於降級。
  11. 如請求項10之裝置，其中該罩係藉由一選擇性沈積而形成。
  12. 如請求項11之裝置，其形成一記憶體胞，其中該記憶體胞係一電阻式隨機存取記憶體(ReRAM)胞、導電橋隨機存取記憶體(CB-RAM)胞或一相變記憶體(PCRAM)胞。
  13. 如請求項11之裝置，其中該罩係一介電罩或一金屬罩。
  14. 如請求項13之裝置，其中該金屬罩係使用W、TiN、TaN、Ta或TiW之一者而形成，且該介電罩係使用SiN、SiOx或一高k介電質之一者而形成。
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US20170133585A1 (en) 2017-05-11
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