TW201543582A - 半導體裝置及其製造方法 - Google Patents

半導體裝置及其製造方法 Download PDF

Info

Publication number
TW201543582A
TW201543582A TW104102682A TW104102682A TW201543582A TW 201543582 A TW201543582 A TW 201543582A TW 104102682 A TW104102682 A TW 104102682A TW 104102682 A TW104102682 A TW 104102682A TW 201543582 A TW201543582 A TW 201543582A
Authority
TW
Taiwan
Prior art keywords
semiconductor wafer
semiconductor device
manufacturing
uneven
semiconductor
Prior art date
Application number
TW104102682A
Other languages
English (en)
Other versions
TWI643267B (zh
Inventor
Makoto Takesawa
Original Assignee
Seiko Instr Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Instr Inc filed Critical Seiko Instr Inc
Publication of TW201543582A publication Critical patent/TW201543582A/zh
Application granted granted Critical
Publication of TWI643267B publication Critical patent/TWI643267B/zh

Links

Classifications

    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K26/00—Working by laser beam, e.g. welding, cutting or boring
    • B23K26/50—Working by transmitting the laser beam through or within the workpiece
    • B23K26/53—Working by transmitting the laser beam through or within the workpiece for modifying or reforming the material inside the workpiece, e.g. for producing break initiation cracks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/27—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3142—Sealing arrangements between parts, e.g. adhesion promotors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L24/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K2103/00—Materials to be soldered, welded or cut
    • B23K2103/50—Inorganic material, e.g. metals, not provided for in B23K2103/02 – B23K2103/26
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K2103/00—Materials to be soldered, welded or cut
    • B23K2103/50—Inorganic material, e.g. metals, not provided for in B23K2103/02 – B23K2103/26
    • B23K2103/56—Inorganic material, e.g. metals, not provided for in B23K2103/02 – B23K2103/26 semiconducting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L2224/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
    • H01L2224/0801—Structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29298—Fillers
    • H01L2224/29299—Base material
    • H01L2224/293—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29338—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/29339—Silver [Ag] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/3201—Structure
    • H01L2224/32012—Structure relative to the bonding area, e.g. bond pad
    • H01L2224/32013—Structure relative to the bonding area, e.g. bond pad the layer connector being larger than the bonding area, e.g. bond pad
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45147—Copper (Cu) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/1015—Shape
    • H01L2924/10155—Shape being other than a cuboid
    • H01L2924/10156—Shape being other than a cuboid at the periphery
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12042—LASER
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/183—Connection portion, e.g. seal
    • H01L2924/18301—Connection portion, e.g. seal being an anchoring portion, i.e. mechanical interlocking between the encapsulation resin and another package part

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)
  • Manufacturing & Machinery (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Oil, Petroleum & Natural Gas (AREA)
  • Mechanical Engineering (AREA)
  • Plasma & Fusion (AREA)
  • General Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Chemical & Material Sciences (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Dicing (AREA)
  • Geometry (AREA)
  • Electromagnetism (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Die Bonding (AREA)

Abstract

本發明係一種半導體裝置及其製造方法，其課題為提供耐濕性良好的之半導體裝置。 解決手段為由形成具有大的凹凸之範圍(25)於經由封閉樹脂(8)所被覆之半導體晶片(2)之上側面，而形成具有小的凹凸之範圍(24)於下側面者，使半導體晶片(2)與封閉樹脂(8)之密著力提升，防止自外部的水分之浸入。

Description

半導體裝置及其製造方法
本發明係有關半導體裝置之製造方法，特別是有關可抑制於半導體晶片與塑模樹脂之間產生有剝離情況之半導體封裝之製造方法。
環繞近年來的半導體裝置之環境係特別在車載領域中電子化進展著，對於引擎室搭載電子構件等變多，而市場上要求有在更高溫且多濕的環境之動作保障。為了進行動作保障之試驗方法，係具體而言在公共機關中加以規定。例如，對於經由代表性的規格之IPC/JEDEC之J-STD-020D“Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices”之Moisture Sensitivity Level(以下MSL)，係有的對於保管溫度‧濕度條件或開封後之處理時間或信賴性試驗的條件之規定。
對於對應於如此之試驗，係特別必須抑制在半導體封裝內部之各密著界面的剝離情況，而揭示有至此各種構造 或製造方法。
作為一例，揭示有：於引線架表面，將稱作PPF(Pre-Plated Frame)之自Pd/Ni/Au等加以構成之電鍍表面，作為凹凸化，使與塑模樹脂之密著性提升之信賴性高的樹脂封閉型半導體裝置。(例如，參照專利文獻1)
另外，揭示有作為剝離的原因而有經由在各構成材料之熱膨脹係數差的熱應力之影響，為了抑制此等而調整，塑模樹脂之熱膨脹係數與彎曲彈性，半導體封裝內部的熱應力則變小而封裝的信性性高之樹脂封閉型半導體裝置。 (例如，參照專利文獻2)
〔先前技術文獻〕 〔專利文獻〕
[專利文獻1]日本特開2005-223305號公報
[專利文獻2]日本特開2001-223304號公報
但作為使用此等技術，亦無法完全抑制半導體封裝之剝離者。原因是半導體封裝之主要構成材料的引線架，塑模樹脂，半導體晶片係因各自材料不同之故而伴隨有熱膨脹係數的差。另外，從各材料之加工方法的不同，表面狀態亦為不同之故而內部的密著力與應力係有著不均一之狀態。隨之，即使使特定部位之密著性提升，以及將塑模樹脂作為低應力化，如未相對性地均一化內部密著力時，結 果係應力將集中於密著力弱的部分，而成為從其部位誘發剝離者。半導體晶片之保護膜表面與封閉樹脂之密著性或引線架與封閉樹脂之密著性係持續加以改善，但部分存在有密著性弱的部分。
於圖4，顯示為了說明在半導體晶片側面之剝離的圖。如圖4(a)所示，半導體晶片2係於施以粗面15於表面的晶粒墊片3上，藉由銀電糊等之接著劑18而加以搭載。半導體晶片2之上表面係由聚醯亞胺膜等所成之保護膜17而加以被覆，而晶粒墊片3，半導體晶片2係經由封閉樹脂8而加以封閉。擴大半導體晶片2側面者則為圖4(b)。對於半導體晶片2側面係存在有稱為剝離之剝離部19，封閉樹脂8與半導體晶片2則未密著，而有耐濕性低之問題。
本發明係提供：為了解決上述課題之半導體裝置及其製造方法者。
為了解決上述課題，而使用以下的手段。
首先，一種半導體裝置，係具備半導體晶片，和支持前述半導體晶片之晶粒墊片，和接著前述半導體晶片與前述晶粒墊片之接著劑，和朝向前述晶粒墊片的邊而延伸存在之複數之信號用引線，和連接前述半導體晶片與前述信號用引線之接合導線，和以塑模樹脂封閉之封閉體之半導體裝置，其特徵為前述半導體晶片之側面則由第一凹凸側 面與加以形成於前述第一側面之上方的第二凹凸側面所成，而在前述第二凹凸側面的第二凹凸係較在前述第一凹凸側面的第一凹凸為大者。
另外，作成前述第二凹凸側面為前述半導體晶片之厚度的2/3以上者為特徵之半導體裝置。
另外，使用一種半導體裝置之製造方法，係具備半導體晶片，和支持前述半導體晶片之晶粒墊片，和接著前述半導體晶片與前述晶粒墊片之接著劑，和朝向前述晶粒墊片的邊而延伸存在之複數之信號用引線，和連接前述半導體晶片與前述信號用引線之接合導線，和以塑模樹脂封閉之封閉體之半導體裝置之製造方法，其中，於前述半導體晶片之側面形成第一凹凸側面之工程，和於前述半導體晶片之側面形成第二凹凸側面的工程所成者。
另外，使用：形成前述第二凹凸側面之工程則以脈衝雷射形成連續之改質層於前述半導體晶片內之工程者為特徵之半導體裝置之製造方法。
另外，使用：形成前述第二凹凸側面之工程則使用燒蝕雷射之工程者為特徵之半導體裝置之製造方法。
另外，使用：形成前述第一凹凸側面之工程則以脈衝雷射形成隔離之改質層於前述半導體晶片內之工程者為特徵之半導體裝置之製造方法。
另外，使用：形成前述第二凹凸側面之工程則為刀切割工程，而切割刀之網孔尺寸為#1000以下者為特徵之半導體裝置之製造方法。
另外，使用：於前述刀切割工程之後，進行等向性電漿矽蝕刻者為特徵之半導體裝置之製造方法。
另外，使用：形成前述第二凹凸側面之工程則為電漿切割工程，其中，為蝕刻製程之矽蝕刻者為特徵之半導體裝置之製造方法。
由使用上述手段者，可得到半導體晶片與封閉樹脂之密著提升，而耐濕性良好之半導體裝置。
1‧‧‧半導體裝置
2‧‧‧半導體晶片
3‧‧‧晶粒墊片
4‧‧‧引線
5‧‧‧吊引線
5a‧‧‧吊引線基部
5b‧‧‧吊引線外面部
6‧‧‧引線
6a‧‧‧引線內在部
6b‧‧‧引線外面部
7‧‧‧接合導線
8‧‧‧封閉樹脂
9‧‧‧脈衝雷射
10‧‧‧改質層
11‧‧‧改質層
12‧‧‧劃片線
13‧‧‧聚光透鏡
14‧‧‧切割膠帶
15‧‧‧粗面
16‧‧‧切割刀
17‧‧‧保護膜
18‧‧‧接著劑
19‧‧‧剝離部
24‧‧‧第一凹凸側面
25‧‧‧第二凹凸側面
S1‧‧‧切割工程
S2‧‧‧晶片黏合工程
S3‧‧‧晶片黏合處理工程
S4‧‧‧導線接合工程
S5‧‧‧組裝檢查工程
S6‧‧‧樹脂封閉工程
S7‧‧‧改質工程
圖1係顯示本發明之半導體裝置之第1實施形態之剖面圖。
圖2係本發明之半導體裝置的平面圖。
圖3係顯示本發明之半導體裝置之製造方法的工程流程圖。
圖4係以往之半導體裝置的剖面圖。
圖5係顯示本發明之半導體裝置之製造方法的圖。
圖6係顯示本發明之半導體裝置之製造方法的圖。
對於本發明之半導體裝置與其製造方法，使用圖而加以說明。
圖1係本發明之半導體裝置的部分剖面圖。如圖1 (a)所示，半導體晶片2係於施以粗面15於上表面的晶粒墊片3上，藉由銀電糊等之接著劑18而加以搭載。半導體晶片2之上表面係經由聚醯亞胺膜等所成之保護膜17而加以被覆，而晶粒墊片3，半導體晶片2係經由封閉樹脂8而加以封閉。擴大半導體晶片2側面者則為圖1(b)。對於半導體晶片2之側面下部係加以形成有小凹凸所成之第一凹凸側面24(第一凹凸係未圖示)，而對於側面上部，係加以形成有配置較在側面下部的凹凸為大之凹凸的第二凹凸側面25。由作為如此之構成者，加以形成有半導體元件之半導體晶片之側面上部與封閉樹脂8之密著力則成為提升，而成為可抑制水分的浸入，作為耐濕性良好之半導體裝置者。然而，在此凹凸為大或小之表現係為從所形成之凹凸的凹部底至凸部頂上為止之長度為大或小者。
然而，於半導體晶片2之側面下部，由設置第一凹凸側面24者，晶片黏合時之接著劑18的冒出則成為良好，即使為小型的半導體晶片，與晶粒墊片3之密著性則亦提升者。
圖2係顯示本發明之半導體裝置之構成的平面圖。樹脂封閉型之半導體裝置1係具備：半導體晶片2，和固定半導體晶片2之晶粒墊片3，和延伸於晶粒墊片3兩側之引線4。半導體晶片2係例如，由半導體基板，和加以設置於半導體基板上之配線層等而加以構成者，加以固定於晶粒墊片3。晶粒墊片3及引線部4係具有導電性者，例 如，由Fe-Ni合金、Cu合金等之金屬所形成。對於晶粒墊片周圍係有複數之引線4，而於晶粒墊片3之一邊側配置有2條，於對向之另一邊側配置有2條，合計加以配置有4條。並且，此等引線部4之中的1條之引線係吊引線5，而吊引線5之基部5a則加以固定於晶粒墊片3。其他的3條係從晶粒墊片3隔離之引線部6，而其內在部6a則藉由具有導電性之接合導線7而與半導體晶片2加以電性連接。對於接合導線7係加以使用金線或銅線。如此所構成之半導體晶片2，晶粒墊片3及引線6之內在部6a係作為由以樹脂加以形成之封閉樹脂8加以封閉，從自外部的衝擊等而保護半導體晶片2，作為電性絕緣之同時，藉由複數之引線4而可電性連接半導體晶片2與外部之構成。作為封閉樹脂8，係例如，使用添加有酚系硬化劑或添加有矽橡膠或填充物等之聯苯系之絕緣樹脂。
接著，使用圖3，對於本發明之半導體裝置之製造方法加以說明。
首先，對於圖所示之工程S1~S6加以說明。切割工程S1係將半導體晶圓分割為半導體晶片之工程。晶片黏合工程S2係使用銀電糊等而接著半導體晶片於引線架之晶粒墊片範圍之工程。接下來的晶片黏合處理工程S3係加熱所接著之晶粒墊片與半導體晶片而使接合部硬化之工程。接下來之導線接合工程S4係經由對於熱壓著併用超音波振動之接合法等，將接合導線，連接半導體晶片表面的電極部分與引線內在部之工程。並且，在以組裝檢查工 程S5，對於晶粒墊片與半導體晶片之接合狀態，半導體晶片與接合導線之接合狀態進行檢查，移行至樹脂封閉工程S6。
樹脂封閉工程S6中，首先，對應於各晶粒墊片，準備具備圍繞晶粒墊片及半導體晶片之空間的模孔，和使加以注入之封閉樹脂，流入至各模孔附近為止之流路，和連通流路與模孔之閘閥的塑模金屬模具。並且，以塑模金屬模具夾入引線架，於各塑模金屬模具，注入，充填封閉樹脂之後，從塑模金屬模具取出所封閉之引線架。在此時點中，於引線間等加以形成有薄的樹脂毛邊。此係在充填樹脂於塑模金屬模具之模孔時，經由從些微的間隙漏出之樹脂者，依存於塑模金屬模具，以對於各塑模金屬模具不同之位置，形狀加以形成。
對於切割工程S1之詳細，以例說明3種方法。
最初，圖3(a)係使用雷射切割工程之製造方法。如圖5所示，在此係於形成於加以貼合在切割膠帶14之半導體基板的半導體晶片2與鄰接之半導體晶片2間，所設置之劃片線12，藉由聚光透鏡13而照射脈衝雷射9。脈衝雷射係加以多段數照射於深度方向，而對於加以雷射照射的範圍係加以形成有改質層10。對於半導體晶片2之厚度方向的上部2/3，係加以形成於深度方向之改質層10則呈平面連續性地連結地，以高輸出緊密地加以照射脈衝雷射。此等則相當於圖3(a)之雷射切割工程1，形成圖1(b)之第二凹凸側面25的工程。雷射切割工程2 係於半導體晶片之厚度方向的下部1/3，形成第一凹凸側面24之工程，經由低輸出之脈衝雷射而加以形成於深度方向之改質層11係加以隔離形成，而各個改質層11的尺寸亦較在雷射切割工程1所形成之改質層10之尺寸為小。歷經雷射切割工程1及2之後，加以劈開，成為得到具有第一凹凸側面24與第二凹凸側面25之半導體晶片2者。
對於半導體晶片2之厚度而言，第二凹凸側面25之厚度如為充分厚時，無須進行雷射切割工程2，於雷射切割工程1之後加以劈開。在此製造方法中，對於第二凹凸側面25係成為加以形成有與前述的例相同尺寸的凹凸者，但第一凹凸側面24係為劈開面之故而成為加以形成極小之凹凸者。
在以上中，說明過脈衝雷射係從半導體晶片之元件形成面之上表面加以照射的例，但在從迴避加以形成於劃片線之TEG之半導體晶片的背面之照射亦可。
第二凹凸側面25係取代脈衝雷射法而使用燒蝕雷射法亦可實現。此情況，對於雷射切割工程1成為使用燒蝕雷射，但比較於脈衝雷射法而成為形成大的凹凸者。對於雷射切割工程2係使用低輸出之脈衝雷射，之後，歷經進行劈開之工程而得到半導體晶片。
接著，圖3(b)係使用刀切割工程之製造方法。如圖6(a)，(b)所示，在此係於形成於加以貼合在切割膠帶14之半導體基板的半導體晶片2與鄰接之半導體晶 片2間，所設置之劃片線12，使切割刀16移動而將半導體晶圓，切斷成各個半導體晶片之方法。在此係使用粒度不同之2種切割刀，在刀切割工程1中，以網孔為# 1000以下之粗度的刀，從半導體晶片表面進行半切割，形成第二凹凸側面25。接著，在刀切割工程2中，由使用網孔為# 2000以上的刀而進行割斷者，形成第一凹凸側面24，而成為得到具有第一凹凸側面24與第二凹凸側面25之半導體晶片2。在此製造方法中，由追加如等向性之電漿矽蝕刻之改質工程S7者，加以除去割斷面之損傷層，可作為耐濕性更高之半導體裝置者。
圖3(c)係使用電漿切割工程之製造方法。在電漿切割工程1中，以反覆等向性蝕刻與保護膜之堆積之蝕刻製程，進行矽蝕刻而形成第二凹凸側面25。在蝕刻製程中，於半導體晶片側面，成為加以形成有稱作扇形之連續的凹凸者。接著，以在電漿切割工程2，進行剩餘的矽蝕刻，將半導體晶圓割斷成各個半導體晶片。在此係並非蝕刻製程而使用以異向性蝕刻進行深掘的手法。由歷經如此之電漿切割工程1及2者，成為得到具有第一凹凸側面24與第二凹凸側面25之半導體晶片2者。
2‧‧‧半導體晶片
3‧‧‧晶粒墊片
8‧‧‧封閉樹脂
15‧‧‧粗面
17‧‧‧保護膜
18‧‧‧接著劑
24‧‧‧第一凹凸側面
25‧‧‧第二凹凸側面

Claims (9)

  1. 一種半導體裝置，係具備半導體晶片，和支持前述半導體晶片之晶粒墊片，和接著前述半導體晶片與前述晶粒墊片之接著劑，和朝向前述晶粒墊片的邊而延伸存在之複數之信號用引線，和連接前述半導體晶片與前述信號用引線之接合導線，和以塑模樹脂封閉之封閉體之半導體裝置，其特徵為前述半導體晶片之側面則由第一凹凸側面與加以形成於前述第一凹凸側面之上方的第二凹凸側面所成，在前述第二凹凸側面的第二凹凸係較在前述第一凹凸側面的第一凹凸為大者。
  2. 如申請專利範圍第1項記載之半導體裝置，其中，前述第二凹凸側面為前述半導體晶片之厚度的2/3以上者。
  3. 一種半導體裝置之製造方法，係具備半導體晶片，和支持前述半導體晶片之晶粒墊片，和接著前述半導體晶片與前述晶粒墊片之接著劑，和朝向前述晶粒墊片的邊而延伸存在之複數之信號用引線，和連接前述半導體晶片與前述信號用引線之接合導線，和以塑模樹脂封閉之封閉體之半導體裝置之製造方法，其特徵為具備：於前述半導體晶片之側面形成第一凹凸側面之工程，和於前述半導體晶片之側面形成與前述第一凹凸面不同之第二凹凸側面的工程者。
  4. 如申請專利範圍第3項記載之半導體裝置之製造 方法，其中，形成前述第二凹凸側面之工程則以脈衝雷射形成連續之改質層於前述半導體晶片內之工程者。
  5. 如申請專利範圍第3項記載之半導體裝置之製造方法，其中，形成前述第二凹凸側面之工程則使用燒蝕雷射之工程者。
  6. 如申請專利範圍第3項記載之半導體裝置之製造方法，其中，形成前述第一凹凸側面之工程則以脈衝雷射形成隔離之改質層於前述半導體晶片內之工程者。
  7. 如申請專利範圍第3項記載之半導體裝置之製造方法，其中，形成前述第二凹凸側面之工程則為電漿切割工程，係蝕刻製程之矽蝕刻者。
  8. 如申請專利範圍第3項記載之半導體裝置之製造方法，其中，形成前述第二凹凸側面之工程則為刀切割工程，係切割刀之網孔尺寸為#1000以下者。
  9. 如申請專利範圍第8項記載之半導體裝置之製造方法，其中，於前述刀切割工程之後，進行等向性電漿矽蝕刻者。
TW104102682A 2014-02-13 2015-01-27 半導體裝置及其製造方法 TWI643267B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2014025799A JP6250429B2 (ja) 2014-02-13 2014-02-13 半導体装置およびその製造方法
JP2014-025799 2014-02-13

Publications (2)

Publication Number Publication Date
TW201543582A true TW201543582A (zh) 2015-11-16
TWI643267B TWI643267B (zh) 2018-12-01

Family

ID=53775549

Family Applications (1)

Application Number Title Priority Date Filing Date
TW104102682A TWI643267B (zh) 2014-02-13 2015-01-27 半導體裝置及其製造方法

Country Status (5)

Country Link
US (2) US9887171B2 (zh)
JP (1) JP6250429B2 (zh)
KR (1) KR102287698B1 (zh)
CN (1) CN104851851B (zh)
TW (1) TWI643267B (zh)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6250429B2 (ja) * 2014-02-13 2017-12-20 エスアイアイ・セミコンダクタ株式会社 半導体装置およびその製造方法
JP6478821B2 (ja) * 2015-06-05 2019-03-06 株式会社ディスコ ウエーハの生成方法
US9496193B1 (en) 2015-09-18 2016-11-15 Infineon Technologies Ag Semiconductor chip with structured sidewalls
JP6674677B2 (ja) * 2016-02-17 2020-04-01 ローム株式会社 チップ部品およびその製造方法
KR20170098476A (ko) * 2016-02-22 2017-08-30 (주)파트론 지문인식 센서 패키지 및 그 제조 방법
JP2018078192A (ja) * 2016-11-09 2018-05-17 株式会社村田製作所 半導体装置
JP2018110156A (ja) * 2016-12-28 2018-07-12 キヤノン株式会社 半導体装置、その製造方法およびカメラ
JP6649308B2 (ja) * 2017-03-22 2020-02-19 キオクシア株式会社 半導体装置およびその製造方法
GB201708927D0 (en) * 2017-06-05 2017-07-19 Spts Technologies Ltd Methods of plasma etching and plasma dicing
DE102017212858A1 (de) * 2017-07-26 2019-01-31 Disco Corporation Verfahren zum Bearbeiten eines Substrats
JP6903532B2 (ja) * 2017-09-20 2021-07-14 キオクシア株式会社 半導体装置およびその製造方法
JP7491098B2 (ja) 2020-07-07 2024-05-28 株式会社デンソー 半導体装置

Family Cites Families (29)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01208105A (ja) * 1988-02-15 1989-08-22 Nec Corp 半導体装置の製造方法
JPH03270156A (ja) * 1990-03-20 1991-12-02 Oki Electric Ind Co Ltd 半導体装置の製造方法
JPH0574932A (ja) * 1991-09-17 1993-03-26 Fujitsu Ltd 半導体ウエハのダイシング方法
JP3147455B2 (ja) * 1992-01-20 2001-03-19 富士通株式会社 半導体ウェーハの切断方法
JPH06236899A (ja) * 1992-09-29 1994-08-23 Toshiba Corp 樹脂封止型半導体装置
DE4305296C3 (de) * 1993-02-20 1999-07-15 Vishay Semiconductor Gmbh Verfahren zum Herstellen einer strahlungsemittierenden Diode
DE19506323A1 (de) * 1995-02-23 1996-08-29 Siemens Ag Halbleitervorrichtung mit aufgerauhter Halbleiteroberfläche
JP2001223304A (ja) 2000-02-09 2001-08-17 Sumitomo Bakelite Co Ltd 樹脂封止型半導体装置
WO2002041364A2 (en) * 2000-11-16 2002-05-23 Emcore Corporation Led packages having improved light extraction
DE60211728T2 (de) * 2001-10-01 2007-05-03 Xsil Technology Ltd. Verfahren und vorrichtung zur bearbeitung von substraten
JP2003197564A (ja) * 2001-12-21 2003-07-11 Disco Abrasive Syst Ltd 低誘電体絶縁材料を積層した基板のダイシング方法
KR101037142B1 (ko) * 2002-04-19 2011-05-26 일렉트로 사이언티픽 인더스트리즈, 아이엔씨 펄스 레이저를 이용한 기판의 프로그램 제어 다이싱
JP2004179565A (ja) * 2002-11-29 2004-06-24 Sony Corp 電子部品の製造方法及びダイシング方法、並びにこれらを実施するための製造装置
JP4495916B2 (ja) * 2003-03-31 2010-07-07 富士通マイクロエレクトロニクス株式会社 半導体チップの製造方法
JP4301068B2 (ja) 2004-01-09 2009-07-22 株式会社デンソー 樹脂封止型半導体装置およびその製造方法
JP4008931B2 (ja) * 2004-03-25 2007-11-14 株式会社東芝 半導体装置及びその製造方法
KR101109860B1 (ko) * 2004-08-06 2012-02-21 하마마츠 포토닉스 가부시키가이샤 레이저 가공 방법, 가공 대상물 절단 방법 및 반도체 장치
JP5064985B2 (ja) * 2006-12-05 2012-10-31 古河電気工業株式会社 半導体ウェハの処理方法
JP2009004625A (ja) * 2007-06-22 2009-01-08 Sanken Electric Co Ltd 半導体発光装置
JP2010080769A (ja) * 2008-09-26 2010-04-08 Mitsumi Electric Co Ltd 半導体装置の製造方法
KR20100080423A (ko) 2008-12-30 2010-07-08 삼성엘이디 주식회사 발광소자 패키지 및 그 제조방법
TW201041185A (en) * 2009-05-04 2010-11-16 Taiwan Iris Co Ltd LED chip for increasing front light emitting rate and its fabricating method
TWM508801U (zh) * 2009-11-28 2015-09-11 Great Team Backend Foundry Inc 高散熱低成本之導線架結構改良
JP2012089570A (ja) * 2010-10-15 2012-05-10 Panasonic Corp 半導体装置
CN102751266B (zh) * 2011-04-21 2016-02-03 精材科技股份有限公司 芯片封装体及其形成方法
WO2012170463A1 (en) 2011-06-08 2012-12-13 Universal Display Corporation Heteroleptic iridium carbene complexes and light emitting device using them
JP5980504B2 (ja) * 2011-12-27 2016-08-31 株式会社ディスコ ウエーハの加工方法およびレーザー加工装置
JP6060509B2 (ja) * 2012-03-29 2017-01-18 大日本印刷株式会社 半導体素子の製造方法
JP6250429B2 (ja) * 2014-02-13 2017-12-20 エスアイアイ・セミコンダクタ株式会社 半導体装置およびその製造方法

Also Published As

Publication number Publication date
JP2015153874A (ja) 2015-08-24
US20150228504A1 (en) 2015-08-13
KR20150095586A (ko) 2015-08-21
JP6250429B2 (ja) 2017-12-20
KR102287698B1 (ko) 2021-08-09
TWI643267B (zh) 2018-12-01
US9887171B2 (en) 2018-02-06
CN104851851A (zh) 2015-08-19
CN104851851B (zh) 2018-12-11
US10236269B2 (en) 2019-03-19
US20180158792A1 (en) 2018-06-07

Similar Documents

Publication Publication Date Title
TWI643267B (zh) 半導體裝置及其製造方法
US9899239B2 (en) Carrier ultra thin substrate
US7863107B2 (en) Semiconductor device and manufacturing method of the same
JP2009529804A (ja) 半導体デバイスのパッケージング
KR20110015047A (ko) 포일계 반도체 패키지
JP2009105362A (ja) 半導体装置とその製造方法および半導体基板
US20180204786A1 (en) Die with metallized sidewall and method of manufacturing
KR101590453B1 (ko) 휨 개선을 위한 반도체 칩 다이 구조 및 방법
US7652385B2 (en) Semiconductor device and method of manufacturing the same
JP2018046289A (ja) 半導体装置およびその製造方法
TW200822315A (en) Sensor type semiconductor package and fabrication method thereof
JP2010103348A (ja) 半導体装置及びその製造方法
US10872845B2 (en) Process for manufacturing a flip chip semiconductor package and a corresponding flip chip package
JP2012164697A (ja) 電力用パワーモジュール及び電力用半導体装置
TW201705313A (zh) 半導體裝置之製造方法及半導體裝置
TW201246474A (en) Semiconductor device, semiconductor package
TW202008529A (zh) 半導體裝置及其製造方法
TWI740350B (zh) 半導體裝置之製造方法
JPH09172029A (ja) 半導体チップ及びその製造方法並びに半導体装置
CN114765162A (zh) 具有锥形金属涂层侧壁的半导体装置
TW201628150A (zh) 半導體裝置
US20230017286A1 (en) Semiconductor die with stepped side surface
US20080246166A1 (en) Semiconductor device and method of manufacturing same
JP2002164362A (ja) チップサイズ半導体装置及びその製造方法
KR20160102994A (ko) 리드프레임 표면을 처리하는 방법 및 처리된 리드프레임 표면을 구비한 장치

Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees