TW201351571A - 電子零件之安裝構造體及電子零件之安裝構造體之製造方法 - Google Patents

電子零件之安裝構造體及電子零件之安裝構造體之製造方法 Download PDF

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TW201351571A
TW201351571A TW102112902A TW102112902A TW201351571A TW 201351571 A TW201351571 A TW 201351571A TW 102112902 A TW102112902 A TW 102112902A TW 102112902 A TW102112902 A TW 102112902A TW 201351571 A TW201351571 A TW 201351571A
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Taiwan
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electrode
protruding electrodes
electronic component
protruding
semiconductor wafer
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TW102112902A
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English (en)
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TWI506739B (zh
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Takatoshi Osumi
Daisuke Sakurai
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Panasonic Corp
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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
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    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
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    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76885—By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
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Abstract

本發明之電子零件之安裝構造體包括使電子零件之複數個第1電極端子接合於電路基板之複數個第2電極端子之複數個接合部，上述複數個接合部包含：複數個第1突起狀電極，其等形成於上述複數個第1電極端子上；複數個第2突起狀電極，其等形成於上述複數個第2電極端子上；及複數個焊料部，其等使上述複數個第1突起狀電極接合於上述複數個第2突起狀電極；且上述複數個第1突起狀電極之端面之面積大於上述複數個第2突起狀電極之端面之面積，自上述電路基板露出之上述複數個第2電極端子之面積中包含大於上述複數個第2突起狀電極之底面之面積。

Description

電子零件之安裝構造體及電子零件之安裝構造體之製造方法
本發明係關於一種包含電路基板、及安裝於該電路基板上之半導體晶片等電子零件的電子零件之安裝構造體。
包含電路基板、及安裝於該電路基板上之LSI(Large Scale Integration，大型積體電路)等半導體晶片的安裝構造體之一種係藉由覆晶(flip chip)安裝法而製造。於覆晶安裝法中，於在半導體晶片之複數個電極端子上分別形成焊接凸塊等突起狀電極後，將該半導體晶片面朝下地安裝於電路基板上。詳細而言，一面對半導體晶片與電路基板中之至少一者進行加熱，一面將半導體晶片上之複數個突起狀電極壓接於電路基板之複數個電極端子。
一般而言，形成焊接凸塊之方法包括以下步驟：以分配裝置、絲網印刷法、或電鍍法等向半導體晶片之複數個電極端子上分別供給焊料；及利用回焊爐等將半導體晶片加熱至焊料之熔點以上。於使用焊接凸塊之情形時，在半導體晶片與電路基板之間之空隙中填充密封樹脂，而加強半導體晶片上之複數個突起狀電極與電路基板之複數個電極端子之間之接合的強度。
除焊接凸塊以外，亦有含有金或銅等之突起狀電極。含有金或銅等之突起狀電極係藉由例如電鍍法而形成。於使用含有金或銅等之突起狀電極之情形時，一般而言，於將包含接著劑、及混入至該接著劑中之金屬粒子之各向異性導電膜配置於半導體晶片與電路基板之間 後，將半導體晶片上之複數個突起狀電極朝向電路基板之複數個電極端子加壓。
一般而言，半導體晶片之複數個電極端子係於半導體晶片之外周部配置成1行、或以2行配置成鋸齒狀。另一方面，為了謀求半導體晶片之高密度化及半導體晶片之多銷化，而推進電極端子間距離之狹小化(窄間距化)及電極面積之縮小化，尤其是窄間距化之進展顯著。因此，於如上所述般將複數個電極端子於半導體晶片之外周部以1行或2行進行排列之情形時，存在如下情況：電極端子間發生短路，或因半導體晶片與電路基板之間之熱膨脹係數之差所引起之熱應力而導致產生連接不良。
具體而言，於使用焊接凸塊之情形時，有產生所謂之橋接不良而於電極端子間發生短路不良之虞。橋接不良之起因在於：於覆晶安裝時，已熔融之焊料產生變形，藉由焊料之表面張力而使鄰接之焊接凸塊彼此連接。因此，若上述窄間距化發展，則變得易於產生橋接不良。又，因半導體晶片與電路基板之間之熱膨脹係數之差所引起之熱應力而導致產生之連接不良之起因在於：插入至半導體晶片與電路基板之間之空隙之密封樹脂不會遍及該空隙之整個區域，而僅填充至該空隙之一部分區域。因此，若上述窄間距化發展，則密封樹脂之流動會受到阻礙，而變得易於產生上述由熱應力引起之連接不良。
如上所述，若電極端子間距離之狹小化(窄間距化)發展，則存在於電極端子間發生短路、或因半導體晶片與電路基板之間之熱膨脹係數之差所引起之熱應力而導致產生連接不良的情況。因此，為了擴大電極端子間距離，而將複數個電極端子於半導體晶片之面內(區域內)配置成矩陣狀(格子狀)。藉由將複數個電極端子於半導體晶片之面內配置成矩陣狀(格子狀)，而與僅在半導體晶片之外周部將複數個電極端子以1行或2行進行排列之情形相比，配置複數個電極端子之區域之 面積變大，故而可擴大電極端子間距離。
然而，近年來，於將複數個電極端子配置成矩陣狀(格子狀)之半導體晶片中，電極端子間距離之狹小化(窄間距化)之進展亦變得顯著。因此，即便於將複數個電極端子於半導體晶片之面內配置成矩陣狀(格子狀)之情形時，亦於電極端子間發生短路不良。
為了解決此種問題，例如於日本專利特開平9-97791號公報中，提出有於在覆晶安裝時不熔融之具有高熔點之下層電極上形成包含焊料之上層電極而成的雙層構造之突起狀電極。根據該突起狀電極，焊料之量較僅包含焊料之焊接凸塊減少，且焊料於覆晶安裝時向平面方向之突出量減少，故而橋接不良之產生減少。
然而，近年來，半導體裝置之薄化之要求變得非常嚴格，為了應對其薄化之要求，半導體晶片之厚度變為50μm以下，且半導體晶片與電路基板之間之距離變為25μm以下。其結果為，半導體晶片之內部層間之熱膨脹係數之差及半導體晶片與電路基板之間之熱膨脹係數之差所引起之較大之翹曲產生於半導體晶片。而且，可知因半導體晶片產生較大之翹曲，而導致即便於使用在高熔點之下層電極之頂部設置包含焊料之上層電極而成的雙層構造之突起狀電極之情形時，亦會產生以下說明之問題。
圖7至圖9係用以說明挪用日本專利特開平9-97791號公報所記載之雙層構造之突起狀電極之安裝構造體的剖面圖。
如圖7所示，於半導體晶片101之各電極端子102上設置有雙層構造之突起狀電極。各電極端子102上之突起狀電極包含於覆晶安裝時不熔融之具有高熔點之圓柱狀下層電極103、及形成於該圓柱狀下層電極103上之上層電極，且該上層電極包含焊料104。又，於半導體晶片101上形成有用以保護設置有複數個電極端子102之整個面之保護膜 105。於該保護膜105中，於複數個電極端子102相對應地形成有複數個開口部，且複數個圓柱狀下層電極103自該複數個開口部突出。
於電路基板106之各電極端子107上僅形成有於覆晶安裝時不熔融之具有高熔點之圓柱狀電極108。又，於電路基板106上形成有用以保護設置有複數個電極端子107之整個面之保護膜109。於該保護膜109中，與複數個電極端子107相對應地形成有複數個開口部，且複數個圓柱狀電極108自該複數個開口部突出。
於進行覆晶安裝時，一面對半導體晶片101及電路基板106中之至少一者進行加熱，一面將半導體晶片101上之複數個圓柱狀下層電極103朝向電路基板106上之複數個圓柱狀電極108加壓，從而使焊料104熔融。藉此，熔融之焊料104擴散接合於電路基板106上之複數個圓柱狀電極108之各者，從而於電路基板106上搭載半導體晶片101。
然而，通常，設置於半導體晶片101上之複數個圓柱狀下層電極103之直徑與設置於電路基板106上之複數個圓柱狀電極108之直徑近似或相同。因此，如圖7所示，若半導體晶片101中產生翹曲，而導致於半導體晶片101之面內半導體晶片101與電路基板106之間之距離變得不均勻，則會產生圖8及圖9所示之問題。即，有如下之虞：如圖8所示，於因產生於半導體晶片101之翹曲而導致半導體晶片101與電路基板106之間之距離增加，從而使焊料104a被拉伸之區域內，相對於半導體晶片101與電路基板106之間之距離，焊料104a之量不足，而使半導體晶片101之電極端子102a與電路基板106之電極端子107a之間之電性導通不良化。視情形會有半導體晶片101之電極端子102a與電路基板106之電極端子107a未電性連接之虞。另一方面，於因產生於半導體晶片101之翹曲而導致半導體晶片101與電路基板106之間之距離減少之區域內，如圖9所示，相對於半導體晶片101與電路基板106之間之距離，焊料104b之量變得過剩，焊料104b向平面方向之突出量增 加而產生橋接不良。
本發明之目的之一在於提供一種即便於將具有翹曲之半導體晶片等電子零件安裝於電路基板之情形時，亦可確保較高之連接可靠性之電子零件之安裝構造體。又，本發明之另一目的之一在於提供一種製造電子零件之安裝構造體之方法，該電子零件之安裝構造體即便於將具有翹曲之半導體晶片等電子零件安裝於電路基板之情形時，亦可確保較高之連接可靠性。
為了達成上述目的，本發明之電子零件之安裝構造體亦可設為包括：電子零件，其具有複數個第1電極端子；電路基板，其具有與上述複數個第1電極端子相對應之複數個第2電極端子；及複數個接合部，其等使上述複數個第1電極端子接合於上述複數個第2電極端子；且上述複數個接合部包含：複數個第1突起狀電極，其等形成於上述複數個第1電極端子上；複數個第2突起狀電極，其等形成於上述複數個第2電極端子上；及複數個焊料部，其等使上述複數個第1突起狀電極接合於上述複數個第2突起狀電極；且上述複數個第1突起狀電極之端面之面積大於上述複數個第2突起狀電極之端面之面積，自上述電路基板露出之上述複數個第2電極端子之面積中包含大於上述複數個第2突起狀電極之底面之面積。
本發明之電子零件之安裝構造體亦可設為：對應於上述電子零件之外周部而配置之第2電極端子自上述電路基板露出之面積小於對應於上述電子零件之中央部而配置之第2電極端子自上述電路基板露出之面積。
本發明之電子零件之安裝構造體亦可設為：上述複數個第1突起狀電極分別具有柱狀之形狀，上述複數個第2突起狀電極分別具有柱狀之形狀。
本發明之電子零件之安裝構造體亦可設為：上述複數個焊料部 係配置於上述複數個第2突起狀電極之周圍。
本發明之電子零件之安裝構造體亦可設為：第1突起狀電極之前端之面積、使該第1突起狀電極接合於第2突起狀電極之焊料部之體積、該第2突起狀電極之前端或底面之面積、及該第2突起狀電極之高度滿足下式之關係。
焊料部之體積≦(第1突起狀電極之前端之面積-第2突起狀電極之前端或底面之面積)×第2突起狀電極之高度
本發明之電子零件之安裝構造體亦可設為：上述複數個第1突起狀電極分別具有圓柱狀之形狀，上述複數個第2突起狀電極分別具有圓柱狀之形狀，上述複數個第2突起狀電極之高度及直徑滿足高度≦直徑之關係。
本發明之電子零件之安裝構造體亦可設為：上述複數個第1突起狀電極分別具有圓柱狀之形狀，上述複數個第2突起狀電極分別具有圓柱狀之形狀，上述複數個第2突起狀電極之直徑為上述複數個第1突起狀電極之直徑之0.4倍~0.7倍之大小。
本發明之電子零件之安裝構造體亦可設為：上述複數個第1突起狀電極分別含有銅。
本發明之電子零件之安裝構造體亦可設為：上述複數個第2突起狀電極分別含有銅或鎳。
本發明之電子零件之安裝構造體亦可設為：上述複數個第2突起狀電極分別具備含有金之表層。
本發明之電子零件之安裝構造體亦可設為：上述複數個焊料部分別含有錫。
又，為了達成上述目的，本發明之電子零件之安裝構造體之製造方法亦可設為：其係製造如下電子零件之安裝構造體之方法，該電子零件之安裝構造體包括：電子零件，其具有複數個第1電極端子； 電路基板，其具有與上述複數個第1電極端子相對應之複數個第2電極端子；及複數個接合部，其等使上述複數個第1電極端子接合於上述複數個第2電極端子；該電子零件之安裝構造體之製造方法包括以下步驟：於上述複數個第1電極端子上形成複數個第1突起狀電極；於上述複數個第2電極端子上形成複數個第2突起狀電極；對上述複數個第1突起狀電極分別供給焊料；及於使上述焊料分別熔融之狀態下，使上述複數個第1突起狀電極之前端與上述複數個第2突起狀電極之前端接觸，而形成上述複數個接合部。
本發明之電子零件之安裝構造體之製造方法亦可設為：於形成上述複數個接合部時，自上述複數個第2突起狀電極之前端對上述複數個第1突起狀電極之前端施加壓力，藉此於上述複數個第1突起狀電極之前端分別形成凹陷。
根據本發明，即便於將具有翹曲之半導體晶片等電子零件安裝於電路基板之情形時，亦可確保良好之連接可靠性。
1‧‧‧半導體晶片
2‧‧‧電路基板
3‧‧‧電極端子
3a‧‧‧電極端子
3b‧‧‧電極端子
4‧‧‧電極端子
4a‧‧‧電極端子
4b‧‧‧電極端子
5‧‧‧突起狀電極
5a‧‧‧突起狀電極
5b‧‧‧突起狀電極
6‧‧‧突起狀電極
6a‧‧‧突起狀電極
6b‧‧‧突起狀電極
7‧‧‧焊料部
7a‧‧‧焊料部
7b‧‧‧焊料部
7c‧‧‧焊料
8‧‧‧保護膜
9‧‧‧保護膜
101‧‧‧半導體晶片
102‧‧‧電極端子
102a‧‧‧電極端子
102b‧‧‧電極端子
103‧‧‧下層電極
103a‧‧‧下層電極
103b‧‧‧下層電極
104‧‧‧焊料
104a‧‧‧焊料
104b‧‧‧焊料
105‧‧‧保護膜
106‧‧‧電路基板
107‧‧‧電極端子
107a‧‧‧電極端子
107b‧‧‧電極端子
108‧‧‧圓柱狀電極
108a‧‧‧圓柱狀電極
108b‧‧‧圓柱狀電極
109‧‧‧保護膜
圖1係用以說明本發明之實施形態中之電子零件之安裝構造體的剖面圖。
圖2係用以說明本發明之實施形態中之電子零件之安裝構造體所包含之接合部的放大剖面圖。
圖3係用以說明本發明之實施形態中之電子零件之安裝構造體所包含之接合部的放大剖面圖。
圖4係表示本發明之實施形態中之電子零件之安裝構造體之製造方法的流程圖。
圖5A係用以說明本發明之實施形態中之電子零件之安裝構造體之製造方法的步驟剖面圖。
圖5B係用以說明本發明之實施形態中之電子零件之安裝構造體 之製造方法的步驟剖面圖。
圖5C係用以說明本發明之實施形態中之電子零件之安裝構造體之製造方法的步驟剖面圖。
圖5D係用以說明本發明之實施形態中之電子零件之安裝構造體之製造方法的步驟剖面圖。
圖6A係用以說明本發明之實施形態中之電子零件之安裝構造體之製造方法的步驟剖面圖。
圖6B係用以說明本發明之實施形態中之電子零件之安裝構造體之製造方法的步驟剖面圖。
圖6C係用以說明本發明之實施形態中之電子零件之安裝構造體之製造方法的步驟剖面圖。
圖7係用以說明先前之安裝構造體之剖面圖。
圖8係用以說明先前之安裝構造體之接合部之放大剖面圖。
圖9係用以說明先前之安裝構造體之接合部之放大剖面圖。
以下，一面參照圖式一面對本發明之實施形態進行說明。然而，為了易於理解，圖式係模式性地對各個構成要素進行圖示。又，所圖示之各構成要素之形狀、或厚度、長度、個數等係出於圖式製作之便利，與實際有所不同。再者，以下之實施形態中所示之各構成要素之材質、或形狀、尺寸等係一例而並無特別限定，可在實質上不脫離本發明之效果之範圍內進行各種變更。
於以下之實施形態中，作為電子零件之安裝構造體之一例，對包含電路基板、及安裝於該電路基板上之半導體晶片之安裝構造體進行說明。半導體晶片為電子零件之一例，選自例如Si(矽)製之半導體晶片或GaAs(砷化鎵)製之半導體晶片等。然而，電子零件並不限定於半導體晶片。例如，於電子零件為電容器、或線圈、電阻等被動零件 之情形時，亦可獲得與以下之實施形態相同之效果。
圖1係用以說明本實施形態中之電子零件之安裝構造體之剖面圖。
如圖1所示，半導體晶片1包含與電路基板2相對向之面、及複數個電極端子(第1電極端子)3。複數個電極端子3係於與電路基板2相對向之面之內側之層呈矩陣狀(格子狀)以等間隔配置。詳細而言，於與電路基板2相對向之面之內側設置有多層配線層，於該多層配線層之最表面設置有複數個電極端子3。多層配線層包含例如含有Cu(銅)或Al(鋁)等之未圖示之微細配線層、及例如含有低介電常數(low-k)層或超低介電常數(Ultra low-k)層等脆弱之低介電常數絕緣層之未圖示之層間絕緣膜。
低介電常數絕緣層之膜厚為每1層數百nm。各電極端子3之材料係使用例如Al-Cu系、Al-Si-Cu系、或Al-Si系等鋁合金。或者，各電極端子3含有Cu或Al等。於本實施形態中，對選擇Al作為各電極端子3之材料之情形進行說明。
電路基板2包含以與半導體晶片1之複數個電極端子3相對向之方式配置之複數個電極端子(第2電極端子)4。電路基板2之基材係選自例如矽、多晶矽、或玻璃等。各電極端子4之材料係使用例如Al-Cu系、Al-Si-Cu系、或Al-Si系等鋁合金。或者，各電極端子4含有Cu或Al等。於本實施形態中，對選擇Al作為各電極端子4之材料之情形進行說明。
於半導體晶片1之各電極端子3上設置有圓柱狀或角柱狀等柱狀之突起狀電極(第1突起狀電極)5。於電路基板2之各電極端子4上亦設置有圓柱狀或角柱狀等柱狀之突起狀電極(第2突起狀電極)6。
半導體晶片1上之複數個突起狀電極5係藉由複數個焊料部7而電性及機械地連接於電路基板2上之複數個突起狀電極6。因此，將半導 體晶片1之複數個電極端子3接合於電路基板2之複數個電極端子4之複數個接合部包含複數個突起狀電極5、複數個突起狀電極6、及複數個焊料部7。該複數個接合部係於半導體晶片1與電路基板2之間以等間隔配置成矩陣狀(格子狀)。
各突起狀電極5含有例如Cu(銅)。或者，各突起狀電極5之材料亦可選自例如Ni-P(磷)合金、Ni-B(硼)合金或Ni等。或者，各突起狀電極5亦可為例如Ni/Pd(鈀)/Au(金)等之3層構造。
各突起狀電極6含有例如Cu(銅)。或者，各突起狀電極6之材料亦可選自例如Ni-P(磷)合金、Ni-B(硼)合金或Ni等。或者，各突起狀電極6亦可為例如Ni/Pd(鈀)/Au(金)等之3層構造。
各焊料部7之材質係使用例如Sn-Ag系、Sn-Ag-Cu系、Sn-Zn(鋅)系、Sn-Zn-Bi(鉍)系、Sn-Pb(鉛)系、Sn-Bi系、Sn-Ag-Bi-In(銦)系、或Sn-In系等焊料。或者，各焊料部7含有In或Sn等。
於本實施形態中，對半導體晶片1上之各突起狀電極5之主成分為Cu(銅)、電路基板2上之各突起狀電極6之主成分為Ni(鎳)、各焊料部7之主成分為Sn(錫)之情形進行說明。
半導體晶片1具備以保護與電路基板2相對向之面之方式形成之保護膜8，且於該保護膜8中，對應於複數個電極端子3而形成有複數個開口部。而且，複數個電極端子3各自之表面之至少一部分自該保護膜8之各開口部露出，於自保護膜8露出之複數個電極端子3上分別設置有突起狀電極5。因此，突起狀電極5分別自保護膜8之複數個開口部突出。
同樣地，電路基板2具備與半導體晶片1相對向之面、及以保護與該半導體晶片1相對向之面之方式形成之保護膜9，且於該保護膜9中，對應於複數個電極端子4而形成有複數個開口部。而且，複數個電極端子4各自之表面之至少一部分自該保護膜9之各開口部露出，於 自保護膜9露出之複數個電極端子4上分別設置有突起狀電極6。因此，突起狀電極6分別自保護膜9之複數個開口部突出。
保護膜8及9含有例如SiN(氮化矽)或聚醯亞胺等。於本實施形態中，對選擇SiN作為保護膜8及9之材料之情形進行說明。
半導體晶片1上之複數個突起狀電極5之頭頂部(端面)之面積大於電路基板2上之複數個突起狀電極6之頭頂部(端面)之面積。因此，於各突起狀電極5具有圓柱狀之形狀、且各突起狀電極6具有圓柱狀之形狀之情形時，半導體晶片1上之複數個突起狀電極5之頭頂部(端面)之直徑大於電路基板2上之複數個突起狀電極6之頭頂部(端面)之直徑。
電路基板2之保護膜9中所形成之複數個開口部之面積(自電路基板2露出之複數個電極端子4之面積)包含大於電路基板2上之複數個突起狀電極6之底面之面積。於複數個接合部之高度包含不同高度之情形時，較佳為至少電路基板2之保護膜9之複數個開口部之中，配置有最低之接合部之開口部具有大於自該開口部突出之突起狀電極之底面之面積。或者，如圖3所示，較佳為於電路基板2之保護膜9之複數個開口部之中，至少配置有突起狀電極5b與突起狀電極6b之頭頂部彼此接觸之接合部的開口部具有大於自該開口部突出之突起狀電極6b之底面之面積。然而，電路基板2之保護膜9之複數個開口部之中除配置有最高之接合部之開口部以外之複數個開口部亦可具有大於自該等開口部分別突出之突起狀電極之底面之面積。或者，亦可為配置有更高之接合部之保護膜9之開口部具有較配置有更低之接合部之保護膜9之開口部窄之面積。或者，亦可為電路基板2之保護膜9之所有開口部具有大於自該等開口部分別突出之突起狀電極6之底面之面積。
如圖1所示，於設置於半導體晶片1之外周部之複數個接合部高於設置於半導體晶片1之中央部之複數個接合部之情形時，對應於半導體晶片1之外周部而形成之保護膜9之複數個開口部亦可具有較對應 於半導體晶片1之中央部而形成之保護膜9之複數個開口部小之面積。又，如圖1所示，於隨著朝向半導體晶片1之端半導體晶片1與電路基板2之間之距離逐漸增加之情形時，配置有更高之接合部之保護膜9之開口部亦可具有較配置有更低之接合部之保護膜9之開口部小之面積。
例如，於將具有矩形狀之外形之半導體晶片1覆晶安裝於電路基板2之情形時，半導體晶片1成為向下凸出地翹曲之狀態。其原因在於：於在覆晶安裝製程中將熔融焊料冷卻之過程中，熱應力集中於半導體晶片1之外形之各角隅部(曲折部)。該熱應力係由半導體晶片1與電路基板2之間之彈性模數及線膨脹係數各自之差、半導體晶片1之內部層間之彈性模數及線膨脹係數各自之差、以及電路基板2之內部層間之彈性模數及線膨脹係數各自之差所引起而產生。若如此般半導體晶片1發生翹曲，則形成於半導體晶片1之外形之各角隅部附近之接合部會變得高於形成於半導體晶片1之中央部之複數個接合部。其結果為，如圖2所示，各接合部所包含之焊料部7之中，位於半導體晶片1之外形之各角隅部附近之焊料部7a被拉伸。然而，根據本實施形態之安裝構造體，由於電路基板2上之複數個突起狀電極6之前端之面積小於半導體晶片1上之複數個突起狀電極5之前端之面積，故而即便如圖2所示般焊料部7a被拉伸，形成焊料部7a之焊料亦潤濕擴散至電路基板2上之突起狀電極6a之側面。由此，於半導體晶片1之電極端子3a與電路基板2之電極端子4a之間難以產生電性導通之不良化。另一方面，於半導體晶片1之中央部，如圖3所示，半導體晶片1上之突起狀電極5b與電路基板2上之突起狀電極6b之頭頂部彼此接觸。因此，形成焊料部7b之焊料自突起狀電極5b之頭頂部與突起狀電極6b之頭頂部之間被擠出。然而，根據本實施形態之安裝構造體，電路基板2上之複數個突起狀電極6之前端之面積小於半導體晶片1上之複數個突起狀 電極5之前端之面積。又，如圖3所示，於電路基板2之保護膜9之複數個開口部之中，配置有突起狀電極5b與突起狀電極6b之頭頂部彼此接觸之接合部之開口部具有大於自該開口部突出之突起狀電極6b之底面的面積。藉此，自突起狀電極5b之頭頂部與突起狀電極6b之頭頂部之間擠出之焊料潤濕擴散至突起狀電極6b之側面、及自保護膜9露出之電極端子4b之表面。由此，焊料部7b難以自半導體晶片1上之突起狀電極5b之底面之投影區域溢出，從而難以產生橋接不良。
於本實施形態中，半導體晶片1之外形為8mm×8mm之矩形狀，半導體晶片1之厚度為0.05mm。另一方面，電路基板2之外形為16mm×16mm之矩形狀，電路基板2之厚度為0.15mm。
又，於本實施形態中，半導體晶片1之各電極端子3於俯視時為直徑25μm之圓形狀。同樣地，電路基板2之各電極端子4於俯視時為直徑25μm之圓形狀。又，半導體晶片1之各電極端子3之厚度為0.5~2.0μm。同樣地，電路基板2之各電極端子4之厚度為0.5~2.0μm。半導體晶片1之電極端子間距離(鄰接之電極端子3、3之中心間距離)為40μm。由此，電路基板2之電極端子間距離(鄰接之電極端子4、4之中心間距離)亦為40μm。
又，於本實施形態中，半導體晶片1上之各突起狀電極5為直徑20μm、高度20μm之圓柱狀，鄰接之突起狀電極5、5之中心線間之距離為40μm。另一方面，電路基板2上之各突起狀電極6為直徑10μm、高度10μm之圓柱狀，鄰接之突起狀電極6、6之中心線間之距離為40μm。較佳為就電路基板2上之各突起狀電極6之直徑與高度而言，直徑成為高度以上。又，較佳為使電路基板2上之複數個突起狀電極6之直徑為半導體晶片1上之複數個突起狀電極5之直徑之0.4倍~0.7倍的大小。
又，於本實施形態中，形成於半導體晶片1之保護膜8之各開口 部為直徑20μm之圓形狀。另一方面，電路基板2之保護膜9之各開口部之形狀亦為圓形狀，對應於半導體晶片1之中央部而設置之開口部之直徑為20μm。又，對應於半導體晶片1之外形之各角隅部(曲折部)附近而設置之保護膜9之開口部之直徑為10μm。於保護膜9之複數個開口部中，亦可設定隨著自對應於半導體晶片1之中央部之區域朝向對應於半導體晶片1之外形之角隅部附近之區域逐漸變小之直徑。半導體晶片1之保護膜8與電路基板2之保護膜9各自之膜厚為0.5~5.0μm左右。
繼而，對本實施形態中之電子零件之安裝構造體之製造方法進行說明。圖4表示本實施形態中之電子零件之安裝構造體之製造方法的流程圖，圖5A~圖5D及圖6A~圖6C分別係用以說明本實施形態中之電子零件之安裝構造體之製造方法的步驟剖面圖。
於本實施形態中，於分別設置於晶圓上所形成之複數個半導體晶片1上之複數個電極端子3上，藉由電鍍法批次形成有複數個突起狀電極5。具體而言，首先，如圖5A所示，於自含有鋁(Al)之各電極端子3之表面去除雜質後，將例如含有TiW/Cu之UBM(Under Barrier Metal，底障金屬)濺鍍於晶圓之整個面(露出有複數個電極端子3之面之整個面)。其次，於將光阻劑塗佈於晶圓之整個面(露出有複數個電極端子3之面之整個面)後，進行曝光及顯影。繼而，如圖5B所示，於自經顯影之圖案(光阻劑之圖案)露出之各UBM上鍍銅(Cu)，藉此於各電極端子3上形成突起狀電極5(圖4之步驟S1)。繼而，如圖5C所示，於各突起狀電極5上鍍敷焊料7c(圖4之步驟S2)。繼而，去除光阻劑，其後，蝕刻去除不需要之UBM。繼而，如圖5D所示，以達到焊料之熔點以上之方式藉由回焊爐對晶圓進行加熱，從而使焊料7c熔融。藉此，各突起狀電極5上之焊料7c之表面成為具有曲率之形狀、例如半球狀(圖4之步驟S3)。再者，亦可於在晶圓上塗佈焊劑後，將晶圓投 入至例如N2回焊爐等中，於N2等惰性氣體氛圍下使晶圓升溫至焊料之熔點以上，藉此使焊料7c熔融。或者，亦可將晶圓投入至還原回焊爐中，於例如甲酸或氫等還原氛圍下使晶圓升溫至焊料之熔點以上，藉此使焊料7c熔融。
電路基板2之各電極端子4上之突起狀電極6亦與半導體晶片1之各電極端子3上之突起狀電極5同樣地藉由電鍍法而形成。具體而言，首先，如圖6A所示，於自含有鋁(Al)之各電極端子4之表面去除雜質後，將例如含有TiW/Cu之UBM濺鍍於露出有複數個電極端子4之電路基板2之面之整個面。其次，於將光阻劑塗佈於露出有複數個電極端子4之電路基板2之面之整個面後，進行曝光及顯影。繼而，如圖6B所示，於自經顯影之圖案(光阻劑之圖案)露出之各UBM上鍍Ni，藉此於各電極端子4上形成突起狀電極6(圖4之步驟S4)。繼而，去除光阻劑，其後，閃熔鍍敷含有金(Au)之抗氧化膜。藉此，於電路基板2上之各突起狀電極6之表面形成含有Au之抗氧化膜。繼而，蝕刻去除不需要之抗氧化膜及不需要之UBM。
於在半導體晶片1之各電極端子3上形成突起狀電極5、在電路基板2之各電極端子4上形成突起狀電極6後，如圖6C所示，一面對半導體晶片1與電路基板2中之至少一者進行加熱，一面將半導體晶片1上之複數個突起狀電極5朝向電路基板2上之複數個突起狀電極6加壓。藉此，將半導體晶片1覆晶安裝於電路基板2上(圖4之步驟S5)。
具體而言，首先，對半導體晶片1與電路基板2中之至少一者進行加熱，使供給至半導體晶片1之各突起狀電極5上之焊料7c升溫至焊料之熔點以上之溫度(例如220~260℃)。藉由該加熱處理使焊料7c熔融。
繼而，將半導體晶片1朝向電路基板2加壓，從而使半導體晶片1上之複數個突起狀電極5與電路基板2上之複數個突起狀電極6之頭頂 部彼此接觸。藉此，熔融焊料7c變形，從而熔融焊料7c潤濕擴散至電路基板2上之各突起狀電極6之含有Au之表面。半導體晶片1繼續朝向電路基板2加壓，直至熔融焊料7潤濕擴散至電路基板2上之各突起狀電極6之表面為止。藉此，於電路基板2上之各突起狀電極6之周圍配置焊料部7。又，於該過程中，半導體晶片1上之各突起狀電極5中所含有之Cu原子擴散至熔融焊料7c內，電路基板2上之各突起狀電極6中所含有之Ni原子擴散至熔融焊料7c內。再者，於未設置在各突起狀電極6之表面之整個面上使Ni原子擴散至熔融焊料7c內之後續步驟之情形時，半導體晶片1繼續朝向電路基板2加壓，直至Ni原子於各突起狀電極6之表面之整個面上擴散至熔融焊料7c內為止。
本實施形態中之電子零件之安裝構造體之製造方法包括如下步驟：使焊料7c熔融，而使包含構成半導體晶片1上之各突起狀電極5之金屬(銅)與構成焊料7c之金屬(錫)的合金層及包含構成電路基板2上之各突起狀電極6之金屬(鎳)與構成焊料7c之金屬(錫)的合金層分別成長。藉此，自半導體晶片1上之各突起狀電極5之頭頂部成長之合金層、與自電路基板2上之各突起狀電極6之頭頂部及側面分別成長之合金層分別由焊料包圍。
繼而，將半導體晶片1與電路基板2冷卻至焊料之凝固點以下。藉此，使焊料7c凝固，如圖6C所示，形成將半導體晶片1之複數個電極端子3連接於電路基板2之複數個電極端子4之複數個接合部(圖4之步驟S5)。進而，藉由將半導體晶片1與電路基板2冷卻至常溫，而獲得電子零件之安裝構造體。
關於以此方式製造之安裝構造體，由於在覆晶安裝製程中之熔融焊料7c之冷卻過程中，例如，如圖1所示般半導體晶片1之外周部翹起，故而包含整體向下凸出地翹曲之半導體晶片1。因此，配置於半導體晶片1之外形之各角隅部(曲折部)附近之接合部變得高於配置於 半導體晶片1之中央部之接合部。其結果為，於半導體晶片1之外形之各角隅部附近，如圖2所示，半導體晶片1上之突起狀電極5a之頭頂部與電路基板2上之突起狀電極6a之頭頂部之間之距離增加，而焊料部7a被拉伸。
於本實施形態之安裝構造體中，配置有預想到高度會因半導體晶片1發生翹曲而增加之接合部之保護膜9之開口部之直徑(開口部之面積)係根據該預測之接合部之高度增加量而設定。具體而言，所預測之接合部之高度之增加量越大，則該開口部之直徑設定得越小。由於焊料7c不潤濕擴散至電路基板2之保護膜9之表面，故而自設定有較小之直徑(面積)之保護膜9之開口部露出的電極端子之表面中焊料7c所潤濕之面積變得小於自設定有較大之直徑(面積)之保護膜9之開口部露出的電極端子之表面中焊料7c所潤濕之面積。因此，焊料7c向自保護膜9之開口部露出之電極端子之潤溼擴散得到抑制，該保護膜9係配置有高度因半導體晶片1發生翹曲而增加之接合部。藉此，因半導體晶片1發生翹曲而被拉伸之焊料7c難以被扯斷，且該焊料7c充分地潤濕擴散至被供給有該焊料7c之半導體晶片1上之突起狀電極所具有之頭頂部(端面)、以及與該突起狀電極5相對向之電路基板2上之突起狀電極所具有之頭頂部(端面)及側面的狀態得以保持。
又，於本實施形態之安裝構造體中，由於電路基板2上之複數個突起狀電極6之直徑(截面面積)小於半導體晶片1上之複數個突起狀電極5之直徑(截面面積)，故而如圖3所示，於對應於半導體晶片1之中央部之區域內，形成焊料部7b之焊料潤濕擴散至電路基板2上之突起狀電極6b之側面。又，如圖3所示，於對應於半導體晶片1之中央部之區域內，電路基板2之保護膜9之開口部之直徑(開口部之面積)大於電路基板2上之突起狀電極6b之直徑(突起狀電極6b之底面之面積)，故而形成焊料部7b之焊料亦潤濕擴散至電路基板2之電極端子4b之表 面。因此，於對應於半導體晶片1之中央部之區域內，焊料部7b難以自半導體晶片1上之突起狀電極5b之底面之投影區域溢出。由此，減少了橋接不良之產生。
又，即便於具有較對應於半導體晶片1之中央部而設置之保護膜9之開口部小之直徑且自保護膜9之開口部突出的突起狀電極之頭頂部於半導體晶片1發生翹曲前接觸於與該突起狀電極相對向之半導體晶片1上之突起狀電極之頭頂部之情形時，熔融焊料7c自該半導體晶片1上之突起狀電極之底面之投影區域溢出之量亦難以達到引起橋接不良之溢出量以上。其原因在於：電路基板2上之複數個突起狀電極6之直徑(截面面積)小於半導體晶片1上之複數個突起狀電極5之直徑(截面面積)，且熔融焊料7c潤濕擴散至電路基板2上之各突起狀電極6之側面。
如上所述，根據本實施形態，即便因在半導體晶片1與電路基板2之間彈性模數及線膨脹係數中之至少一者不同而導致於在覆晶安裝製程中將熔融焊料冷卻之過程中半導體晶片1產生翹曲，半導體晶片1之複數個電極端子3與電路基板2之複數個電極端子4之間亦難以產生電性未連接之情況，又，亦難以產生橋接不良。由此，確保較高之連接可靠性。其原因在於：自半導體晶片1上之複數個突起狀電極5之頭頂部(端面)至電路基板2上之複數個突起狀電極6之側面確保了焊料之潤濕。又，於產生急遽之溫度差之使用環境下，有時半導體晶片1亦會產生翹曲。然而，根據本實施形態，由於自半導體晶片1上之複數個突起狀電極5之頭頂部(端面)至電路基板2上之複數個突起狀電極6之側面確保了焊料之潤濕，故而即便於在產生急遽之溫度差之使用環境下半導體晶片1產生有翹曲之情形時，半導體晶片1之複數個電極端子3與電路基板2之複數個電極端子4之間亦難以產生電性未連接之情況，又，亦難以產生橋接不良。
因此，根據本實施形態，於具有藉由複數個微細焊料接合體將半導體晶片1之複數個電極端子3電性及機械地接合於電路基板2之複數個電極端子4之構造的安裝構造體中，即便使半導體晶片1與電路基板2中之至少一者薄化，亦可確保較高之連接可靠性。
再者，雖未進行圖示，但亦可藉由例如分配裝置於半導體晶片1與電路基板2之間之空隙內填充密封樹脂。藉由該密封樹脂使半導體晶片1之複數個電極端子3分別承受之應力降低，故而進一步提高連接可靠性。
此處，對各焊料部7之體積(供給至各突起狀電極5之焊料7c之量)進行說明。各焊料部7之體積較佳為與設置有各焊料部7之接合部所包含之突起狀電極5及6各自之尺寸之間滿足下式之關係。
焊料部7之體積≦(半導體晶片1上之突起狀電極5之頭頂部之面積-電路基板2上之突起狀電極6之底面之面積)×電路基板2上之突起狀電極6之高度
若為滿足上述式之關係之接合部，則即便該接合部所包含之突起狀電極5與突起狀電極6之頭頂部彼此接觸，焊料部7亦不會自該突起狀電極5之底面之投影區域溢出。因此，可確實地防止橋接不良之產生，從而確保更高之連接可靠性。
又，於所有接合部滿足上述式之關係之情形時，即便以半導體晶片1上之複數個突起狀電極5與電路基板2上之複數個突起狀電極6之頭頂部彼此全部接觸之方式，將半導體晶片1朝向電路基板2加壓，亦能防止橋接不良。由此，無需控制半導體晶片1之搭載高度，故而可縮短半導體晶片1向電路基板2搭載所耗費之時間。
再者，亦可以半導體晶片1上之複數個突起狀電極5與電路基板2上之複數個突起狀電極6之頭頂部彼此不接觸之方式，於半導體晶片1之搭載高度受到控制之狀態下，執行焊料7c之熔融及冷卻。於此情形 時，因半導體晶片1產生翹曲，而導致形成於半導體晶片1之中央部之接合部之高度減少，形成於半導體晶片1之外形之各角隅部附近之接合部之高度增加。然而，根據本實施形態之安裝構造體，如上所述，因半導體晶片1產生翹曲而被拉伸之焊料7c難以被扯斷，且焊料7c充分地潤濕擴散至被供給有該焊料7c之半導體晶片1上之突起狀電極所具有之頭頂部(端面)、以及與該突起狀電極5相對向之電路基板2上之突起狀電極所具有之頭頂部(端面)及側面的狀態得以保持。另一方面，於因半導體晶片1產生翹曲而導致接合部之高度減少之區域內，焊料7c潤濕擴散至自配置於該區域之保護膜9之開口部露出之電極端子之表面，藉此，由該焊料7c形成之焊料部7難以自設置有該焊料部7之接合部所包含之突起狀電極5之底面之投影區域溢出，從而難以產生橋接不良。
又，於形成複數個接合部時，對半導體晶片1施加有搭載壓力(荷重)，而使半導體晶片1朝向電路基板2加壓，藉由其反作用，而自電路基板2上之複數個突起狀電極6之端面向半導體晶片1上之複數個突起狀電極5之端面施加壓力。此時，亦可以於半導體晶片1上之複數個突起狀電極5各自之端面形成凹陷之方式設定搭載壓力。若如此於半導體晶片1上之各突起狀電極5之端面形成凹陷，則複數個接合部之高度整體上降低。由此，即便半導體晶片1之翹曲量增加，亦容易確保配置於半導體晶片1之外周部之複數個電極端子3與對應於該等電極端子3之電路基板2之複數個電極端子4之間的電性連接。半導體晶片1上之各突起狀電極5中所形成之凹陷之深度係藉由搭載壓力(荷重)之調整而進行控制。較佳為以半導體晶片1之翹曲越大則各凹陷越深之方式提高搭載壓力(荷重)。
又，亦可於本實施形態相反地，半導體晶片1上之複數個突起狀電極5之頭頂部(端面)具有小於電路基板2上之複數個突起狀電極6之 頭頂部(端面)之面積。於此情形時，與上述形成於電路基板2之保護膜9之複數個開口部之面積同樣地，藉由調整形成於半導體晶片1之保護膜8之複數個開口部之面積，可獲得與本實施形態相同之效果。
如以上所說明般，根據本實施形態，因半導體晶片1之翹曲而導致半導體晶片1與電路基板2之間之距離增加之區域內所設置之電路基板2之電極端子的表面中焊料7c所潤濕之面積變得小於設置於其他區域之電路基板2之電極端子之表面中焊料7c所潤濕之面積。藉此，設置於半導體晶片1與電路基板2之間之距離增加之區域的半導體晶片1之電極端子與對應於該電極端子之電路基板2之電極端子之間難以產生電性未連接之情況。另一方面，設置於因半導體晶片1之翹曲而導致半導體晶片1與電路基板2之間之距離減少之區域的電路基板2之電極端子之表面中焊料7c所潤濕之面積變得大於設置於其他區域之電路基板2之電極端子之表面中焊料7c所潤濕之面積。藉此，焊料難以自設置於半導體晶片1與電路基板2之間之距離減少之區域的半導體晶片1上之突起狀電極之底面之投影區域溢出，從而難以產生橋接不良。因此，可減少即便於將半導體晶片1連接於電路基板2之複數個接合部間複數個焊料部7之體積均勻，在半導體晶片1之面內半導體晶片1與電路基板2之間之距離亦會變得不均勻而引起之不良之產生。由此，即便於將具有翹曲之半導體晶片1安裝於電路基板2之情形時，亦可確保較高之連接可靠性。
又，即便於將半導體晶片1之複數個電極端子3接合於電路基板2之複數個電極端子4時，半導體晶片1上之各突起狀電極5與電路基板2上之各突起狀電極6之前端彼此接觸，亦難以產生橋接不良。由此，於將半導體晶片1搭載於電路基板2時，即便不控制半導體晶片1之搭載高度，亦難以產生橋接不良。因此，無需控制半導體晶片1之搭載高度，故而可謀求半導體晶片1向電路基板2之搭載時間之縮短化。
以上，對成為本發明之示範之實施形態進行了詳細記述，但只要為精通該技術者，則可容易地認識到本發明係新穎地進行教示，以及可在實質上不脫離本發明之效果之範圍內，於上述成為示範之實施形態中進行各種變更。因此，意圖將此種各種變更包含於本發明之範圍內。
1‧‧‧半導體晶片
2‧‧‧電路基板
3‧‧‧電極端子
4‧‧‧電極端子
5‧‧‧突起狀電極
6‧‧‧突起狀電極
7‧‧‧焊料部
8‧‧‧保護膜
9‧‧‧保護膜

Claims (13)

  1. 一種電子零件之安裝構造體，其包括：電子零件，其具有複數個第1電極端子；電路基板，其具有與上述複數個第1電極端子相對應之複數個第2電極端子；及複數個接合部，其等使上述複數個第1電極端子接合於上述複數個第2電極端子；且上述複數個接合部包含：複數個第1突起狀電極，其等形成於上述複數個第1電極端子上；複數個第2突起狀電極，其等形成於上述複數個第2電極端子上；及複數個焊料部，其等使上述複數個第1突起狀電極接合於上述複數個第2突起狀電極；且上述複數個第1突起狀電極之端面之面積大於上述複數個第2突起狀電極之端面之面積；自上述電路基板露出之上述複數個第2電極端子之面積中包含大於上述複數個第2突起狀電極之底面之面積。
  2. 如請求項1之電子零件之安裝構造體，其中對應於上述電子零件之外周部而配置之第2電極端子自上述電路基板露出之面積小於對應於上述電子零件之中央部而配置之第2電極端子自上述電路基板露出之面積。
  3. 如請求項1之電子零件之安裝構造體，其中上述複數個第1突起狀電極分別具有柱狀之形狀，上述複數個第2突起狀電極分別具有柱狀之形狀。
  4. 如請求項1之電子零件之安裝構造體，其中上述複數個焊料部係配置於上述複數個第2突起狀電極之周圍。
  5. 如請求項1之電子零件之安裝構造體，其中第1突起狀電極之前 端之面積、使該第1突起狀電極接合於第2突起狀電極之焊料部之體積、該第2突起狀電極之前端或底面之面積、及該第2突起狀電極之高度滿足下式之關係：焊料部之體積≦(第1突起狀電極之前端之面積-第2突起狀電極之前端或底面之面積)×第2突起狀電極之高度。
  6. 如請求項1之電子零件之安裝構造體，其中上述複數個第1突起狀電極分別具有圓柱狀之形狀，上述複數個第2突起狀電極分別具有圓柱狀之形狀，上述複數個第2突起狀電極之高度及直徑滿足高度≦直徑之關係。
  7. 如請求項1之電子零件之安裝構造體，其中上述複數個第1突起狀電極分別具有圓柱狀之形狀，上述複數個第2突起狀電極分別具有圓柱狀之形狀，上述複數個第2突起狀電極之直徑為上述複數個第1突起狀電極之直徑之0.4倍~0.7倍之大小。
  8. 如請求項1之電子零件之安裝構造體，其中上述複數個第1突起狀電極分別含有銅。
  9. 如請求項1之電子零件之安裝構造體，其中上述複數個第2突起狀電極分別含有銅或鎳。
  10. 如請求項1之電子零件之安裝構造體，其中上述複數個第2突起狀電極分別具備含有金之表層。
  11. 如請求項1之電子零件之安裝構造體，其中上述複數個焊料部分別含有錫。
  12. 一種電子零件之安裝構造體之製造方法，其係製造如下電子零件之安裝構造體之方法，該電子零件之安裝構造體包括：電子零件，其具有複數個第1電極端子；電路基板，其具有與上述複數個第1電極端子相對應之複數個第2電極端子；及 複數個接合部，其等使上述複數個第1電極端子接合於上述複數個第2電極端子；該電子零件之安裝構造體之製造方法包括以下步驟：於上述複數個第1電極端子上形成複數個第1突起狀電極；於上述複數個第2電極端子上形成複數個第2突起狀電極；對上述複數個第1突起狀電極分別供給焊料；及於使上述焊料分別熔融之狀態下，使上述複數個第1突起狀電極之前端與上述複數個第2突起狀電極之前端接觸而形成上述複數個接合部。
  13. 如請求項12之電子零件之安裝構造體之製造方法，其中於形成上述複數個接合部時，藉由自上述複數個第2突起狀電極之前端向上述複數個第1突起狀電極之前端施加壓力，而於上述複數個第1突起狀電極之前端分別形成凹陷。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI669792B (zh) * 2017-03-03 2019-08-21 日商 Tdk 股份有限公司 半導體晶片之製造方法

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9646923B2 (en) * 2012-04-17 2017-05-09 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor devices, methods of manufacture thereof, and packaged semiconductor devices
JP5923725B2 (ja) * 2012-05-15 2016-05-25 パナソニックＩｐマネジメント株式会社 電子部品の実装構造体
US20150097286A1 (en) * 2013-04-12 2015-04-09 Xintec Inc. Chip package and method for fabricating the same
CN104392940A (zh) * 2014-10-31 2015-03-04 南通富士通微电子股份有限公司 形成倒装芯片半导体封装的方法
JP6485235B2 (ja) * 2015-06-10 2019-03-20 富士電機株式会社 半導体装置
KR20170042429A (ko) * 2015-10-08 2017-04-19 삼성전자주식회사 반도체 패키지
JP6565609B2 (ja) * 2015-11-02 2019-08-28 富士通株式会社 電子装置、電子部品及び半田
JP6536397B2 (ja) * 2015-12-25 2019-07-03 富士通株式会社 電子装置、電子装置の製造方法及び電子機器
US9953909B2 (en) * 2016-07-18 2018-04-24 Intel Corporation Ball grid array (BGA) with anchoring pins
JP7207150B2 (ja) * 2019-05-15 2023-01-18 株式会社デンソー 半導体装置
JP7390824B2 (ja) * 2019-08-28 2023-12-04 デクセリアルズ株式会社 半導体装置の製造方法
US11502056B2 (en) * 2020-07-08 2022-11-15 Taiwan Semiconductor Manufacturing Company, Ltd. Joint structure in semiconductor package and manufacturing method thereof
CN112768363B (zh) * 2021-04-08 2021-06-22 浙江集迈科微电子有限公司 曲面芯片贴装结构及其制备方法
US20230086180A1 (en) * 2021-09-20 2023-03-23 Intel Corporation Deformable semiconductor device connection

Family Cites Families (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3353534B2 (ja) * 1995-04-27 2002-12-03 株式会社日立製作所 電子回路装置及び電子回路部品
JPH0997791A (ja) 1995-09-27 1997-04-08 Internatl Business Mach Corp <Ibm> バンプ構造、バンプの形成方法、実装接続体
JP3608640B2 (ja) * 1997-05-12 2005-01-12 株式会社リコー 半導体装置およびその実装方法
JP2000174048A (ja) * 1998-12-03 2000-06-23 Matsushita Electric Ind Co Ltd 突起電極形成方法および半導体装置
JP3910363B2 (ja) * 2000-12-28 2007-04-25 富士通株式会社 外部接続端子
JP2004335660A (ja) * 2003-05-06 2004-11-25 Sony Corp 半導体装置及びその製造方法、並びに配線基板及びその製造方法
JP4104490B2 (ja) 2003-05-21 2008-06-18 オリンパス株式会社 半導体装置の製造方法
JP2004356294A (ja) 2003-05-28 2004-12-16 Ngk Spark Plug Co Ltd 配線基板の製造方法
JP2006100552A (ja) * 2004-09-29 2006-04-13 Rohm Co Ltd 配線基板および半導体装置
JP4908750B2 (ja) * 2004-11-25 2012-04-04 ローム株式会社 半導体装置
JP2006202969A (ja) 2005-01-20 2006-08-03 Taiyo Yuden Co Ltd 半導体装置およびその実装体
JP2006278576A (ja) * 2005-03-28 2006-10-12 Sanyo Electric Co Ltd 半導体レーザ装置、半導体レーザ装置の製造方法および光ピックアップ装置
WO2007105535A1 (ja) * 2006-03-14 2007-09-20 Matsushita Electric Industrial Co., Ltd. 電子部品実装構造体およびその製造方法
JP2007281369A (ja) 2006-04-11 2007-10-25 Shinko Electric Ind Co Ltd 半田接続部の形成方法、配線基板の製造方法、および半導体装置の製造方法
JP4920330B2 (ja) 2006-07-18 2012-04-18 ソニー株式会社 実装構造体の実装方法、発光ダイオードディスプレイの実装方法、発光ダイオードバックライトの実装方法および電子機器の実装方法
JP2008205260A (ja) 2007-02-21 2008-09-04 Sharp Corp 回路基板接合構造体およびその製造方法
WO2008117513A1 (ja) * 2007-03-23 2008-10-02 Panasonic Corporation 導電性バンプとその製造方法および電子部品実装構造体
JP5266699B2 (ja) * 2007-09-25 2013-08-21 日本電気株式会社 コンタクト支持体及び半導体装置の実装構造
JP2009105119A (ja) * 2007-10-22 2009-05-14 Spansion Llc 半導体装置及びその製造方法
JP4591529B2 (ja) 2008-03-26 2010-12-01 株式会社デンソー バンプの接合方法およびバンプの接合構造体
JP2010003927A (ja) * 2008-06-20 2010-01-07 Fujitsu Ltd 回路基板及びその製造方法
JP5056718B2 (ja) * 2008-10-16 2012-10-24 株式会社デンソー 電子装置の製造方法
JP5185062B2 (ja) * 2008-10-21 2013-04-17 パナソニック株式会社 積層型半導体装置及び電子機器
JP5375708B2 (ja) * 2010-03-29 2013-12-25 パナソニック株式会社 半導体装置の製造方法
JP6081044B2 (ja) * 2010-09-16 2017-02-15 富士通株式会社 パッケージ基板ユニットの製造方法
JP5923725B2 (ja) * 2012-05-15 2016-05-25 パナソニックＩｐマネジメント株式会社 電子部品の実装構造体

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI669792B (zh) * 2017-03-03 2019-08-21 日商 Tdk 股份有限公司 半導體晶片之製造方法

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