TW201036127A - High Q factor integrated circuit inductor - Google Patents

High Q factor integrated circuit inductor Download PDF

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Publication number
TW201036127A
TW201036127A TW099116268A TW99116268A TW201036127A TW 201036127 A TW201036127 A TW 201036127A TW 099116268 A TW099116268 A TW 099116268A TW 99116268 A TW99116268 A TW 99116268A TW 201036127 A TW201036127 A TW 201036127A
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Taiwan
Prior art keywords
layer
inductor
top surface
pad
upper portion
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TW099116268A
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English (en)
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TWI351748B (en
Inventor
Daniel C Edelstein
Panayotis C Andricacos
John M Cotte
Hariklia Deligianni
John H Magerlein
Kevin S Petrarca
Kenneth J Stein
Richard P Volant
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Ibm
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Publication of TW201036127A publication Critical patent/TW201036127A/zh
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Publication of TWI351748B publication Critical patent/TWI351748B/zh

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201036127 發明說明： 【發明所屬之技術領域】 本發明係關於積體電路，特別是，有關高Q factor^ factor))的電感器結構、製造高Q值電感器結 及將尚Q值之電感器結構整合至積體電路製程的方法。 【先前技術】 卉多用於射頻(RF)應用上的積體電路都會使用 〇 電感器埂常在積體電路晶片的表面上或其附近，以相;^交厚 的金屬製成。當積體電路操作的RF頻率增加時，除非電感哭 的Q值也增加，否則功率消耗將會增加。電感器的卩值^^ 義，Q=Es/El，其中ES是儲存於電感器之反應部分的總能量， E1是損失於電感器之反應部分的總能量。電感器的Q值亦可 表=為Q=W〇L/R，其中WQ是共振頻率，L是電感值，R是電 感器的電阻。第二等式的含義為：Q會隨著R減少而增加。 使用南導電率金屬、寬金屬線或厚金屬線來製造電感器 可以降，電感器的電阻。然而，使用寬金屬線的電感器卻會 ◎ 佔用大量的積體電路晶片表面，且通常也會大幅限制積體電 路用以配置電感器的合適區域。尤其在使用高導電率金屬以 及在後續整合高導電率、厚金屬電感器和積體電路的互連層 (inter-connection)時，厚金屬電感器的製造很有問題。因此， 需要以高導電率金屬形成高Q值、厚金屬電感器，以及用以 形成積體電路晶片之電感器的互連層製造技術的方法與整合 方案。 【發明内容】 本發明的第一方面為形成電感器的方法，此方法按所列 4 201036127 順序包含·（a)提供-半導體基板；（b)在此基板的一頂面上形 成-介電層；⑹在此介電層中形成—下方溝渠；⑷在此介電 層的頂面上形成一阻抗層，（e)在此阻抗層中形成一上方溝 渠^此上方麟和下謂騎齊，此上謂渠的—底部對下 $渠為·;及_-賴完全填充下方溝纽至少部分 ，、充上方溝渠以形成電感器。 咖的第二方面為形成—電感器的方法，此方法按所 ⑻提供一半導縣板;(b)在此基板的-頂面上 Ο Ο ί 此介電層中形成一下方溝渠；⑷在此下 方溝渠中及；丨電層之一頂面之上形成—丘形 liner);⑹在此導電轉之上形成一共形 ^層^成上方溝渠，此上謂^下 .m鶼吟阳卩刀填充上方溝渠以形成電感 S成斤有暴露的Cu表面之上，選擇性地 襯墊覆蓋ί ί ί e passivatiGn layer);及(k)自導電 復盘；丨电層的表面之區域，選擇性地移降兮Γ11 ， 以及自介電層的表面移除導電襯塾移除扣U日日種層 感器本第=體結構’該結構包含：一電 么=部半導體基板上之—介電層、 的裝詈。 °λ"甩層之上，以及電性接觸該電感器 【實施方式】 ^為根據本發明第一實施例所繪示的電感器及接觸塾 5 201036127 之俯視圖。圖1中，積體電路晶片100Α包含電咸器105，此 電感态105具有整合介層窗(integral vias)110A與"ll〇B，用以 積體電路晶片内的線路層(wirinSlevels)(未顯示）。雖將 ，感器105顯示為螺旋形(spiral)電感器，但本發明亦適用於 ，、他形狀的電感器。積體電路晶片100A還包含··在介層窗 120底部的_ 1/〇端墊115 ’其係用以在積體電路晶片内互連 層(未顯示）；以及一導電保護層125，其形成於1/〇端 塾115之頂部並和介層窗12〇重疊。 ❹ Ο 圖2為根據本發明第二實施例所繪示的電感器及接觸墊 圖。圖2中’積體電路晶片麵包含電感器1〇5，此 電感益105具有整合介層窗11〇A與11〇B，用以互連至積體 曰:片内的線路層(未顯示)。雖將電感器1〇5顯示為螺旋形 明亦適用於其他形狀的電感11。積體電路晶 還L 3 .在介層窗120底部的一 I/O端塾115，並儀 η積體電路晶片内互連至線路層(未顯示）卜導電保^層 ^25 ’其形成於1/0端墊115之頂部並和介層窗12 一 ;以及一焊球135，其形成於導電保 ° : 干球又名為「控制塌陷晶片連接(controlled =PSe chlp connection(C4))球」、「C4焊球」及「焊鍚凸塊 (sender 就本發明的效用而言，用語「焊接餘 C〇1_)」可用來取代用語「焊球」。焊接柱為錯(Pb)或錯/鍚 (Pb/Sn)合金的柱狀物，本發明亦適用於焊接柱互連技術。 為發明第三實施例所1 會示的電感器及接觸墊 電感器Π>5具有整合介層窗110A與 電路晶片内的線路層(未顯示）。雖將電感器1〇5 、 電感器，但本發明亦適用於其他形狀&電感器積體“ 6 201036127 片100C還包含·在介層窗120底部的1/0端墊115，其係用 以在積體電路晶片内互連至線路層（未顯示）；的一導電保護 層，以形成於頂部並重疊介層窗12〇的凸起墊14〇覆蓋；plm 層130，以及形成於導電保護層125之上的焊球I%。PLM層 130完全落在凸起墊140上。 圖4A至4F係用以描述本發明第一、第二及第三實施例 所共有之製造步驟的部分橫截面圖。圖4A至4F係截取自圖 1的直線S1-S1、圖2的直線S2-S2或圖3的直線S3-S3。 圖4A中，半導體基板2〇〇包含：1/〇端墊115及下穿線 路(underpass wireS)205A 與 205B。I/O 端墊 115 的頂面 21〇 及 下穿線路205A與205B個別的頂面215A與215B，和基板200 的頂面220共面(co-planer)。下穿線路2〇5A與205B及I/O端 墊115電性地連接其他線路層的線路(未顯示），最後再電性地 連接至基板200内的主動元件(actjve devjce)。下穿線路2〇5a 與205B可提供電性連接至電感器1〇5(請見圖！、2或3)。在 一例子中，I/O端墊115及下穿線路2〇5A與2〇5B包含氮化 鈕/^(TaN/Ta)襯墊(首先形成TaN層)及Cu核心，而且其形成 係藉由鑲肷(damascene)或雙鑲嵌(duai damascene)製程；且圖 4A所不之基板200的部分包含二氧化矽(si〇2)。TaN/Ta襯墊 可被取消，或是以包含其他材料(如鎢(w)、鈦(Ή)及氮化鈦 (TiN))的襯墊來取代。 在鑲嵌製程中，在一介電層中蝕刻一溝渠，在溝渠的底 邰及側壁和”電層的頂面上，沉積一最佳導電共形襯墊及導 電晶種層。然後，在晶種層上沉骸魏—核心導體，以填 充溝渠。最後，執行一化學機械拋光 (cheimcal-mechanical-polish)步驟’從介電層的頂面移除所有 7 201036127 的襯墊、晶種層及核心導體，然後留下導電填 的頂面和介電層的頂面共面。在雙鑲嵌程序中， 之前’先在溝渠的底部中形成對下方線路層為開 圖4Β中，在基板200的頂面22〇及下穿線路2〇5α、2_ 及I/O端墊115個別的頂面215Α、125Β及210上，來成—笛 一介電層225。在第一介電層225的頂面235上形成一第-八 電層230。在第二介電層23〇的頂面撕上形成 Ο ❹ L至。f0 A ’第三介電層—_4，其3 可以僅使用-單一介電層(如Si〇2或8购，或
Si3N4之上），來取代三個介電層⑵、23〇曰及 240，用以實施本發明。 汉 圖尸中，將在下穿線路2〇5a、施B及⑽端塾出 =三，丨電層240對齊的部分移除， =面245。圖4D中，將在下穿線路2〇5a、 ^ 15亡之弟二介電層23G及第—介電層225對齊的部^ 二11成溝渠2觀、_及介職12G，並露出 =路2脱、2㈣及1/0端塾115個別的頂面韻、21犯^ 八。此外，將第三介電層24〇的部分及第二介電層23 # 刀，向下移除至深度D卜以形成溝渠260。 圖 2 個互解Ϊ是，溝渠雇、細及實際上為一 個互連的螺旋形溝渠，其中將會形成電感器啊請見巧 8 201036127 及3)，且應明白，溝渠250A與250B代表這些螺旋形溝渠的 部分，其中形成介層窗110A與11〇Β(請見圖1、2及3)1溝 渠250A、250B及260僅在截面圖示中顯示為分開的溝渠， 為了避免在某個時刻說明螺旋形溝渠的某個部分時發生混 淆，因此將會使用術語：“分開的”溝渠。 λ 只要在溝渠260中保留足夠的第二介電層盖 II 250Λ . 250Β t 120 225 电層,225，那麼溝渠260中第二介電層230的確實移除深度 ❹ D1並非關鍵。在一例子中，Di約25〇〇 a至75〇〇 a。D2是 ^渠260的深度，D3是溝渠25〇A、2遞及介層窗12〇的深 又。溝渠260及溝渠250A、250B及介層窗120間的深度差 為 D3-D2。 圖4C~及4D所示步驟可以若干方法來完成。在第一方法 中，塗上第一光阻層，執行第一微影I虫刻程序，執行第一反 應性離子蝕刻(RIE)程序，以選擇性的蝕刻前述例子中si〇2之 上的Si#4，用以定義圖4C所示之第三介電層24〇中的溝渠 250A: 250B及介層窗120。然後，移除第一阻抗層，塗上第、 了阻抗層，執行第二微影蝕刻程序後，再執行第二程序， ，選擇=的蝕刻前述例子中之上的Si〇2,用以完全開啟 第二及第三介電層240中的溝渠250A、250B及介層窗12〇， 並蝕刻D1至溝渠260中的第二介電層230,如圖4D所示之。 然後移除第二阻抗層。 人、在第二方法中，塗上一單一雙標(dualtone)阻抗層(堆疊或 二成正/負光阻），及執行使用雙標光罩的一微影蝕刻步驟，以 :全，移除在溝渠25GA、25GB及介層窗12G形成處的阻抗 g，並僅部分地移除在溝渠26〇形成處的阻抗層（薄化阻抗 9 201036127 層）。然後，執行單一 RIE蝕刻以形成圖4D中所示的結構(略 過圖4C)。接著，移除雙標阻抗層。在任一方法中，均可執行 一清除蝕刻’例如使用稀釋HF的濕蝕刻。
圖4E中，在第三介電層240的頂面270上及溝渠250A、 250B與260和介層窗120的側壁與底部上，沉積一共形襯墊 265。然後’在襯塾265的頂面280上’沉積一共形晶種層275。 在一例子中，襯墊265為約200 Λ至5000 A的Ta，其係沉積 在約10人至1000 A之TaN之上，而晶種層275為約1〇〇 A 至1500 A的Cu，二者均以物理氣相沉積(physical vap〇r deposition, (PVD))或離子化物理氣相沉積(i〇nized vapor deposition, (IPVD))所形成。 圖扑肀，執行CMP程序，自襯墊265接觸到第三 層240之頂面270的地方，移除晶種層275，但在溝渠25〇a、 250B、26。及介層窗丨2。的側壁與底部上留下晶種層。在⑽ 可以執行一選擇性的清除侧。在晶種層275為Cu的例 =中’可以使用稀釋的乙二酸(〇xalic add)/HF鞋刻劑來主 除韻刻。糾也可以執行選擇性的Cu清除钮刻。丨^月 f第二方法中，不會執行上述CMp程序，且晶 移飢終纟請雜續步驟^， 二!層實：發來:Ζ明可:二，㈡更少4 膚來取代上述的三個j電層。使用早一门電層或兩個介電 201036127 圖5A至5F係用以描述本發明第一及第二實施例所共 有，而為圖4A至4F所描述的製造步驟之後續步驟的 ^ 截面圖。圖5A至5F係戴取自第一實施例中圖！的直/ & 或第二實施例中圖2的直線S2_S2。 圖5A中，形成阻抗層285及加以圖案化，露出溝準 250A、250B與260之底部與側壁上的晶種層275，但會保言蔓 介層窗120。阻抗層285具有厚度D4。圖案化的阻抗層 ❹ 可用來增加溝渠25〇A、250B與260的深度。在一例子中， D4為約8至20微米厚。在一例子中，阻抗層285可以是任 何習知的旋塗光阻(spun applied resist)。在第二例子中，D4為 約20至50微米。在約20微米以上，可以使用杜邦(]〇111)〇故)(考急 拉威州威明頓(Wilmington, De.))所製造的Riston_其他滾^ 光阻(roll applied resist)。D4的值是控制電感器105(請見圖2) 之厚度的因子，δ玄電感器的形成如圖5B所示，且將於下文中 說明。 圖5Β中，藉由使用晶種層275作為陰極進行電鍍，以厚 〇 度D5的金屬部分填充溝渠25〇八、25(^與26〇，以形成電感 器105。厚度D5是控制電感器1〇5之厚度的另一個因子。請 注意’晶種層275的個別島之間係藉由襯墊265加以電性連 接’而襯墊265實際上為在所有基板2〇〇上延伸的一毯狀(但 共形)導電覆蓋層。一般而言，電鍍程序在金屬達到填充阻抗 層285的溝渠260至約1到2微米時停止，以使後續阻抗層 的移除較為容易。可以過剩的填滿溝渠，然後再CMp過多的 金屬。在一例子中，電感器105係由電鍍的Cu所形成。示範 性的Cu電鑛程序說明於volant等人的美國專利 US6,368,484’其全文以引用的方式併入本文中。在一例子中， 201036127 D5約5至50微米。 ♦ a，5C中，移除阻抗層285(請見圖5Β)。本發明並不限制 電感器105之線圈的寬度W1及間隔S1。 程f光阻系統、鮮技術、曝^具及^) 小線路/間隔；上限為電感器可用之積體電路的 =了買。在-例子中，W1約2至3G微米及si約2至2〇 Ο Ο Ϊ第—方法中，現藉由如濕蝕刻(wetetch)，將晶種# 275 ，露出的區域移除。在一例子中’酬Ur Hi iim=niumpe祕ate)及水的混合物。cu _醉慢到i以 265二！摆騎有暴露表面之上(但不在暴露的襯墊 Γ為約2000 A至6000 A厚的綱，第二ϊ 12：〇A^4000^^(au)^^^^ 295等同於圖1、2及3所示及上述的導電保護層Γ25層 及第圖iE雷！所有暴露的概塾265。在概墊265為TaN/Ta RI^ 層295為Au的例子中，可以使用基於氟的 圖5F中，塗上一毯狀有機保護層300，並以微影蝕刻的 201036127 方式將其圖案化’以在1/0端墊U5之上露出一接觸墊3〇5。 在例子中，毯狀有機保護層300為聚醯亞胺(polyimide)。聚 酿亞胺層通常藉由以下方式提供：以一聚驢亞胺前驅物質 (precursor)覆盍後，再利用加熱將前驅物質轉換為熟化的 (cured)聚邮胺。市場上可麟㈣醯亞胺前轉質(聚酿胺 酸）或由杜邦(德拉威州威明頓)所製造的各種的聚醯亞胺前 驅物質’以商名「P>Talin」t可麟。這些聚 質有許多等級，其商名包含也555、PI2545、p」6〇、 ΡΙ-5878、ΡΙΗ-61454、及PI-2540皆可購得。部分係為 〇 Pyrcmfletie dianhydride_oxydianline (PMA_ODA)聚醯亞胺前 驅物質。熟化的聚醯亞胺層約0·4至5微米厚。接觸墊3〇5 可用作線路連接墊。在線路接合中，以超音波的方式將鋁(A1) 或Au線路焊接或接合至接觸墊。在此總結本發明第一施 的製造。 ' 圖5G係用以描述在本發明第二實施例中，圖5A至5F 所描述的製造步驟之後續步驟的部分橫截面圖。圖5G截取自 圖2的直線S2-S2。圖5G中，形成PLM層130以電性地接 觸凸起接觸墊305 ’並在PLM層130上形成焊球135。利用 Ο 穿通遮罩電鍍 C4 製程(through mask plated C4 process)即可 形成PLM 130及焊球135。穿通遮罩電鍍C4製程在本技術領 域中為習知，簡言之係有關蒸鍍或濺鍍一 PLM及一晶種層， 以在一晶圓上形成一圖案化光罩、電鍍pb或洲/如合金、剝 除光罩、及蝕刻移除暴露的PLM及晶種層。一示範性的C4 電鍍製程說明於Uzoh等人的美國專利US6,297，140及也是 Uzoh等人的美國專利US6,251，428，二者的全文以引用的方 式併入本文中。在穿通電鍍C4製程的一個例子中，PLM層 130包含鈦鎢/鉻銅/銅(Tiw/CrCu/Cu)的三重層，且焊球135包 含Pb或Pb/Sn合金。在後蒸鑛(p0St_evap0rative)或後電鍍(p〇st 13 201036127 plating)回炫退火(reflow anneal)後，顯示焊球135。在一例子 中，TiW 層約 250 A 至 2000 A 厚，CrCu 層約 100 A 至 2000 A 厚，及Cu層約1000 A至20,000 A厚。在此總結本發明第二 實施例的製造。 由於電感器1〇5(請見圖5G)明顯高於接觸墊305,因此無 法使用蒸鍍C4製程來形成圖5G的PLM 130及焊球135，因 為在蒸錄C4製程中使用的銦（molybdenum)遮罩是遠離接觸 墊’因而造成遮罩蒸鍍下無法容忍的量。本發明第三實施例 提供一墊結構，可允許使用一蒸鍍C4製程。 圖6A至6G係用以描述在本發明第三實施例中，圖4A 至4F所描述的製造步驟之後續步驟的部分橫截面圖。圖6A 至6G截取自圖3的直線S3-S3。 圖6A中，形成阻抗層285並加以圖案化，露出溝渠 250A、250B與260及介層窗120之底部與側壁上的晶種層 275。上文已說明阻抗層285的組成物及厚度。
圆中 秸田便用晶種層275作為陰極進行電鍍，以金 填充溝渠2观、2通與及介層窗12〇，用以形 門：、105及凸起墊140。請注意’晶種層275的個別島之 襯塾265加以電性地連接，襯塾275實際上為在所 電伸的—毯狀(但共形)導電覆蓋層。—般而言， Ξίίί屬達到阻抗層285頂面約1至2微米時停止， 後齡較為料。可⑽麵填騎渠，然 k多的孟屬。上文已說明電感器1〇5的組成物及厚度。 圖c中’移除阻抗層285(請見圖6B)。上文已說明電感 14 201036127 器105之線圈的寬度W1及間隔S1。 在第二方法中’如上所述’將晶種層275從其暴露區域 中移除。 圖6D中，在電感器1〇5及凸起墊140所有暴露的表面之 上(但不在暴路的概塾265上）’選擇性地電鍵一第一導電保護 層290。在第一導電保護層29〇的所有暴露表面之上(但不在 暴露的襯墊265上），選擇性地電鍍第二導電保護層295。上 ◎ 文已說明第一保護層290及第二保護層295的組成物及厚度。 圖6E中，移除所有暴露的襯墊265。在襯墊265為TaN/Ta 且第二導電保護層295為Au的例子中，可以使用基於氟的 RIE 〇 圖6F中，塗上毯狀有機保護層3〇〇並以微影蝕刻的方式 將其圖案化，以在I/O端墊115之上露出一凸起接觸墊31〇。 上文已說明毯狀有機保護層300的組成物。此時，在本發明 第三實施例的製造中，可以修改製造，如上述塗上一聚^亞 〇 胺或其他保護覆蓋層，及將凸起接觸墊31〇作為一線路連接 墊或一平台墊（landing pad)，以建立懸臂式橫樑連接 (cantilevered beam connection) ’如本發明第四實施例中的捲帶 式自動接合(tape automated bonding (TAB))封裝。 繼縯本發明第三實施例，圖6G中，在凸起接觸墊310上 形成PLM層130’並在PLM層130上形成焊球135。利用穿 通遮罩電鑛C4或洛鍍C4製程，即可形成pLM 13〇及焊球 135。由於凸起接觸塾w㈣高度’因為錮蒸鍵遮罩將會接近 凸起接觸墊310，所以現在可以使用蒸鍍C4製程，可以避免 15 201036127 上述遮罩遠雜時_題。絲C4 在本技術領域 ^，係有臟辦罩放置接近—半導體細，透避 中的孔洞，蒸鍍或猶PLM，絲透過相同的孔洞，罩 或Pb/Sn合金，接著移除遮罩。在蒸鑛c 例子 PLM ^ 130 ^ Cr/CrCu/Au ^ ί ΐ金。在一例中，Cr層約100 A至_ A厚，Cu ，約1 ί、2000人厚，及Au層約100 A至_入厚。 =k^itiil_ C4製程及材料。在此總結本發 三實施例的製造。 4¾月弟 Ο Ο 明所有實施例均顯示，製造的電―其具有約大於 專於40的Q值及具有約大於等於〇 5 ηΗ的電感。 戸入，!^本發明不僅提供以高導電率金屬所形成的高Q值 ^屬電感器’還提供—種電感器的形成方法及整合，以適 用於積體電路晶片的互連層製造技術上。 上述本發明實施例的說明是為了暸解本發明。應明白， ^明不限於本文所述的特定實施例，而是在不脫離本發明 =可下，能夠進行各種修改、重新配置及替換 ’正如本技術 曰所明白的。例如’儘管本發明說明以TaN/Ta襯墊、Qj g種，、及Cu核心形成電感器，但也可以換成其他導電材 u a 此以下申睛專利範圍是用來涵蓋此種在本發明精神 及乾嚀之内的修改及變更。 【圖式簡單說明】 八瞌ί發明的特色如隨附的申請專利範圍所述。然而’要完 =回解本發明本身’請參考解說性實施例的詳細說明並連同 附圖一起閱讀，其中： 201036127 圖1為根據本發明第一實施例所繪示的電感器及接觸墊 之俯視圖； 圖2為根據本發明第二實施例所繪示的電感器及接觸墊 之俯視圖； 圖3為根據本發明第三實施例所繪示的電感器及接觸墊 之俯視圖； 圖4A至4F係用以描述本發明第一、第二及第三實施例 所共有之製造步驟的部分橫截面圖； 圖5A至5F係用以描述本發明第一及第二實施例所共 有，而為圖4A至4F所描述的製造步驟之後續步驟的部分横 截面圖； 圖5G係用以描述在本發明第二實施例中，圖5A至5F 所描述的製造步驟之後續步驟的部分橫截面圖；以及 圖6A至6G係用以描述在本發明第三實施例中，圖4A 至4F所描述的製造步驟之後續步驟的部分橫戴面圖。 【主要元件符號說明】 100A、100B、100C :積體電路晶片 、110B :整合介層窗 介層窗 襯墊限制冶金(PLM)層 導電純化塗布凸起塾 、205B :下穿線路 、245、270、280 :頂面 第二介電層 、250B、260 :溝渠 共形晶種層 第一導電保護層 毯狀有機保護層
1〇5:電感器 110A
115: I/O 端墊 120: 125 :導電保護層 130 : 135 :焊球 140 :
200:半導體基板 205A 210、215A、215B、220、235 225:第一介電層 230:
240 :第三介電層 250A 265 :共形襯墊 275 285 :阻抗層 290 295 :第二導電保護層300 17 201036127 305 :接觸墊 310 :凸起接觸墊
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Claims (1)

  1. 201036127 七、申請專利範圍： 1. 一種半導體結構，其包含： —電感器’具有一頂面、一底面及侧壁、該電感器的一下方 部分延伸一固定距離至形成於一半導體基板上之一介電層、以及 一上方部分延伸至該介電層之上；以及 電性接觸該電感器的裝置。 2. 如請求項1所述之該結構’其中該電感器的該下方部分包含一 導電襯墊及一核心導體(core conductor)，及該電感器的該上方部 ❹ 分包含該核心導體。 3. 如請求項2所述之該結構’其中該核心導體為Cu，及該襯墊包 含TaN及Ta所形成的一雙層。 4. 如睛求項2所述之該結構’其中該上方部分更包含一導電保護 層’位在該電感器之該上方部分之—頂面及侧壁上。 5. 如請求項4所述之該結構，其中該保護層包含一祕層或在一 Ni層之上的一 Au層。 ❹ 6. 如請求項1所述之該結構，其中該電感器具有由大於約5微米 之該側壁所定義的一高度。 7. 如μ求項1所述之該結構，其中該下方部分延伸小於3微米的 一距離至該介電層中。 8. ^凊求項1所述之該結構’其巾接繼械器的該裝置包 a整合介層窗(integral vias) ’其自該電感器的該底部延伸通 介電層’並電性地接觸通過該基板中冶金層的介層窗。 Λ 19 201036127 9中在該介層窗之上的該電感器之 更S該之上的該電感器的該頂面部分， 10‘如請求項1所述之該結構，其中 旋形線圈—中之該介電〜的！;=感_申而平行於在-螺 11.如請求:員ω所述之該結構，其中該電感器為約2至 ， ❹ G 及该職觀嶋接的複數個_間闕2至2㈣米。…見 12+=ΐ=^結構，㈣糊槪_猶的 25的一 40的一 13(^求項1所述之魏構’其+該城器具有大於約 14.如請求項1所述之該結構，其中該電感器具有大 Q值。 、 15.如請求項1所述之該結構，更包含—接觸塾，其包含人+ idi—=丄該介層窗在該基板中露出—1/0端： 蓋在:保護層，該保護層位在—導電襯墊之上之 1共； Jil- ° 田 16.如請求項15所述之該結構，其中該導電襯墊包含— ί ί tu’m包含&，侧_包含n/ 20 201036127 17. 如請求項16所述之該結構，更包含一鋁(八1)或Au線路，導電 性地接合至該接觸墊。 18. 如請求項16所述之該結構，更包含在該保護層上的一墊限制 冶金層，及在該墊限制冶金上的一焊球。 19·如請求項18所述之該結構，其中該墊限制冶金包含選自& 層、AU層、⑶層、及欽鶴(TiW>層所組成群組 ❹ 之—或更多層，且該焊球包含Pb或Pb/Sn合金。 15胃所述之該結構，其巾該1感__面係在和該 接觸墊的一頂面不同的一平面中。 15 1述t該結構，其中相對於該介電層之-頂面， ^電感态的一頂面尚於的該接觸墊之該頂面。 22·如請求項1所述之該結構，更包含： ❹ 二1/0端墊，形成於該基板中；以及 頂面、-端塾’該凸起接觸墊具有一 在〜半導體基板上形成之該下方部分延伸該固定距離到 介電層上方。人电g中、以及一上方部分延伸到該 23. 包含」導電她及其，6峨缝賴下方部分 包含該核心導體。，，且該凸起接觸墊的該上方部分 24. 如請求項23所述之該結構，其中該核 心導體為Cu，及該襯墊 21 201036127 包含TaN及Ta所形成的一雙層。 25. 如請求項23所述之該結構，其中該上方部分更包含在該凸起接 觸塾之该上方部分的該頂面及側壁上的一導電保護層。 26. 如請求項25所述之該結構，其中該保護層包含—炖芦 Ni層之上的一 Au層。 曰4隹 27.如請求項26所述之該結構，更包含一 A1或Au線路， ❹ 地接合至該凸起接觸墊。 糾口請求項26所述之該結構’更包含在該保護層上的一襯塾限制 冶金層’以及在該襯墊限制冶金上的一焊球。 糾口請，項28所述之該結構，其中該襯塾限制冶金包含選自q ί展層、AU層、CU層、及TiW層所組成群組之一或更 夕層’且該烊球包含Pb或Pb/Sn合金。 〇 所述之其中該電感器的該頂面係在和該凸 起接觸墊的一頂面不同的一平面中。 31.如請求項22所述之該結構，其中相對於該 電感器的一頂面高於的該凸起接觸墊之該頂面。s °人 22
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