TW200924094A - Semiconductor device having bonding pad above low-k dielectric film and manufacturing method therefor - Google Patents

Semiconductor device having bonding pad above low-k dielectric film and manufacturing method therefor Download PDF

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Publication number
TW200924094A
TW200924094A TW097149109A TW97149109A TW200924094A TW 200924094 A TW200924094 A TW 200924094A TW 097149109 A TW097149109 A TW 097149109A TW 97149109 A TW97149109 A TW 97149109A TW 200924094 A TW200924094 A TW 200924094A
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Taiwan
Prior art keywords
wiring
film
semiconductor device
dielectric film
low dielectric
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TW097149109A
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English (en)
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TWI315090B (en
Inventor
Yoshihisa Matsubara
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Nec Electronics Corp
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Publication of TW200924094A publication Critical patent/TW200924094A/zh
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Publication of TWI315090B publication Critical patent/TWI315090B/zh

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Description

200924094 九、發明說明： 【發明所屬之技術領域】 本發明係關於具有低介電率膜，且經改良焊接用焊墊構造 的半導體裝置及其製造方法。 【先前技術】 近年’為達成半導體裝置細微化，便有採用雙鑲嵌法的多 層佈線技術。而且，因為因應半導體裝置細微化及高速化的要 求，便有開發採用在氧化膜中摻雜入有機基的CVD膜、或由無 r 機或有機材料所構成的塗布膜，將層間絕緣膜低介電率化，俾 降低電氣信號傳輸的技術。 第13圖所示係具低介電率膜之習知半導體裝置的剖面圖。 如第13圖所示，在具擴散層6〇la的基板6〇1上形成低介電率 膜602,在該低介電率膜6〇2内，形成由佈線6〇4與耦接介層窗 603複數積層而成的多層佈線構造。在最上層佈線6〇4上的既定 位置處形成焊接墊605,並在該焊墊605上耦接著金屬搭線6〇6。 隨上述低介電率膜的導入而加速裝置的多機能化，電氣信 、 號輸出入用焊接墊605的數量將增加，焊接墊6〇5佔半導體裝 置的面積比率將增加。隨此焊墊面積比率的增加，窄焊墊間距 化與焊墊尺寸縮小化將加速。第14圖所示係說明焊墊間隔與焊 墊尺寸的平面圖。如第14圖所示，焊墊尺寸128係從習知的 ΙΟΟμιη方塊以上，縮小為8〇μιη方塊、6〇μηι方塊。焊墊間隔〖Μ 在習知ΙΟμιη以上，但是現況僅能確保5μηι程度。所以，焊墊 間距亦將窄小化。隨此現象，焊接墊與金屬搭線間的 將縮小。 在上述窄焊墊間距焊接搭線技術、與供達成細微化/高速化 的低介電率膜共存的前端裝置方面，於焊接搭線時，應力與衝 2118-6681A-PF 5 200924094 :焊接墊6°5的窄小範圍内。所以’如第13圖所示， 門之只塾6〇5下層發生龜裂術的問題，與在與焊墊605 介電率膜602剝落的問題4種低介電率膜 的=6〇7或剝落，不僅將造成焊接不良與妨礙電氣信號傳 别月少且將因水分吸濕而街生佈線腐钮 ^明顯劣化情況發生。而且，在焊接墊 銅佈線604將裸露出並遭氧化，而已氧化的銅佈線綱與谭藝 6〇5間的密接性將降低，導致焊接搭線強度降低的問題發生。 為求解決該等問題，便有提案藉由將烊接塾令所使用的金 屬膜，施打多層重疊積層，而提昇電極部對谭接時所產生衝擊 的财久性與層間密接性之方法（例如參照專利文獻^。但是，此 方法雖在焊接塾能確保某程度大小的情況時屬有效，但是當融 合應力/衝擊集中於窄小範圍的窄間距化技術之情況時，因為焊 墊屬於積層構造，因而在焊接時將有焊塾薄膜材料間發生剝落 的顧慮。所以，此方法並;^:法應付料的窄焊㈣距。況且， 其製作方法、步驟管理方法較為複雜，變成較難穩定量產的可 能性頗高。 另一方面，有提案將較層間絕緣膜材料的耐衝擊性更強的 構造體配置於谭塾下方，而補強焊接塾下層的方法（例如參照專 利文獻2)。第15圖所示係具補強佈線的習知半導體裝置剖面圖。 【專利文獻1】 曰本專利特開平11-340319號公報 【專利文獻2】 曰本專利特·開平11-54544號公報 【發明内容】 (發明欲解決之課題） 2118-6681A-PF 6 200924094 補強佈線與信號配線係獨 未具裝置的機能。因而晶 分，導致晶片面積無法縮 但是，上述習知的半導體裝置， 立，且焊接墊下端的補強佈線構造並 粒尺寸便將浪費此補強佈線構造的部 小的問題發生。 1明乃為解決上述習知課題而所構思，其第丨目的在於 k供一種具〶機械強度焊塾構造的半導體裝置。此外，本發明 之第2目的在於提供-種具有可將半導體晶片小型化之焊墊構 造的半導體裝i。 洱墊構 f (供解決課題之手段) 且具有機械強度較低於氧化石夕 本發明的半導體裝置係包括 在基板上所形成的保護元件 形成於上述保護元件上方， 膜的低介電率膜； 具有在上述保護元件上方且上述低介電率膜内，形成網狀 之電源佈線、與接地佈線的網狀佈線’且電祕於上述保護元 件的網狀佈線； 形成於上述網狀佈線與低介電率膜上的氧化矽膜；以及 在上述網狀佈線上方且氧化矽膜上所形成的焊接墊。 在本發明的半導體裝置中，上述保護元件最好為電容元 件、二極體或電晶體。 在本發明的半導體裝置中，上述電源佈線與上述接地佈線 的佈線寬度，最好為佈線間隔的2倍以上大小。 在本發明的半導體裝置中，上述網狀佈線最好當作上述低 介電率膜的補強構造使用。 _ 本發明的半導體裝置係包括： 形成於基板上，且具有機械強度較低於氧化矽膜的低介電 2118-6681A-PF 7 200924094 率膜； 線之述低介電率膜内形成網狀的電源佈線、與接地佈 線之線，且上述電源佈線構成保護元件的網狀佈線； == 狀佈線與低介電率膜上所形成的氧化石夕膜；以及 在上述氧化矽膜上所形成的焊接墊。 在本發明的半導體裝置中，上述 ^ ^ ^ 疋電源佈線與上述接地佈線 的佈線見度，最好為佈線間隔的2倍以上大小。 在本發明的半導體裝置中，上述網狀佈 介電率膜的補強構造使用。 田作上述低 本發明的半導體裝置之製造方法係包括： 在基板上形成保護元件的步驟； 形成覆蓋著上述保護元件之層間絕緣膜的步驟； 在上述層間絕緣膜内形成插塞的步驟； 在上述層間絕緣膜與插塞上，形成具有機械強度較低 化矽膜之低介電率膜的步驟； 、 採用鑲嵌法在上述低介電率膜内，將具有電源佈線與接地 佈線的網狀佈線，形成耦接於上述插塞狀態的步驟； 在上述網狀佈線與上述低介電率膜上，形成氧化矽膜的 驟；以及 、’ 在上述網狀佈線上方且氧化矽膜上，形成焊接墊的步驟。 在本發明的半導體裝置之製造方法中，最好依上述電源佈 線與上述接地佈線的佈線寬度，在佈線間隔之2 Λ' ^ σ Α上大小的 万式，形成上述網狀佈線。
在本發明的半導體裝置之製造方法中，最好包括上述保上 元件形成電容元件、二極體或電晶體的步驟。 I (發明之效果） 2118-6681A-PF 8 200924094 依照本發明’如上述所說明，藉由將網狀佈線使用為低介 電率膜的補強構造’便可提供具較高機械強度，且能將半導體 曰曰片小型化之焊塾構造的半導體裝置。 【實施方式】 以下，參照圖式，針對本發明實施形態進行說明。圖中， 就相同或相當的部分便賦予相同元件符號，並簡化或省略其說 明0 本發明乃著眼於在半導體晶片的I/〇.(I/〇Bi〇ck)中，保護 70件用電源網狀佈線構造兼用為低介電率膜補強構造。一般 璋所必要的電路元件（以下稱「保護元件」），有如：去輕電容器 元件、Peh 驅動 H、Neh 驅動器、ESD(EleetrQ_Statie 此咖 保護二極體。在該等保護元件中，具大面積者乃為電容元件與 一極體’驅動器則屬於較小面積。所以，為將1/〇埠小型化， 便如下述所說明’兼用電容元件與二極體用電源網狀佈線構 造、及低介電率膜補強構造的方式，乃屬有效的方法。 實施形態1. 本發明之實施形態i係針對將保護元件用電源網狀佈線構 造，兼用為低介電率膜補強構造的情況進行說明。帛一 係在本實施形態i中，保護元件的電路圖。如第ι圖所示，= 埠的保護7G件10係具有二極體u與電容元件12。二極體U鱼 電容元件！2係透過電源佈，線13而搞接於電源電位㈤句，且透 過接地佈線14而搞接於接地電位（GND)。 第2圖所示係㈣本實施形態丨之半導體裝置的 第3圖係第2圖所示半導體裝置的a_a,剖面圖。第4 θ 圖所示半導體裝置的Β-Β1剖面圖。 ' 如第2圖〜第4圖所示，在基板1〇1的ρ+型石夕基板上，形成 2118-6681A-PF 9 200924094 鎖存防止用p+擴散層117a、電容元件119用P+擴散層117b、及 二極體用N+擴散層118。該等擴散層117a，117b，118係藉由採用 STI(shall〇w trench isolation)法等所形成的元件隔離j 21而相互 隔離。利用P+擴散層117b、與由該P+擴散層117b上所形成矽 膜構成的閘極122，而構成電容元件119。依覆蓋著二極體118 與電各元件119之方式，在基板1 〇 1上形成層間絕緣膜丨的 氧化矽膜。在氧化矽膜102内，形成複數個執行二極體118或 電容元件119、與電源佈線116間之耦接，以及擴散層U7a與 接地佈線115間之耦接的插塞120。 在氧化矽膜102上，形成具有機械強度/硬度較低於該氧化 矽膜102的低介電率膜103。低介電率膜1〇3係具有3以下之介 電常數的CVD膜或塗布膜，具體而言，乃如 MSQ(methylSilseSqUi〇xane)膜、HSQ(hydr〇gen 膜、有機聚合物膜（例如道化學公司製製之SiLK(註冊商標））、 或在該等中導入細孔的膜（實際上為該等膜所積層的膜）。 在低介電率膜103内，形成分別具有第i佈線1〇6、第2 佈線107、第3佈線108及第4佈線1〇9,以及耦接該等佈線的 介層窗123，124，125之電源佈線n6及接地佈線115。換句話說， 在機械強度較低於氧化矽膜102的低介電率膜1〇3内，電源佈 線116與接地佈線115所形成的網狀電源網狀佈線將形成區域 佈線。電源佈線116係形成於二極體118與電容元件119上方 的低介電率膜103内，並透過插塞12〇而耦接於N+擴散層 或閘極122。接地佈線115係形成於電源佈線116外周（即H，位 於二極體118與電容元件119外周的p+擴散層U7a上方之低介 電率膜103内），並透過插塞12〇而耦接於p+擴散層丨】％。 如第2圖所示，電源佈線116與接地佈線ιΐ5係依—定的 2118-6681A-PF 10 200924094 佈線寬度與佈線間隔規則的形成。而且，在本實施形態1中， 電源記線116與接地佈線115係佈線寬度形成佈線間隔之2倍 以上的狀態。換句話說，電源配線116之佈線寬度對佈線間隔 的比率（=佈線寬度/佈線間隔）在2以上（容後詳述）。 在電源佈線116與接地佈線115上、及低介電率膜1 〇3上， 形成雙層氧化矽膜1 〇4a，104b。在下層的氧化矽膜1 〇4a内，於 晶片内部信號線的第4佈線1〇9上，形成第5配線110與第6 佈線111 ’以及耦接該等佈線的介層窗126、127。換句話說， 在氧化石夕膜104a内形成接地伟線。在上層的氧化石夕膜1 〇4b中， 則依裸露出第6佈線ill的方式形成開口部，並在該開口部内 與氧化秒膜104b上形成焊接墊ip的鋁佈線。焊接墊n2係形 成可吸收焊接金屬搭線114時所產生衝擊的膜厚，且對製品出 貨前的動作確認用探針測試具耐久性的膜厚。另外，配合用途， 可將銅佈線當作焊墊112使用。最上層的第6佈線U1係構成 所焊接搭線的信號線之端子。此外，對焊接墊112當施行探針 測試時’便施加利用探針（針）進行切削的機械衝擊。 在氧化珍膜1 〇4b與鋁佈線112上，形成當作防止水分渗入 用保護膜105的氮化矽膜。在該氮化矽膜1〇5中形成，在裸露 出於該開口部113底部的鋁佈線112上，耦接著供執行與外部 間之電氣信號輸出入用的金屬搭線114。在施行焊接搭線時，基 板101被加熱至約25(TC〜350°c的溫度，並對該金屬搭線114 施加超音波振動與荷重。金屬搭線114乃由如金或鋁合金之類 的材料所形成。 其次’針對上述半導體裝置之製造方法進行說明。 第5圖所示係說明本實施形態1的半導體裝置之製造方法 的步驟剖面圖。 2118-6681A-PF 11 200924094 • 首先，如第5⑷圖所示，採用STI法在基板101内形成元 件隔離m之後，利用施行植入與熱處理，巾在基板而上層 形成擴散層117a，117b，118。然後，形成多晶石夕膜，並藉由對該 多晶石夕膜施行圖案化處理，便在所需位置處形成閉極122。藉 此，便形成二極體118與電容元件119。 曰 其次，依覆蓋著二極體118與電容元件119之方式，形成 層間絕緣膜102的氧化石夕膜。然後，利用微影技術與乾式敲刻 處理，在氧切膜1()2内形成洞。之後，藉由在該洞内埋藏著 ( 導電膜（例如鎢臈），而形成複數插塞120。 其次，如第5(b)圖所示，在插塞120與氧化矽膜1〇2上， 禾1用D法或塗布法形成低介電率膜1 〇3a。然後，利用微影技 術與乾式钱刻處理，在低介電率膜1〇3a内形成佈線1〇6用溝渠 之後，再依埋藏此溝渠之方式沉積著導電膜，並利用cMp法去 除低介電率膜l〇3a上不需要的導電膜。依此便在低介電率膜 103a内形成佈線106。 其次，在低介電率膜l〇3a與佈線1〇6上形成低介電率膜 103b °雙層低介電率膜1Q3a，1()3b種類亦可互異（相關後述的低 介電率膜亦同）。利用微影技術與乾式蝕刻處理，在低介電率膜 l〇3b内形成介層窗123用洞。然後，依埋藏此洞之方式沉積著 導電膜，並利用CMP法去除低介電率膜103b上不需要的導電 膜。依此便在低介電率膜1 〇3b内形成介層窗123。 以下利用同樣的方法，在低介電率膜l〇3c内形成佈線 107,並在低介電率膜1〇3d内形成介層窗124。然後，在低介電 率膜l〇3e内形成佈線1〇8，並在低介電率膜1〇3f内形成介層窗 125 °更於低介電率膜i〇3g内形成佈線1〇9。 依此採用單鑲嵌法，在低介電率膜103(103a〜l〇3g)内形成 2118-6681A-PF 12 200924094 . 電源佈線116與接地佈線115。 另外，亦可取代上述單鑲嵌法改為雙鑲嵌法，形成網狀佈 線。第6圖所示係本實施形態丨中，採用雙鑲嵌法形成網狀佈 線的步驟剖面圖。 依上述方法在低介電率膜l〇3a内形成佈線1〇6之後，再如 第6圖所示，於基板整面上形成低介電率膜1〇3h。其次，在低 介電率膜103h内形成佈線107用溝渠，更形成介層窗123用洞_。 然後，便依埋藏此溝渠與洞之方式沉積著導電膜，並利用cMp ^法去除低介電率膜103h上的不需要導電膜。依此便在低介電率 膜103h内形成介層窗123與佈線1〇7。 以下依同樣的方法，在低介電率膜1〇3h與佈線1〇7上形成 低介電率膜103i，並在此低誘電率膜1〇3i内形成介層窗124與 佈線108。更於低介電率膜1〇3i與佈線1〇8上形成低介電率膜 i〇3j’並在此低介電率膜103』内形成介層窗125與佈線1〇9。' 依此便在低介電率膜103(103a，1〇3h，1〇31)内形成電源佈線ιΐ6 與接地佈線115。 _ 其次，如第5(c)圖所示，採用上述的單鑲嵌法或雙鑲嵌法， 、在氧化矽膜l〇4a内形成佈線110，1U與介層窗126，127。然後， 在^化石夕膜104a上形成氧化膜104b，並在氧化石夕膜1〇4b内依 裸露出佈線111的方式形成開口部。在此開口部内面與氧化石夕 膜l〇4b上形成紹膜，並藉由對該銘膜施行圖案化處理，便形成 焊接墊U2的鋁佈線。然後，在氧化矽膜104b與鋁佈線112上， 利用CVD法形成保護膜1〇5的氮化石夕膜。接著，利用微影技術 與乾式敍刻處理，在氮化石夕膜1〇5内依裸露出銘配線ιΐ2之方 式形成開口部113。 . 然後，在對基板101施行加熱的狀態下，對金屬搭線 2118-668ΙΛ-PF 13 200924094 • 施加超音波振動與加重，便將金屬搭線114耦接於鋁佈線112。 如上所說明，在本實施形態1中’透過插塞120而耦接於 二極體119與電容元件118上的電源佈線116,兼用低介電率膜 103的補強構造。而且，透過插塞12〇耦接於鎖存對策用擴散層 117a的接地佈線115 ,兼用低介電率膜1〇3的補強構造。換句 話說，保護元件用電源網狀構造，兼用低介電率膜1〇3的補強 構造。藉此，便將提昇焊接墊112下層所形成的低介電率膜 機械強度，且在I/O埠中可將低介電率膜1〇3的補強佈線有效 ( 的活用為保護元件用佈線。 第7圖所示係半導體裝置的焊接墊配置平面圖。第7(甸圖 料接塾131單行配置情況時的圖示，第7⑻圖係焊接墊132 父錯狀配置情況θ㈣圖示。帛8圖所示係技術節點與焊接塾尺 寸間之關係圖。 如第8圖所示，單行排列的焊接墊尺寸（長度、及交錯狀 配置的焊接墊間距C，乃隨技術節點的提高而變小。尺寸B係 以普通製品的尺寸B(General)為中心，具有從高層次系（高附加 價值）製品尺寸B(Highend)，至低層次系（低附加價值）製品尺寸 B(10wend)的寬度。另外，當縮小尺寸B之際，亦有增加尺寸a， 確保接觸面積的情況。此外，間距c係設定為較尺寸b更小 數值。 依此，便在上述尺寸的焊接墊下方，配置著兼用補強構造 的網狀佈線，藉由將該網狀佈線耦接於半導體元件，便可在焊 接塾下方配置著具有機能的半導體元件。所以，僅焊接塾的大 小，便可提升設計裕度。另外，藉由在焊接墊下方，配置著在 其他地方所配置的元件，便可縮小半導體晶片的面積，可降低 半導體裝置的製造成本。而且，藉由半導體晶片的小型化，便 2118-6681A-PF 14 200924094 可達搭載著該晶片之行動通信機器等電氣通信裝置的小型化。 再者，如上述，電源佈線116的佈線寬度與佈線間隔之比 率（以下稱「電源佈線寬度/間隔比」），最好在2以上，尤以設 計基準所許容的最大佈線寬度與最小佈線間隔為佳。例如，可 將佈線寬度設為G.2〜3μιη，將佈線間隔設為第9圖 所不係在本實施形態丨巾，金屬搭㈣裂試驗 寬度/間隔比依存性圖。如第9圖所示，電源佈線寬度/間隔比在 、的匱況時不良率將為零，得知將可提供具有優越焊接強
度（機械強度）的焊墊構造及半導體裝置。而且，本發明者更確認 到不僅接地佈線115,藉由將接地佈線115與電源佈線ιΐ6的配 線寬度/間隔比設為此適#|請，便可獲得優越的焊接強度，可 防止電源部分的壓降。 、再者:當電源佈、線116與接地佈、線115採用c讀後佈線的 It况時’藉由設定為最大佈線寬度3μηι、佈線間隔_程度， 便可降低因Οι-CMP所發生的佈線侵蚀情^依此便可更加 升半導體裝置的可靠性。 另外’在本實施形態i巾’層間絕緣膜1()2雖採用氧化石夕 膜，但是亦可取代氧切膜改為低介電率膜。此情況下，亦可 藉由層間絕緣膜102内所形成的插塞，獲得較高的焊接強 述實施形態2亦同）。 再者，除二極體118與電容元件119之外，當將"◦蜂中的 MIS電晶體形成保護元件的情況時，亦可適用本發明。換句^ 說，可將MIS電晶體用電源佈線兼用為低介電率膜的補強構造。 實施形態2. 在上述的實施形態1中，乃針對焊接搭線組裝用半導體裝 置進行說明’而本發明的實施形態2則針對覆晶組裝用半導體 2118-6681A-PF 15 200924094 裝置進行說明。以下，便以與實施形態丨之半導體裝置間的差 異點為中心進行說明。 第ίο圖所示係本實施形態2的半導體裝置說明剖面圖。 如第10圖所示，在二極體119與電容元件118上方的低介 電率膜103内形成電源佈線116，並在鎖存防止用擴散層“π 上方的低介電率膜103内形成接地佈線115。該等保護元件用電 源佈線116與接地佈線115係兼用為低介電率膜1〇3的補強構 造。在電源佈線116與接地佈線115上形成雙層氧化石夕膜 114a，114b，在上層的氧化矽膜U4b上形成焊接墊112，在焊墊 112上形成保護膜105,並在該保護膜1〇5内所形成的開口部ιΐ3 底部裸露出焊塾112。在開口部113内與保護膜1〇5上形成電極 2〇〇 ’在該電極2〇〇上形成當作覆晶元件2〇1用的凸塊。其他構 造均如同實施形態1。 組裝時所要求的機械強度係焊接搭線構造較覆晶構造嚴 格。所以，藉由將實施形態丨中所說明的焊接搭線構造，改變 為本實施形態2所說明的覆晶構造，得知將可達本發明的效果。 故’本實施形態2將可獲得如同實施形g i中所述的效果。 本發明的實施形態3係針對將金屬電容器使用為保 的情況進行說明。 第11圖所示係本實施形態3的半導體裝置說明剖面圖，% 12圖係第U圖所示半導體裝置的電源佈線平面圖。 ，第圖所示’電源佈線116形成梳齒狀。 屬電容元件，如第7圖所示，並_於: 車乂第1佈、線1〇6更下層處所形成，如擴散層im，ii8、_ 晶體之類的保護元件。僅在接地佈線115下方的氧化如 2118-6681A-PF 16 200924094 ，内形成插塞120,透過該插塞120而耗接於接地佈線115與擴散 層117a。因為在電源佈線116下方的氧化石夕膜1〇2内並未形成 插塞，因而不同於實施形態丨，2,並無法將氧化矽膜ι〇2取代為 低介電率膜。 在本實施形態3巾，將構成金屬電容元件的電源佈線ιΐ6 兼用為低介電率膜103的補強構造。而且，將透過插塞12〇而 麵接於鎖存對策用擴散層117a的接地佈線出，兼用為低介電 率膜103的補強構造。所以，如同實施形態丨，將提昇焊接墊 【 112下層所形成低介電率膜的機械強度，且可將1/〇蟑之保 護元件的金屬電容元件116,有效的應用為低介電率膜1〇3的補 強佈線。故，可縮小半導體晶片的面積，可降低半導體裝置的 製成本。甚至藉由半導體晶片的小型化，便可達搭載著該晶 片的行動通信機器等電氣通信裝置之小型化。 再者，在本實施形態3中，亦是藉由將電源佈線116與接 地佈線115的佈線寬度/間隔比設為2以上，便可提升金屬搭線 斷裂試驗良率，可獲得具優越焊接強度的半導體裝置。 【圖式簡單說明】 ζ Κ 第1圖係本發明實施形態1中，保護元件的電路圖。 第2圖係說明本發明實施形態1之半導體裝置的平面圖。 第3圖係第2圖所示半導體裝置的Α-Α，剖面圖。 第4圖係第2圖所示半導體裝置的Β-Β，剖面圖。 第5圖（a)〜(c)係說明本發明實施形態1的半導體裝置之製 造方法的步驟剖面圖。 第6圖係本發明實施形態1中，採用雙鑲嵌法形成網狀佈 線的步驟剖面圖。 第7圖（a)〜(b)係半導體裝置的焊接墊之配置平面圖。 2118-6681A-PF 17 200924094 第8圖係技術節點與焊接墊尺寸間之關係圖。 第9圖係本發明實施形態1中，金屬搭線斷裂試驗良率的 電源配線寬度/間隔比依存性圖。 第1〇圖係說明本發明實施形態2之半導體裝置的剖面圖 ^圖係說明本發明實施形態3之半導體裝置的剖面圖 第12圖係第11圖所示半導體裝置的電源佈線平面圖。 ^3圖係具有低介電率膜的習知半導體裝置剖面圖。 第14圖係焊㈣距與料尺寸的說明平面圖。 第15圖係具有補強佈線的習知半 主要元件符號說明】 10 保護元件 11 二極體 12 電容元件 13 電源佈線 14 接地佈線 101 基板 102 層間絕緣膜（氧化矽 103 低介電率膜 104a,104b 氧化石夕膜 105 保護膜（氮化矽臈） 106 第1佈線 107 第2佈線 108 第3佈線 109 第4佈線 110 第5佈線 111 第6佈線
2118-6681A-PF 18 200924094 112 焊接墊（鋁佈線） 113 開口部 114 金屬搭線 115 接地佈線 116 電源佈線 117a,117b P+擴散層 118 N+擴散層（二極體) 119 電容元件 120 插塞 121 元件隔離 122 閘極 123 第1介層窗 124 第2介層窗 125 第3介層窗 131,132 焊接墊 200 電極 201 覆晶元件 2118-6681A-PF 19

Claims (1)

  1. 200924094 十、申請專利範圍： 1.一種半導體裝置，包括： 電路元件，形成於基板上； 低介電率膜，形成於該基板上方； 網狀佈線，具有在該電路元件之形成範圍上方且該低介電 率膜内網狀形成之電源佈線與接地佈線的網狀佈線，且其電耦 接於該電路元件； 氧化矽膜’形成於該低介電率膜上；以及 焊接墊，形成於該電路元件之形成範圍上方且氧化矽膜上。 2·如申請專利範圍第丨項之半導體裝置，其中，該電路元件 包括電容元件、二極體或電晶體之至少一個。 s亥電路元件 3.如申請專利範圍第1項之半導體裝置，其中 係電容元件。 4.如申請專利範圍第1項之半導體裂 係二極體或電晶體 5.如申請專利範圍第丨項之半導 包圍該電源佈線。 ♦體破置，其中，該接地佈線 /·如申請專利範圍第！項之半導體裝置，其中， 與該接地佈線的佈線寬度，係佈線間隔的2仵以上大彳’、、、、 入如申請專利範圍第！項之半導體裝置，° ζ接 具有被焊接的金屬搭線。 忒烊接墊上 1項之半導體裴 8·如申請專利範圍第 形成有凸塊。 置，其中，該焊接墊上 2118-6681A-PF 20
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