TWI315090B - Semiconductor device having bonding pad above low-k dielectric film and manufacturing method therefor - Google Patents

Semiconductor device having bonding pad above low-k dielectric film and manufacturing method therefor Download PDF

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Publication number
TWI315090B
TWI315090B TW097149109A TW97149109A TWI315090B TW I315090 B TWI315090 B TW I315090B TW 097149109 A TW097149109 A TW 097149109A TW 97149109 A TW97149109 A TW 97149109A TW I315090 B TWI315090 B TW I315090B
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Taiwan
Prior art keywords
wiring
semiconductor device
film
low dielectric
dielectric film
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TW097149109A
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English (en)
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TW200924094A (en
Inventor
Matsubara Yoshihisa
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Nec Electronics Corporatio
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Publication of TW200924094A publication Critical patent/TW200924094A/zh
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Description

1315090 • 九、發明說明： 【發明所屬之技術領域】 本發明係II於具有低介電㈣，且㈣良烊接用焊塾構造 * 的半導體裝置及其製造方法。 % 【先前技術】 近年，為達成半導體裝置細微化，便彳採用雙鎮嵌法的多 層佈線技術。而且，因為因應半導體裝置細微化及高速化的要 求，便有開發採用在氧化膜中摻雜入有機基的cvd膜、或由無 籲機或有機材料所構成的塗布膜，將層間絕緣膜低介電率化，俾 降低電氣信號傳輸的技術。 第13圖所耗具低介電率膜之習知半導㈣置的剖面圖。 如第13圖所示，在具擴散層6〇la的基板6〇1上形成低介電率 膜602,在該低介電率膜6〇2内，形成由佈線6〇4與耦接介層窗 6〇3複數積層而成的多層佈線構造。在最上層佈線上的既定 位置處形成焊接塾605,並在該焊墊605上搞接著金屬搭線_。 〇奴上述低介電率膜的導入而加速裝置的多機能化，電氣信 _號輸出入用焊接墊605的數量將增加，焊接墊6〇5佔半導體裝 置的面積比率將增加。隨此焊塾面積比率的增加，窄焊塾間距 化與焊墊尺寸縮小化將加速。第14圖所示係說明焊墊間隔與焊 墊尺寸的平面圖。如第14圖所示，焊墊尺寸128係從習知的 ΙΟΟμηι方塊以上，縮小為8〇fXm方塊、方塊。焊塾間隔IN ‘ 在習知ΙΟμιη以上，但是現況僅能確保5μιη程度。所以，焊墊 間距亦將窄小化。隨此現象，焊接墊與金屬搭線間的耦接面積 將縮小。 在上述窄焊墊間距焊接搭線技術、與供達成細微化/高速化 的低介電率膜共存的前端裝置方面，於焊接搭線時，應力與衝 2118-6681A-PF 5 1315090 擊將集中於焊接墊605的窄小範圍内。所以，如第13圖所示， 將產生在焊墊605下層發生龜裂607的問題，與在與嬋墊6〇5 間之界面處出現低介電率膜602剝落的問題。此種低介電率膜 602的龜裂607或剝落’不僅將造成焊接不良與妨礙電氣信號傳 輸等情形，且將因水分吸濕而衍生佈線腐蝕，導致半導體裝置 可靠性明顯劣化情況發生。而且，在焊接墊6〇5下方所配置的 銅佈線604將裸露出並遭氧化，而已氧化的銅佈線6〇4與焊墊 605間的密接性將降低，導致焊揍搭線強度降低的問題發生。 | 為求解決該等問題，便有提案藉由將焊接墊中所使用的金 屬膜，施行多層重疊積層，而提昇電極部對焊接時所產生衝擊 的耐久性與層間密接性之方法（例如參照專利文獻1：^但是，此 方法雖在焊接墊能確保某程度大小的情況時屬有效，但是當融 合應力/衝擊集中於窄小範圍的窄間距化技術之情況時，因為焊 墊屬於積層構造，因而在焊接時將有焊墊薄膜材料間發生剝落 的顧慮。所以，此方法並不法應付近年的窄焊墊間距。況且， 其製作方法、步驟管理方法較為複雜，變成較難穩定量產的可 能性頗高。
I 另一方面’有提案將較層間絕緣膜材料的耐衝擊性更強的 構造體配置於焊墊下方’而補強焊接墊下層的方法（例如參照專 利文獻2)。第15圖所示係具補強佈線的習知半導體裝置剖面圖。 【專利文獻1】 曰本專利特開平11-340319號公報 【專利文獻2】 曰本專利特開平11-54544號公報 【發明内容】 (發明欲解決之課題） 2118-6681A-PF 6 1315090 立但是’上述習知的半導體裝置，補強佈線與信號配線係獨 ’且焊接墊下端的補強佈線構造並未具裝置的機能。因而晶 ^寸便將浪費此補強佈線構造的部分，導致晶片面積無 小的問題發生。 本發明乃為解決上述習知課題而所構思，其第ι目的在於 ^供一種具高機械強度焊墊構造的半導體裝置。此外，本發明 之第2目的在於提供一種具有可將半導體晶片小型化之焊墊構 造的半導體裝置。
(供解決課題之手段） 本發明的半導體裝置係包括： 在基板上所形成的保護元件； 形成於上述保護元件上方，且具有機械強度較低於氧化矽 膜的低介電率膜； 具有在上述保護元件上方且上述低介電率膜内，形成網狀 之電源佈線、與接地佈線的網狀佈線，且電耦接於上述保護元 件的網狀佈線； 形成於上述網狀佈線與低介電率膜上的氧化矽膜；以及 在上述網狀佈線上方且氧化矽膜上所形成的焊接墊。 在本發明的半導體裝置中，上述保護元件最好為電容元 件、二極體或電晶體。 在本發明的半導體裝置中，上述電源佈線與上述接地佈線 的佈線寬度’最好為佈線間隔的2倍以上大小。 在本發明的半導體裝置中，上述網狀佈線最好當作上述低 介電率膜的補強構造使用。 _ 本發明的半導體裝置係包括： 形成於基板上，且具有機械強度較低於氧化矽膜的低介電 2118-6681A-PF 7 1315090 率膜； 八有在上述低介電率膜内形成網狀的電源佈線、與接地神 線之網狀佈線’ j_上述電源佈線構成保護元件的網狀佈線； 在上述，狀佈線與低介電率膜上所形成的氧化石夕膜；以及 在上述氧化石夕膜上所形成的焊接墊。 在本發明的半導體裝置令，上述電源佈線與上述接地佈線 的佈線寬度，最好為佈線間隔的2倍以上大小。
在本發明的半導體裝置中，上述網狀佈線最好當作上述低 介電率膜的補強構造使用。 本發明的半導體裝置之製造方法係包括： 在基板上形成保護元件的步驟； 形成覆蓋著上述保護元件之層間絕緣膜的步驟； 在上述層間絕緣膜内形成插塞的步驟； 在上述層間絕緣膜與插塞上，形成具有機械強度較低於氧 化石夕膜之低介電率膜的步驟； 才木用鑲嵌法在上述低介電率膜内，將具有電源佈線與接地 佈線的網狀佈線’形成耦接於上述插塞狀態的步驟； 在上述網狀佈線與上述低介電率膜上，形成氧化矽膜的步 驟；以及 在上述網狀佈線上方且氧化石夕膜上，形成焊接墊的步驟。 在本發明的半導體裝置之製造方法中，最好依上述電源佈 線與上述接地佈線的佈線寬度，在佈線間隔之2倍以上大小的 方式，形成上述網狀佈線。 在本發明的半導體裝置之製造方法中，最好包括上述保護 疋件形成電容元件、二極體或電晶體的步驟。 (發明之效果） 2118-6681A-PF 8 1315090 依照本發明，如上诚nn ^ φ φ ^ .、 这所說明，藉由將網狀佈線使用為低介 電率膜的補強構造，便可挺一u ~ 晶片小型化之焊塾構造的半導體裝置。 ⑽牛導體 【實施方式】 以下，參照圖式’針對本發明實施形態進行說明。圖中， =相同或相當的部分便賦料同元件符號，並簡化或省略其說
本發明乃著眼於在半導體晶片的1/〇料/〇Β1_)中， •元件用電源網狀佈線構造兼用為低介電率膜補強構造。-般⑽ 埠所必要的電路元件（以下稱「保護元件」），有如：去輕電容器 兀件、Pch驅動器、Nch驅動器、Ε8Ι)(Ε1_〇彻^ DM 保護二極體。在該等保護元件中，具大面積者乃為電容元件與 一極體’驅動器則屬於較小面積。所以，為將1/〇埠小型化， 便士下述所說明’兼用電容元件與二極體用電源網狀佈線構 造、及低介電率膜補強構造的方式，乃屬有效的方法。 實施形態1. 本發月之實施开）態1係針對將保護元件用電源網狀佈線構 造，兼用為低介電率膜補強構造的情況進行說明。第丨圖所示 係在本實施形態1中，保護元件的電路圖。如第1圖所示，I/C) 埠的保護元件10係具有二極體u與電容元件12。二極體U與 電谷元件12係透過電源佈線13而搞接於電源電位（Vdd)，且透 、過接地佈線14而耦接於接地電位（GND)。 第2圖所示係說明本實施形態1之半導體裝置的平面圖。 第3圖係第2圖所示半導體裝置的A-A'剖面圖。第4圖係第2 圖所示半導體裝置的B-B'剖面圖。 如第2圖〜第4圖所示，在基板1〇1的p+型石夕基板上，形成 2118-6681A-PF 9 1315090 鎖存防止用P+擴散層117a、電容元件119用P+擴散層117b、及 二極體用N+擴散層118。該等擴散層117a，117b，118係藉由採用 STI(shallow trench isolation)法等所形成的元件隔離ι21而相互 . 隔離。利用P+擴散層117b、與由該P+擴散層117b上所形成矽 膜構成的閘極122’而構成電容元件119。依覆蓋著二極體118 與電容元件119之方式，在基板1〇1上形成層間絕緣膜1〇2的 氧化矽膜。在氧化矽膜102内，形成複數個執行二極體118或 電容元件119、與電源佈線116間之耦接，以及擴散層117&與 φ 接地佈線115間之耦接的插塞120。 在氧化梦膜102上，形成具有機械強度/硬度較低於該氧化 矽膜102的低介電率膜1〇3。低介電率膜103係具有3以下之介 電常數的CVD膜或塗布膜，具體而言，乃如 MSQ(methylSilsesqui〇xane)膜、HSQ(hydrogen silsesqui〇xane) 膜、有機聚合物膜（例如道化學公司製製之SiLK(註冊商標））、 或在該等中導入細孔的膜（實際上為該等膜所積層的膜）。 在低介電率膜103内’形成分別具有第1佈線1〇6、第2 佈線107、第3佈線108及第4佈線1〇9,以及耦接該等佈線的 • 介層窗123，124，125之電源佈線116及接地佈線115。換句話說， 在機械強度較低於氧化矽膜102的低介電率膜1〇3内，電源佈 線116與接地佈線115所形成的網狀電源網狀佈線將形成區域 佈線。電源佈線116係形成於二極體118與電容元件119上方 ' 的低介電率膜103内，並透過插塞120而輕接於n+擴散層ι18 - 或閘極I22。接地佈線115係形成於電源佈線110外周（即，位 於二極體118與電容元件119外周的P+擴散層117a上方之低介 電率膜103内），並透過插塞120而耦接於P+擴散層U7a。 如第2圖所示，電源佈線116與接地佈線丨丨5係依一定的 2118-6681A-PF 10 1315090 . 佈線寬度與佈線間隔規則的形成。而且，在本實施形態i中， 電源記線116與接地佈線115係佈線寬度形成佈線間隔之2倍 以上的狀態。換句話說，電源配線116之佈線寬度對佈線間隔 • 的比率（=佈線寬度/佈線間隔）在2以上（容後詳述）。 在電源佈線116與接地佈線115上、及低介電率膜丨〇3上， 形成雙層氧化矽膜104a，104b。在下層的氧化矽膜104a内，於 晶片内部信號線的第4佈線1〇9上，形成第5配線11〇與第6 佈線111 ’以及耦接該等佈線的介層窗126、127。換句話說， _ 在氧化矽膜104a内形成接地佈線。在上層的氧化矽膜104b中， 則依裸露出第6佈線111的方式形成開口部，並在該開口部内 與氧化矽膜104b上形成焊接墊112的鋁佈線。焊接墊丨12係形 成可吸收焊接金屬搭線114時所產生衝擊的膜厚，且對製品出 釦刖的動作確認用探針測試具耐久性的膜厚。另外，配合用途， 可將銅佈線當作焊墊112使用。最上層的第6佈線lu係構成 所焊接搭線的信號線之端子。此外，對焊接墊112當施行探針 測試時，便施加利用探針（針）進行切削的機械衝擊。 在氧化矽膜104b與鋁佈線ι12上，形成當作防止水分滲入 ® 用保護膜1〇5的氮化矽膜。在該氮化矽膜105中形成，在裸露 出於該開口部U3底部的鋁佈線112上，耦接著供執行與外部 間之電氣信號輸出入用的金屬搭線丨14。在施行焊接搭線時，基 板101被加熱至約25(TC〜35〇r的溫度，並對該金屬搭線114 ' 施加超音波振動與荷重。金屬搭線114乃由如金或鋁合金之類 . 的材料所形成。 其次，針對上述半導體裝置之製造方法進行說明。 第5圖所示係說明本實施形態1的半導體裝置之製造方法 的步驟剖面圖。 2118-6681A-PF 11 1315090 . 首先’如第5⑷圖所示，採用STI法在基板101内形成元 件隔離121之後，利用施行植入與熱處理，而在基板1〇1上層 形成擴散層117a，117b，118。然後，形成多晶矽膜，並藉由對該 多晶矽膜施行圖案化處理，便在所需位置處形成閘極122。藉 此，便形成二極體118與電容元件119。 其次，依覆蓋著二極體118與電容元件119之方式，形成 層間絕緣膜102的氧化矽膜。然後，利用微影技術與乾式蝕刻 處理，在氧化石夕膜1 〇2内形成洞。之後，藉由在該洞内埋藏著 • 導電膜（例如鎢膜），而形成複數插塞120。 其次’如第5(b)圖所示’在插塞120與氧化矽膜1〇2上， 利用CVD法或塗布法形成低介電率膜1〇3ae然後，利用微影技 術與乾式蝕刻處理，在低介電率膜1〇3a内形成佈線1〇6用溝渠 之後，再依埋藏此溝渠之方式沉積著導電膜，並利用CMp法去 除低介電率膜l〇3a上不需要的導電膜。依此便在低介電率膜 l〇3a内形成佈線1〇6。 其次，在低介電率膜l〇3a與佈線ι〇6上形成低介電率膜 103b。雙層低介電率膜1〇3a，1〇3b種類亦可互異（相關後述的低 •介電率膜亦同）。利用微影技術與乾式蝕刻處理，在低介電率膜 l〇3b内形成介層窗123用洞。然後，依埋藏此洞之方式沉積著 導電膜，並利用CMP法去除低介電率臈i〇3b上不需要的導電 膜。依此便在低介電率膜l〇3b内形成介層窗123。 ' 以下利用同樣的方法，在低介電率膜103c内形成佈線 - 107，並在低介電率膜103d内形成介層窗124。然後，在低介電 率膜103e内形成佈線108，並在低介電率膜1〇3f内形成介層窗 125。更於低介電率膜i〇3g内形成佈線1〇9。 依此採用單鑲嵌法’在低介電率膜1〇3(1〇3a〜1〇3g)内形成 2118-6681A-PF 12 1315090 電源佈線116與接地佈線115。 另外，亦可取代上述單鑲嵌法改為雙鑲嵌法，形成網狀佈 線。第6圖所示係本實施形態丨中，採用雙鑲嵌法形成網狀佈 線的步驟剖面圖。 依上述方法在低介電率膜1〇3a内形成佈線1〇6之後，再如 第6圖所示，於基板整面上形成低介電率膜1〇3h。其次，在低 介電率膜103h内形成佈線107用溝渠，更形成介層窗123用洞_。 然後，便依埋藏此溝渠與洞之方式沉積著導電膜，並利用cMp φ 法去除低介電率膜i〇3h上的不需要導電膜。依此便在低介電率 膜103h内形成介層窗123與佈線1〇7。 以下依同樣的方法，在低介電率膜103h與佈線107上形成 低介電率膜103i ’並在此低誘電率膜1〇3i内形成介層窗124與 佈線108。更於低介電率膜1〇3i與佈線1〇8上形成低介電率膜 l〇3j，並在此低介電率膜103]内形成介層窗125與佈線1〇9。 依此便在低介電率膜1〇3(1〇3a，1〇3h，1〇31)内形成電源佈線ιΐ6 與接地佈線115。 其次，如第5(c)圖所示，採用上述的單鑲嵌法或雙鑲嵌法， 春在氧化矽膜104a内形成佈線1HU11與介層窗126,127。然後， 在氧化矽膜1 〇4a上形成氧化膜1 〇朴，並在氧化矽膜1 〇4b内依 裸露出佈線111的方式形成開口部。在此開口部内面與氧化矽 膜104b上形成鋁膜，並藉由對該鋁膜施行圖案化處理，便形成 ' 焊接墊112的鋁佈線。然後，在氧化矽膜104b與鋁佈線112上， . 利用CVD法形成保護膜105的氮化矽膜。接著，利用微影技術 與乾式蝕刻處理，在氮化矽膜1〇5内依裸露出鋁配線U2之方 式形成開口部113。 然後，在對基板1〇丨施行加熱的狀態下，對金屬搭線114 2118-6681A-PF 13 1315090 • 施加超音波振動與加重，便將金屬搭線114耦接於鋁佈線112。 如上所說明，在本實施形態丨中，透過插塞12〇而耦接於 二極體119與電容元件118上的電源佈線116，兼用低介電率膜 1〇3的補強構造。而且，透過插塞120耦接於鎖存對策用擴散層 • 117a的接地佈線115，兼用低介電率膜103的補強構造。換句 話說，保護元件用電源網狀構造，兼用低介電率膜1〇3的補強 構造。藉此，便將提昇焊接墊112下層所形成的低介電率膜ι〇3 機械強度，且在I/O槔中可將低介電率膜1〇3的補強佈線有效 _ 的活用為保護元件用佈線。 第7圖所示係半導體裝置的焊接墊配置平面圖。第7(a)圖 係焊接墊131單行配置情況時的圖示，第7(b)圖係焊接墊132 交錯狀配置情況時的圖示。第8圖所示係技術節點與焊接墊尺 寸間之關係圖。 如第8圖所示，單行排列的焊接墊尺寸（長度）B、及交錯狀 配置的焊接墊間距C，乃隨技術節點的提高而變小。尺寸B係 以普通製品的尺寸B(General)為中心，具有從高層次系（高附加 價值）製品尺寸B(High end)，至低層次系（低附加價值）製品尺寸 » B(lOwend)的寬度。另外’當縮小尺寸b之際，亦有增加尺寸A， 確保接觸面積的情況。此外，間距（3係設定為較尺寸B更小的 數值。 依此，便在上述尺寸的焊接墊下方，配置著兼用補強構造 ‘的網狀佈線，藉由將該網狀佈線耦接於半導體元件，便可在焊 接墊下方配置著具有機能的半導體元件。所以，僅焊接墊的大 小，便可k升設計裕度。另外，藉由在焊接塾下方，配置著在 其他地方所配置的元件，便可縮小半導體晶片的面積，可降低 半導體裝置的製造成本。而且，藉由半導體晶片的小型化，便 2118-6681A-PF 14 1315090 可達搭載著該晶片之行動通信機器等電氣通信裝置的小型化。 再者’如上述’電源佈線116的佈線寬度與佈線間隔之比 率（以下稱「電源佈線寬度/間隔比」），最好在2以上，尤以設 • 計基準所許容的最大佈線寬度與最小佈線間隔為佳。例如，可 將佈線寬度設為〇_2〜3Pm，將佈線間隔設為0.1〜1·5μιη。第9圖 所示係在本實施形態丨中，金屬搭線斷裂試驗良率的電源佈線 I度/間隔比依存性圖。如第9圖所示，電源佈線寬度/間隔比在 2以上的情況時，不良率將為零，得知將可提供具有優越焊接強 • 度（機械強度）的焊墊構造及半導體裝置。而且，本發明者更確認 到不僅接地佈線115,藉由將接地佈線115與電源佈線116的配 線寬度/間隔比設為此適當範圍，便可獲得優越的焊接強度，可 防止電源部分的壓降。 再者，當電源佈線116與接地佈線115採用Cu鑲嵌佈線的 it況時，藉由設定為最大佈線寬度3μιη、佈線間隔丨μιη程度， 便可降低因Cu-CMP所發生的佈線侵蝕情況。依此便可更加提 升半導體裝置的可靠性。 另外，在本實施形態1中，層間絕緣膜1〇2雖採用氧化矽 馨膜，但是亦可取代氧化矽膜改為低介電率臈。此情況下，亦可 藉由層間絕緣膜102内所形成的插塞，獲得較高的焊接強度（後 述實施形態2亦同）。 再者，除二極體118與電容元件119之外，當將〗/〇埠中的 MI S電曰曰體形成保s蒦元件的情況時，亦可適用本發明。換句与 -說，可將MIS電晶體用電源佈線兼用為低介電率膜的補強構造。 實施形態2. 在上述的實施形態1中，乃針對焊接搭線組裝用半導體裝 置進行說明，而本發明的實施形態2則針對覆晶組裝用半導體 2118-6681A-PF 15 1315090 裝置進行說明。以下’便以與實施形態1之半導體裝置間的差 異點為中心進行說明。 第10圖所示係本實施形態2的半導體裝置說明剖面圖。 . 如第10圖所示，在二極體119與電容元件118上方的低介 電率膜1〇3内形成電源佈線116，並在鎖存防止用擴散層U7a 上方的低介電率膜103内形成接地佈線115。該等保護元件用電 源佈線116與接地佈線115係兼用為低介電率膜1〇3的補強構 造。在電源佈線116與接地佈線115上形成雙層氧化矽膜 • U4a，114b，在上層的氧化矽膜U4b上形成焊接墊112，在焊墊 112上形成保護膜1〇5，並在該保護膜1〇5内所形成的開口部Μ] 底部裸露出焊墊112。在開口部in内與保護膜1〇5上形成電極 200，在該電極200上形成當作覆晶元件2〇1用的凸塊。其他構 造均如同實施形態1。 組裝時所要求的機械強度係焊接搭線構造較覆晶構造嚴 格。所以，藉由將實施形態i中所說明的焊接搭線構造，改變 為本實施形態2所說明的覆晶構造，得知將可達本發明的效果。 故，本實施形態2將可獲得如同實施形態丨中所述的效果。 ®實施形態3. 本發明的實施形態3係針對將金屬電容器使用為保護元件 的情況進行說明。 第η圖所示係本實施形態3的半導體裝置說明剖面圖，第 12圖係第11圖所示半導體裝置的電源佈線平面圖。 M U圖解，電源佈、線116形成梳齒狀。該梳齒狀電源 佈線係構成金屬電容元件，如第7圖所示，並未輕接於在 較第1佈線1〇6更下層處所形成，如擴散層117b，m、娜電 晶體之類的保護元件。僅在接地佈線115下方的氧化石夕膜1〇2 2118-6681A-PF 16 1315090 内形成插塞120,透過該插塞120而耦接於接地佈線115與擴散 層117a。因為在電源佈線116下方的氧化矽膜1〇2内並未形成 插塞，因而不同於實施形態1，2，並無法將氧化矽膜1〇2取代為 低介電率膜。 在本實施形態3中，將構成金屬電容元件的電源佈線116 兼用為低介電率膜103的補強構造。而且，將透過插塞12〇而 耦接於鎖存對策用擴散層117a的接地佈線115，兼用為低介電 率膜103的補強構造。所以，如同實施形態i，將提昇焊接墊 φ I12下層所开》成低介電率膜103的機械強度，且可將槔之保 護元件的金屬電容元件116,有效的應用為低介電率膜103的補 強佈線。故，可縮小半導體晶片的面積，可降低半導體裝置的 製造成本。甚至藉由半導體晶片的小型化，便可達搭載著該晶 片的行動通信機器等電氣通信裝置之小型化。 Ha 再者，在本實施形態3中，亦是藉由將電源佈線116與接 地佈線115的佈線寬度/間隔比設為2以上’便可提升金屬搭線 斷裂試驗良率，可獲得具優越焊接強度的半導體裝置。 【圖式簡單說明】 _ 第1圖係本發明實施形態1中，保護元件的電路圖。 第2圖係說明本發明實施形態丨之半導體裝置的平面圖。 第3圖係第2圖所示半導體襞置的A_A，剖面圖。 第4圖係第2圖所示半導體裝置的B_B,剖面圖。 ' 第5圖（a)〜(c)係說明本發明實施形態1的半導體裝置之製 - 造方法的步驟剖面圖。 第6圖係本發明實施形態！ t，採用雙鑲散法形成網 線的步驟剖面圖。 第7圖（a)〜(b)係半導體裝置的焊接墊之配置平面圖。 2118-6681A-PF 17 1315090 第8圖係技術節點與焊接墊尺寸間之關係圖。 第9圖係本發明實施形態丨中，金屬搭線斷裂試驗良率的 電源配線寬度/間隔比依存性圖。 第10圖係說明本發明實施形態2之半導體裝置的剖面圖。 第u圖係說明本發明實施形態3之半導體裝置的剖面圖。 第12圖係第U圖所示半導體裝置的電源佈線平面圖。 第Π圖係具有低介電率膜的習知半導體裝置剖面圖。 第14圖係焊墊間距與焊墊尺寸的說明平面圖。 【主要元件符號說明】 10 保護元件 11 二極體 12 電容元件 13 電源佈線 14 接地佈線 101 基板 102 層間絕緣膜（氧化碎膜） 103 低介電率膜 104a,104b 氧化矽膜 105 保護膜（氮化>5夕膜） 106 第1佈線 107 第2佈線 108 第3佈線 109 第4佈線 110 第5佈線 111 第6佈線 2118-6681A-PF 18 1315090
112 113 114 115 116 117a,117b 118 119 120 121 122 123 124 125 131,132 200 201 焊接墊（鋁佈線） 開口部 金屬搭線 接地佈線 電源佈線 P+擴散層 N+擴散層（二極體） 電容元件 插塞 元件隔離 閘極 第1介層窗 第2介層窗 第3介層窗 焊接墊 電極 覆晶元件
2118-6681A-PF 19

Claims (1)

1315090 十、申請專利範圍： 1·一種半導體裝置，包括： 電路元件，形成於基板上； 低介電率膜，形成於該基板上方； 網狀佈線，具有在該電路元件之形成範圍上方且該低介電 率膜内網狀形成之電源佈線與接地佈線的網狀佈線，且其電耦 接於該電路元件； 氧化矽膜，形成於該低介電率膜上；以及 焊接墊，形成於該電路元件之形成範圍上方且氧化矽膜上。 2·如申請專利範圍第1項之半導體裝置，其中，該電路元件 包括電容元件、二極體或電晶體之至少一個。 3.如申請專利範圍第1項之半導體裝置，其中，該電路元件 係電容元件。 4. 如申請專利範圍第1項之半導體裝置，其中，該電路元件 係二極體或電晶體。
5. 如申請專利範圍第1項之半導體裝置，其中，該接地佈線 包圍該電源佈線。 6.如申請專利範圍帛i項之半導體裝置，其中，該電源佈線 與該接地佈線的佈線寬度，係佈線間隔的2倍以上大小。 該焊接墊上 該焊接墊上 7. 如申請專利範圍第1項之半導體裝置，其中 具有被焊接的金屬搭線。 8. 如申請專利範圍第1項之半導體裝置，其中 形成有凸塊。 2118-6681A-PF 20
TW097149109A 2004-02-09 2004-12-09 Semiconductor device having bonding pad above low-k dielectric film and manufacturing method therefor TWI315090B (en)

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