JP2008532292A - フリップ・チップ・デバイスを形成するための構造および方法 - Google Patents
フリップ・チップ・デバイスを形成するための構造および方法 Download PDFInfo
- Publication number
- JP2008532292A JP2008532292A JP2007557202A JP2007557202A JP2008532292A JP 2008532292 A JP2008532292 A JP 2008532292A JP 2007557202 A JP2007557202 A JP 2007557202A JP 2007557202 A JP2007557202 A JP 2007557202A JP 2008532292 A JP2008532292 A JP 2008532292A
- Authority
- JP
- Japan
- Prior art keywords
- conductive
- forming
- pad
- bump
- base metal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
- H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/03—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/0502—Disposition
- H01L2224/05022—Disposition the internal layer being at least partially embedded in the surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05556—Shape in side view
- H01L2224/05558—Shape in side view conformal layer on a patterned surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0556—Disposition
- H01L2224/05571—Disposition the external layer being disposed in a recess of the surface
- H01L2224/05572—Disposition the external layer being disposed in a recess of the surface the external layer extending out of an opening
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/05624—Aluminium [Al] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/05647—Copper [Cu] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/1012—Auxiliary members for bump connectors, e.g. spacers
- H01L2224/10122—Auxiliary members for bump connectors, e.g. spacers being formed on the semiconductor or solid-state body to be connected
- H01L2224/10125—Reinforcing structures
- H01L2224/10126—Bump collar
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/119—Methods of manufacturing bump connectors involving a specific sequence of method steps
- H01L2224/11912—Methods of manufacturing bump connectors involving a specific sequence of method steps the bump being used as a mask for patterning other parts
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/1302—Disposition
- H01L2224/13022—Disposition the bump connector being at least partially embedded in the surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01014—Silicon [Si]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01022—Titanium [Ti]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01023—Vanadium [V]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01024—Chromium [Cr]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01028—Nickel [Ni]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01042—Molybdenum [Mo]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01073—Tantalum [Ta]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01074—Tungsten [W]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/0132—Binary Alloys
- H01L2924/01327—Intermediate phases, i.e. intermetallics compounds
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/049—Nitrides composed of metals from groups of the periodic table
- H01L2924/0494—4th Group
- H01L2924/04941—TiN
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/049—Nitrides composed of metals from groups of the periodic table
- H01L2924/0495—5th Group
- H01L2924/04953—TaN
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/049—Nitrides composed of metals from groups of the periodic table
- H01L2924/0504—14th Group
- H01L2924/05042—Si3N4
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/1904—Component type
- H01L2924/19043—Component type being a resistor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Wire Bonding (AREA)
Abstract
Description
フォトレジスト層が、図3のフォトレジスト構造部301を形成するために付着され、パターニングされる。UBM層300は、アルミニウム・パッド212をカプセル化するための側面212Aと上表面212Bとの上に延在するバンプ下地金属構造部300A(好ましくは円形)を形成するために、フォトレジスト構造部301に従ってパターニングされる。図4を参照されたい。ウェット・エッチングまたはドライ・エッチングのプロセスはどちらも、UBM層300をエッチングするために使用可能である。エッチング・プロセスは、UBM層300の個々の材料層を取り除くために適切なウェット・エッチングの化学的性質を使用することが好ましい。
Claims (20)
- はんだバンプを形成するための方法であって、
半導体基板の上表面内に第1の導電パッドを形成する工程と、
前記上表面の上に保護層を形成する工程と、
前記第1の導電パッドの上表面を露光するために前記保護層内に開口部を形成する工程と、
前記第1の導電パッドの前記上表面と接触して前記開口部を通して、前記保護層の近接領域に延在する第2の導電パッドを形成する工程と、
前記第2の導電パッドの露光表面上にバンプ下地金属構造部を形成する工程と、
前記バンプ下地金属構造部の上表面上に前記はんだバンプを形成する工程と、
を有する方法。 - 前記バンプ下地金属構造部を形成する前記工程が、前記バンプ下地構造部内の前記第2の導電パッドをカプセル化する工程をさらに含む、請求項1に記載の方法。
- 前記バンプ下地金属構造部を形成する前記工程が、前記第2の導電パッドの露光上表面と露光側面との上に前記バンプ下地金属構造部を形成する工程をさらに含む、請求項1に記載の方法。
- 前記第1の導電パッドを形成する前記工程が銅パッドを形成する工程を含む、請求項1に記載の方法。
- 前記第2の導電パッドを形成する前記工程がアルミニウム・パッドを形成する工程を含む、請求項1に記載の方法。
- 前記半導体基板が前記第1の導電パッドの下側に位置する相互接続構造部を含み、前記第1の導電パッドが前記相互接続構造部のうち少なくとも1つと導電的に連通している、請求項1に記載の方法。
- 前記はんだバンプが前記基板および集積回路パッケージ、電子部品組立てボードまたは受け基板内の導電領域間に電気的接続部を提供する、請求項1に記載の方法。
- 前記第1の導電パッドの材料が前記第2の導電パッドの材料とは異なる、請求項1に記載の方法。
- 半導体デバイスを形成するための方法であって、
基板の上表面に保護層と接合パッドとを有する集積回路を提供する工程であって、各接合パッドは前記保護層内の開口部を通して露光される、工程と、
前記接合パッドの前記上表面に接触して前記開口部を通して導電パッドを形成する工程であって、前記導電パッドは前記保護層に隣接した領域に延在する、工程と、
前記導電パッドの露光表面上にバンプ下地金属構造部を形成する工程と、
前記バンプ下地金属層の上表面上に前記はんだバンプを形成する工程と、
を含む方法。 - 前記接合パッドを形成する前記工程が銅接合パッドを形成する工程を含む、請求項9に記載の方法。
- 前記導電パッドを形成する前記工程がアルミニウム導電パッドを形成する工程を含む、請求項9に記載の方法。
- 前記バンプ下地金属構造部を形成する前記工程が前記導電パッドの露光上表面と、露光側面との上に前記バンプ下地金属構造部を形成する工程をさらに含む、請求項9に記載の方法。
- 前記はんだバンプが前記基板および集積回路パッケージ、電子部品組立てボードまたは受け基板内の導電領域間に電気的接続部を提供する、請求項9に記載の方法。
- 半導体基板と、
前記基板の上表面に配置される第1の導電領域と、
前記第1の導電領域の上側に位置し、前記第1の導電領域の一部分を露光するためにその中に規定される開口部を有する、保護層と、
前記開口部内にあり、前記第1の導電領域に接触する第2の導電領域と、
前記第2の導電領域の露光表面上に配置されるバンプ下地金属構造部と、
前記バンプ下地金属構造部の上側に位置するはんだバンプと、
を含むはんだバンプ構造部。 - 前記第1の導電構造部が集積回路用の接合パッドを含み、前記基板がドープされた半導体領域および相互接続構造部を含み、前記接合パッドが相互接続構造部と導電的に連通している、請求項14に記載のはんだバンプ構造部。
- 前記第2の導電領域が前記開口部の周辺に隣接した前記保護層の領域の上側に位置する、請求項14に記載のはんだバンプ構造部。
- 前記バンプ下地金属構造部が前記第2の導電領域の上表面と側面との上側に位置する、請求項14に記載のはんだバンプ構造部。
- 前記第1の導電領域の材料は銅を含み、前記第2の導電領域の材料はアルミニウムを含む、請求項14に記載のはんだバンプ構造部。
- 前記はんだバンプが光相互接続システム内の電気的相互接続を提供する、請求項14に記載のはんだバンプ構造部。
- パッケージをさらに有し、前記はんだバンプが前記基板内の導電領域と、前記パッケージの外側に配置される導電素子との間の電気的接続を提供する、請求項14に記載のはんだバンプ構造部。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US65581605P | 2005-02-24 | 2005-02-24 | |
PCT/US2006/006673 WO2006091856A1 (en) | 2005-02-24 | 2006-02-24 | Structure and method for fabricating flip chip devices |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2008532292A true JP2008532292A (ja) | 2008-08-14 |
JP2008532292A5 JP2008532292A5 (ja) | 2009-04-16 |
Family
ID=36370840
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2007557202A Pending JP2008532292A (ja) | 2005-02-24 | 2006-02-24 | フリップ・チップ・デバイスを形成するための構造および方法 |
Country Status (6)
Country | Link |
---|---|
US (1) | US7777333B2 (ja) |
JP (1) | JP2008532292A (ja) |
KR (1) | KR101266335B1 (ja) |
CN (1) | CN100593232C (ja) |
GB (1) | GB2438788B (ja) |
WO (1) | WO2006091856A1 (ja) |
Families Citing this family (21)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100886710B1 (ko) | 2007-07-27 | 2009-03-04 | 주식회사 하이닉스반도체 | 반도체 패키지 및 이의 제조 방법 |
TWI392070B (zh) * | 2008-05-05 | 2013-04-01 | Unimicron Technology Corp | 半導體元件暨嵌埋有半導體元件之封裝基板及其製法 |
JP5361264B2 (ja) | 2008-07-04 | 2013-12-04 | ローム株式会社 | 半導体装置 |
US7985671B2 (en) * | 2008-12-29 | 2011-07-26 | International Business Machines Corporation | Structures and methods for improving solder bump connections in semiconductor devices |
US8405211B2 (en) | 2009-05-08 | 2013-03-26 | Taiwan Semiconductor Manufacturing Company, Ltd. | Bump pad structure |
KR101167805B1 (ko) | 2011-04-25 | 2012-07-25 | 삼성전기주식회사 | 패키지 기판 및 이의 제조방법 |
US9905524B2 (en) * | 2011-07-29 | 2018-02-27 | Taiwan Semiconductor Manufacturing Company, Ltd. | Bump structures in semiconductor device and packaging assembly |
US8580672B2 (en) * | 2011-10-25 | 2013-11-12 | Globalfoundries Inc. | Methods of forming bump structures that include a protection layer |
KR101890711B1 (ko) * | 2012-05-03 | 2018-08-22 | 에스케이하이닉스 주식회사 | 범프 버퍼 스프링패드부를 포함하는 전자 소자의 패키지 및 제조 방법 |
CN102915986B (zh) | 2012-11-08 | 2015-04-01 | 南通富士通微电子股份有限公司 | 芯片封装结构 |
WO2014071815A1 (zh) * | 2012-11-08 | 2014-05-15 | 南通富士通微电子股份有限公司 | 半导体器件及其形成方法 |
WO2014071813A1 (zh) | 2012-11-08 | 2014-05-15 | 南通富士通微电子股份有限公司 | 半导体器件的封装件和封装方法 |
US9269682B2 (en) * | 2013-02-27 | 2016-02-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of forming bump structure |
TWI517328B (zh) | 2013-03-07 | 2016-01-11 | 矽品精密工業股份有限公司 | 半導體裝置 |
US20150279793A1 (en) * | 2014-03-27 | 2015-10-01 | Taiwan Semiconductor Manufacturing Company Ltd. | Semiconductor structure and manufacturing method thereof |
US10439720B2 (en) | 2017-05-19 | 2019-10-08 | Adolite Inc. | FPC-based optical interconnect module on glass interposer |
US10608158B2 (en) | 2017-09-29 | 2020-03-31 | International Business Machines Corporation | Two-component bump metallization |
US10727391B2 (en) | 2017-09-29 | 2020-07-28 | International Business Machines Corporation | Bump bonded cryogenic chip carrier |
US10535698B2 (en) * | 2017-11-28 | 2020-01-14 | Taiwan Semiconductor Manufacturing Co., Ltd. | Image sensor with pad structure |
CN108323009A (zh) * | 2018-01-11 | 2018-07-24 | 南昌黑鲨科技有限公司 | 器件结构及器件布局 |
US11018103B2 (en) * | 2019-09-19 | 2021-05-25 | Nanya Technology Corporation | Integrated circuit structure |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS49112570A (ja) * | 1973-02-23 | 1974-10-26 | ||
US20030216039A1 (en) * | 2002-05-17 | 2003-11-20 | Taiwan Semiconductor Manufacturing Company | Method for fabricating an under bump metallization structure |
JP2004055855A (ja) * | 2002-07-19 | 2004-02-19 | Toyoda Gosei Co Ltd | 通信装置 |
WO2004059708A2 (en) * | 2002-12-20 | 2004-07-15 | Agere Systems Inc. | Structure and method for bonding to copper interconnect structures |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6462426B1 (en) * | 2000-12-14 | 2002-10-08 | National Semiconductor Corporation | Barrier pad for wafer level chip scale packages |
KR100640576B1 (ko) * | 2000-12-26 | 2006-10-31 | 삼성전자주식회사 | 유비엠의 형성방법 및 그에 의해 형성된 반도체 소자 |
JP4656275B2 (ja) * | 2001-01-15 | 2011-03-23 | 日本電気株式会社 | 半導体装置の製造方法 |
US6426281B1 (en) * | 2001-01-16 | 2002-07-30 | Taiwan Semiconductor Manufacturing Company | Method to form bump in bumping technology |
DE10146353B4 (de) * | 2001-09-20 | 2007-08-16 | Advanced Micro Devices, Inc., Sunnyvale | Verfahren zur Herstellung einer Lötperle und Lötperlenstruktur |
US7470997B2 (en) * | 2003-07-23 | 2008-12-30 | Megica Corporation | Wirebond pad for semiconductor chip or wafer |
JP2008016514A (ja) * | 2006-07-03 | 2008-01-24 | Renesas Technology Corp | 半導体装置の製造方法および半導体装置 |
-
2006
- 2006-02-24 WO PCT/US2006/006673 patent/WO2006091856A1/en active Application Filing
- 2006-02-24 KR KR1020077019305A patent/KR101266335B1/ko active IP Right Grant
- 2006-02-24 GB GB0718502A patent/GB2438788B/en not_active Expired - Fee Related
- 2006-02-24 JP JP2007557202A patent/JP2008532292A/ja active Pending
- 2006-02-24 CN CN200680006014A patent/CN100593232C/zh active Active
- 2006-02-24 US US11/884,328 patent/US7777333B2/en active Active
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS49112570A (ja) * | 1973-02-23 | 1974-10-26 | ||
US20030216039A1 (en) * | 2002-05-17 | 2003-11-20 | Taiwan Semiconductor Manufacturing Company | Method for fabricating an under bump metallization structure |
JP2004055855A (ja) * | 2002-07-19 | 2004-02-19 | Toyoda Gosei Co Ltd | 通信装置 |
WO2004059708A2 (en) * | 2002-12-20 | 2004-07-15 | Agere Systems Inc. | Structure and method for bonding to copper interconnect structures |
Also Published As
Publication number | Publication date |
---|---|
US20090072393A1 (en) | 2009-03-19 |
GB0718502D0 (en) | 2007-10-31 |
US7777333B2 (en) | 2010-08-17 |
WO2006091856A1 (en) | 2006-08-31 |
CN100593232C (zh) | 2010-03-03 |
GB2438788B (en) | 2009-03-11 |
KR101266335B1 (ko) | 2013-05-24 |
GB2438788A (en) | 2007-12-05 |
KR20070104919A (ko) | 2007-10-29 |
CN101128926A (zh) | 2008-02-20 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
KR101266335B1 (ko) | 플립 칩 장치를 제조하기 위한 구조 및 방법 | |
TWI394218B (zh) | 積體電路封裝及其形成方法、晶圓級積體電路封裝結構 | |
KR100643065B1 (ko) | 솔더링 가능한 패드 및 와이어 본딩 가능한 패드를 구비하는 금속 재배치 층 | |
KR100709662B1 (ko) | 반도체 장치 및 그 제조 방법 | |
JP4775007B2 (ja) | 半導体装置及びその製造方法 | |
US20070085219A1 (en) | Method for manufacture of wafer level package with air pads | |
JP2012054588A (ja) | 銅技術相互接続構造を使用する集積回路デバイス用のアルミニウム・パッド電力バスおよび信号ルーティング技術 | |
JP2007157844A (ja) | 半導体装置、および半導体装置の製造方法 | |
JP4401089B2 (ja) | 集積回路及びその製造方法 | |
JP4844392B2 (ja) | 半導体装置及び配線基板 | |
US20080142945A1 (en) | Semiconductor package with redistribution layer of semiconductor chip directly contacted with substrate and method of fabricating the same | |
US6908845B2 (en) | Integrated circuit die and an electronic assembly having a three-dimensional interconnection scheme | |
KR100826989B1 (ko) | 반도체 패키지 및 그의 제조방법 | |
US20040089946A1 (en) | Chip size semiconductor package structure | |
JPH0338043A (ja) | 半導体集積回路装置 | |
TWI607539B (zh) | 晶片封裝體及其製造方法 | |
EP1544913A2 (en) | Semiconductor device and method of manufacturing thereof | |
US9761555B2 (en) | Passive component structure and manufacturing method thereof | |
US9431370B2 (en) | Compliant dielectric layer for semiconductor device | |
US8878356B2 (en) | Package structure having micro-electro-mechanical system element and method of fabrication the same | |
KR20090106913A (ko) | 반도체 장치 및 그 제조 방법 | |
KR100848741B1 (ko) | 반도체 장치 및 그 제조 방법 | |
US11676920B2 (en) | Semiconductor device and method for fabricating the same | |
US20220238351A1 (en) | Substrate structure, and fabrication and packaging methods thereof | |
CN116435276A (zh) | 半导体封装结构及其制作方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20090223 |
|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20090223 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20110422 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20110427 |
|
A601 | Written request for extension of time |
Free format text: JAPANESE INTERMEDIATE CODE: A601 Effective date: 20110727 |
|
A602 | Written permission of extension of time |
Free format text: JAPANESE INTERMEDIATE CODE: A602 Effective date: 20110803 |
|
A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20111027 |
|
A02 | Decision of refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A02 Effective date: 20120611 |
|
A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20121011 |
|
A911 | Transfer to examiner for re-examination before appeal (zenchi) |
Free format text: JAPANESE INTERMEDIATE CODE: A911 Effective date: 20121128 |
|
A912 | Re-examination (zenchi) completed and case transferred to appeal board |
Free format text: JAPANESE INTERMEDIATE CODE: A912 Effective date: 20121214 |
|
A601 | Written request for extension of time |
Free format text: JAPANESE INTERMEDIATE CODE: A601 Effective date: 20130426 |
|
A602 | Written permission of extension of time |
Free format text: JAPANESE INTERMEDIATE CODE: A602 Effective date: 20130502 |
|
A601 | Written request for extension of time |
Free format text: JAPANESE INTERMEDIATE CODE: A601 Effective date: 20131120 |
|
A602 | Written permission of extension of time |
Free format text: JAPANESE INTERMEDIATE CODE: A602 Effective date: 20131125 |
|
A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20140219 |
|
RD03 | Notification of appointment of power of attorney |
Free format text: JAPANESE INTERMEDIATE CODE: A7423 Effective date: 20140729 |
|
RD04 | Notification of resignation of power of attorney |
Free format text: JAPANESE INTERMEDIATE CODE: A7424 Effective date: 20140805 |