SG140538A1 - Method for plasma etching performance enhancement - Google Patents

Method for plasma etching performance enhancement

Info

Publication number
SG140538A1
SG140538A1 SG200705771-4A SG2007057714A SG140538A1 SG 140538 A1 SG140538 A1 SG 140538A1 SG 2007057714 A SG2007057714 A SG 2007057714A SG 140538 A1 SG140538 A1 SG 140538A1
Authority
SG
Singapore
Prior art keywords
plasma etching
performance enhancement
etching performance
mask
features
Prior art date
Application number
SG200705771-4A
Other languages
English (en)
Inventor
Bing Ji
Erik A Edelberg
Takumi Yanagawa
Zhisong Huang
Lumin Li
Original Assignee
Lam Res Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US11/508,725 external-priority patent/US7977390B2/en
Application filed by Lam Res Corp filed Critical Lam Res Corp
Publication of SG140538A1 publication Critical patent/SG140538A1/en

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/73—Etching of wafers, substrates or parts of devices using masks for insulating materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P76/00—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography
    • H10P76/40—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials
    • H10P76/408—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials characterised by their sizes, orientations, dispositions, behaviours or shapes
    • H10P76/4085—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials characterised by their sizes, orientations, dispositions, behaviours or shapes characterised by the processes involved to create the masks

Landscapes

  • Drying Of Semiconductors (AREA)
SG200705771-4A 2006-08-22 2007-08-07 Method for plasma etching performance enhancement SG140538A1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US11/508,725 US7977390B2 (en) 2002-10-11 2006-08-22 Method for plasma etching performance enhancement

Publications (1)

Publication Number Publication Date
SG140538A1 true SG140538A1 (en) 2008-03-28

Family

ID=39129128

Family Applications (1)

Application Number Title Priority Date Filing Date
SG200705771-4A SG140538A1 (en) 2006-08-22 2007-08-07 Method for plasma etching performance enhancement

Country Status (6)

Country Link
JP (1) JP5085997B2 (https=)
KR (1) KR101468213B1 (https=)
CN (1) CN101131927A (https=)
MY (1) MY148830A (https=)
SG (1) SG140538A1 (https=)
TW (1) TWI453814B (https=)

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JP5662079B2 (ja) * 2010-02-24 2015-01-28 東京エレクトロン株式会社 エッチング処理方法
US9373521B2 (en) 2010-02-24 2016-06-21 Tokyo Electron Limited Etching processing method
US8574447B2 (en) * 2010-03-31 2013-11-05 Lam Research Corporation Inorganic rapid alternating process for silicon etch
JP6001940B2 (ja) * 2012-07-11 2016-10-05 東京エレクトロン株式会社 パターン形成方法及び基板処理システム
US20140051256A1 (en) * 2012-08-15 2014-02-20 Lam Research Corporation Etch with mixed mode pulsing
JP2014225501A (ja) 2013-05-15 2014-12-04 東京エレクトロン株式会社 プラズマエッチング方法及びプラズマエッチング装置
CN104616956B (zh) * 2013-11-05 2017-02-08 北京北方微电子基地设备工艺研究中心有限责任公司 等离子体刻蚀设备及方法
JP6331452B2 (ja) * 2014-02-19 2018-05-30 愛知製鋼株式会社 有機膜のエッチング方法
JP6549765B2 (ja) * 2014-06-16 2019-07-24 東京エレクトロン株式会社 処理方法
JP6373150B2 (ja) 2014-06-16 2018-08-15 東京エレクトロン株式会社 基板処理システム及び基板処理方法
CN105336665B (zh) * 2014-06-19 2019-01-29 中芯国际集成电路制造(上海)有限公司 基于超低k电介质的互连结构的制造方法及制造的产品
JP2017098478A (ja) 2015-11-27 2017-06-01 東京エレクトロン株式会社 エッチング方法
US20170178899A1 (en) * 2015-12-18 2017-06-22 Lam Research Corporation Directional deposition on patterned structures
JP6584339B2 (ja) * 2016-02-10 2019-10-02 Ｓｐｐテクノロジーズ株式会社 半導体素子の製造方法
JP6784530B2 (ja) * 2016-03-29 2020-11-11 東京エレクトロン株式会社 被処理体を処理する方法
WO2017170411A1 (ja) 2016-03-29 2017-10-05 東京エレクトロン株式会社 被処理体を処理する方法
JP6770848B2 (ja) 2016-03-29 2020-10-21 東京エレクトロン株式会社 被処理体を処理する方法
KR102362462B1 (ko) 2016-03-29 2022-02-14 도쿄엘렉트론가부시키가이샤 피처리체를 처리하는 방법
US10658194B2 (en) * 2016-08-23 2020-05-19 Lam Research Corporation Silicon-based deposition for semiconductor processing
CN106856163A (zh) * 2016-11-22 2017-06-16 上海华力微电子有限公司 一种高深宽比图形结构的形成方法
KR102312245B1 (ko) * 2016-12-02 2021-10-13 에이에스엠엘 네델란즈 비.브이. 에치 파라미터를 변화시키는 방법
JP6415636B2 (ja) * 2017-05-25 2018-10-31 東京エレクトロン株式会社 プラズマエッチング方法及びプラズマエッチング装置
JP7037384B2 (ja) * 2018-02-19 2022-03-16 キオクシア株式会社 半導体装置の製造方法
JP2020064924A (ja) * 2018-10-16 2020-04-23 東京エレクトロン株式会社 窒化膜の成膜方法および半導体装置の製造方法
US11640909B2 (en) * 2018-12-14 2023-05-02 Applied Materials, Inc. Techniques and apparatus for unidirectional hole elongation using angled ion beams
JP7174634B2 (ja) * 2019-01-18 2022-11-17 東京エレクトロン株式会社 膜をエッチングする方法
US10886136B2 (en) * 2019-01-31 2021-01-05 Tokyo Electron Limited Method for processing substrates
WO2020121540A1 (ja) * 2019-02-04 2020-06-18 株式会社日立ハイテク プラズマ処理方法及びプラズマ処理装置
JP7235864B2 (ja) * 2019-02-11 2023-03-08 長江存儲科技有限責任公司 保護層のｉｎ－ｓｉｔｕ形成を伴う新規のエッチング処理
KR102904323B1 (ko) 2019-02-27 2025-12-24 램 리써치 코포레이션 희생 층을 사용한 반도체 마스크 재성형
JP7422557B2 (ja) * 2019-02-28 2024-01-26 東京エレクトロン株式会社 基板処理方法および基板処理装置
JP7339032B2 (ja) * 2019-06-28 2023-09-05 東京エレクトロン株式会社 基板処理方法および基板処理装置
US11043394B1 (en) 2019-12-18 2021-06-22 Applied Materials, Inc. Techniques and apparatus for selective shaping of mask features using angled beams
JP7390199B2 (ja) * 2020-01-29 2023-12-01 東京エレクトロン株式会社 エッチング方法、基板処理装置、及び基板処理システム
CN115244664A (zh) 2020-02-28 2022-10-25 朗姆研究公司 用于减少euv图案化缺陷的多层硬掩模
JP7577012B2 (ja) 2021-03-26 2024-11-01 東京エレクトロン株式会社 基板処理方法及び基板処理装置
JP7320554B2 (ja) * 2021-04-27 2023-08-03 株式会社アルバック エッチング方法
WO2023166613A1 (ja) * 2022-03-02 2023-09-07 株式会社日立ハイテク プラズマ処理方法
TW202431406A (zh) 2022-09-22 2024-08-01 日商東京威力科創股份有限公司 基板處理方法及基板處理裝置
CN115513051B (zh) * 2022-11-04 2023-02-10 合肥晶合集成电路股份有限公司 硬掩模层返工方法及dmos形成方法

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US7169701B2 (en) * 2004-06-30 2007-01-30 Taiwan Semiconductor Manufacturing Co., Ltd. Dual damascene trench formation to avoid low-K dielectric damage
TWI255502B (en) * 2005-01-19 2006-05-21 Promos Technologies Inc Method for preparing structure with high aspect ratio

Also Published As

Publication number Publication date
TW200818313A (en) 2008-04-16
TWI453814B (zh) 2014-09-21
JP5085997B2 (ja) 2012-11-28
KR20080018110A (ko) 2008-02-27
JP2008060566A (ja) 2008-03-13
CN101131927A (zh) 2008-02-27
KR101468213B1 (ko) 2014-12-03
MY148830A (en) 2013-06-14

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