RU2014145179A - Физический уровень высокопроизводительного межсоединения - Google Patents

Физический уровень высокопроизводительного межсоединения Download PDF

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RU2014145179A
RU2014145179A RU2014145179A RU2014145179A RU2014145179A RU 2014145179 A RU2014145179 A RU 2014145179A RU 2014145179 A RU2014145179 A RU 2014145179A RU 2014145179 A RU2014145179 A RU 2014145179A RU 2014145179 A RU2014145179 A RU 2014145179A
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Венкатраман АЙЕР
Дэррен С. ДЖУ
Джефф УИЛЛИ
Роберт Дж. БЛЭНКЕНШИП
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Интел Корпорейшн
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Abstract

1. Устройство, содержащеелогическую схему интерфейса, предназначенную для того, чтобы дифференцированно передавать сигналы по нескольким путям передачи данных,логическую схему интерфейса, предназначенную для передачи нескольких флитов, причем несколько флитов содержат несколько полубайтов;и при этом логическая схема интерфейса для передачи нескольких флитов, содержит логическую схему интерфейса для передачичистой границы флита, по меньшей мере, с участком начальных полубайтов от первого флита из множества флитов по нескольким путям передачи данных в первом единичном интервале (UI); иперекрытие полубайтов, по меньшей мере, от двух флитов из множества флитов по нескольким путям передачи данных во время следующего UI.2. Устройство по п. 1, в котором множество флитов содержит, по меньшей мере, пять флитов, которые необходимо передать за 48 UI до того, как надо будет передать следующую чистую границу флита.3. Устройство по п. 1, в котором флит содержит 192 бита, а полубайт содержит 4 бита.4. Устройство по п. 3, в котором биты каждого флита необходимо передавать по порядку, начиная с бита 4n+3.5. Устройство по п. 1, в котором несколько путей передачи данных содержат 8 путей или 20 путей.6. Устройство по п. 1, в котором логическая схема интерфейса содержит логику физического уровня, логику канального уровня и логику уровня протокола.7. Устройство по п. 6, в котором логика уровня протокола предназначена для того, чтобы поддерживать транзакции с когерентным кэшем.8. Устройство по п. 1, в котором логическая схема интерфейса входит в процессор, подсоединенный в одно гнездо сервера, имеющего, по меньшей мере, два гнезда.9. Устройство по п. 1, в котором логическая схема интерфейса входит в систему на к

Claims (20)

1. Устройство, содержащее
логическую схему интерфейса, предназначенную для того, чтобы дифференцированно передавать сигналы по нескольким путям передачи данных,
логическую схему интерфейса, предназначенную для передачи нескольких флитов, причем несколько флитов содержат несколько полубайтов;
и при этом логическая схема интерфейса для передачи нескольких флитов, содержит логическую схему интерфейса для передачи
чистой границы флита, по меньшей мере, с участком начальных полубайтов от первого флита из множества флитов по нескольким путям передачи данных в первом единичном интервале (UI); и
перекрытие полубайтов, по меньшей мере, от двух флитов из множества флитов по нескольким путям передачи данных во время следующего UI.
2. Устройство по п. 1, в котором множество флитов содержит, по меньшей мере, пять флитов, которые необходимо передать за 48 UI до того, как надо будет передать следующую чистую границу флита.
3. Устройство по п. 1, в котором флит содержит 192 бита, а полубайт содержит 4 бита.
4. Устройство по п. 3, в котором биты каждого флита необходимо передавать по порядку, начиная с бита 4n+3.
5. Устройство по п. 1, в котором несколько путей передачи данных содержат 8 путей или 20 путей.
6. Устройство по п. 1, в котором логическая схема интерфейса содержит логику физического уровня, логику канального уровня и логику уровня протокола.
7. Устройство по п. 6, в котором логика уровня протокола предназначена для того, чтобы поддерживать транзакции с когерентным кэшем.
8. Устройство по п. 1, в котором логическая схема интерфейса входит в процессор, подсоединенный в одно гнездо сервера, имеющего, по меньшей мере, два гнезда.
9. Устройство по п. 1, в котором логическая схема интерфейса входит в систему на кристалле (SoC).
10. Устройство по п. 9, в котором SoC подключена к нескольким другим SoC в микросервере.
11. Устройство по п. 9, дополнительно содержащее радио.
12. Устройство, содержащее
контроллер для сопряжения между, по меньшей мере, первым процессором для распознавания первого набора команд, и вторым процессором для распознавания второго набора команд, который отличается от первого набора команд, при этом контроллер содержит логическую схему интерфейса для подключения к последовательному дифференциальному межсоединению, содержащему несколько путей передачи данных, логическую схему интерфейса, предназначенную для передачи нескольких флитов, причем несколько флитов содержат несколько полубайтов; и причем передатчик, предназначенный для передачи нескольких флитов содержит: логическую схему интерфейса для передачи чистой границы флита с начальными полубайтами от первого флита из нескольких флитов по каждому из путей из нескольких путей передачи данных в первом единичном интервале (UI); и перекрытие полубайтов, по меньшей мере, от двух флитов из нескольких флитов по нескольким путям передачи данных во время следующего UI.
13. Устройство по п. 12, в котором каждый из нескольких флитов содержит 192 путей или 48 полубайтов.
14. Устройство по п. 12, в котором несколько путей передачи данных содержат 8 путей или 20 путей.
15. Устройство по п. 12, в котором первый и второй процессоры подключены к контроллеру.
16. Устройство по п. 15, в котором первый набор команд содержит набор команд Intel®.
17. Устройство, содержащее
логическую схему интерфейса, предназначенную для того, чтобы дифференцированно передавать сигналы по нескольким путям передачи данных,
логическую схему интерфейса, предназначенную для того, чтобы логически группировать данные в кванты информации, причем логическая схема интерфейса предназначена для передачи
по меньшей мере, части первого кванта информации из нескольких квантов информации по нескольким путям передачи информации в течение первого единичного интервала (UI); и
по меньшей мере, части первого кванта информации и второго кванта
информации из нескольких квантов информации по нескольким путям передачи данных во время следующего UI.
18. Устройство по п. 17, в котором, по меньшей мере, часть первого кванта информации из нескольких квантов информации по нескольким путям передачи данных следует передавать в течение, по меньшей мере, первых четырех единичных интервалов, и в котором, по меньшей мере, часть первого кванта информации и второго кванта информации из нескольких квантов информации следует передавать по нескольким путям передачи данных в течение следующих четырех последовательных UI.
19. Устройство по п. 17, в котором первый квант информации включает в себя 192 бита.
20. Устройство по п. 17, в котором логическая схема интерфейса содержит логику уровня протокола, предназначенную для того, чтобы поддерживать транзакции с когерентным кэшем.
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US11741030B2 (en) 2023-08-29
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US10909055B2 (en) 2021-02-02
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US20140112339A1 (en) 2014-04-24
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