WO2018099248A1 - 背板设备、信号互联方法及装置 - Google Patents

背板设备、信号互联方法及装置 Download PDF

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Publication number
WO2018099248A1
WO2018099248A1 PCT/CN2017/109728 CN2017109728W WO2018099248A1 WO 2018099248 A1 WO2018099248 A1 WO 2018099248A1 CN 2017109728 W CN2017109728 W CN 2017109728W WO 2018099248 A1 WO2018099248 A1 WO 2018099248A1
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Prior art keywords
signal
board
serial
backplane
parallel
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PCT/CN2017/109728
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English (en)
French (fr)
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华道君
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中兴通讯股份有限公司
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Publication of WO2018099248A1 publication Critical patent/WO2018099248A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/16—Constructional details or arrangements
    • G06F1/18—Packaging or power distribution
    • G06F1/183—Internal mounting support structures, e.g. for printed circuit boards, internal connecting means
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/16—Constructional details or arrangements
    • G06F1/18—Packaging or power distribution

Definitions

  • the present disclosure relates to the field of computer technology, such as a backplane device, a signal interconnection method, and a device.
  • Backplane structure. 1 is a schematic view of a single-sided interposer backplane structure in the related art of the present disclosure.
  • 2 is a schematic view showing a structure of a backplane in a double-sided pair of plug-in boards in the related art of the present disclosure.
  • 3 is a schematic diagram of a structure of a backplane in a double-sided orthogonal card in the related art of the present disclosure.
  • the related rack servers mainly adopt the form of front and rear ventilation and heat dissipation. No matter which type of structure is used, it is necessary to open holes for ventilation and heat dissipation.
  • the multi-channel server design in the related art, it generally consists of a backplane and a board.
  • the board includes a processor board, an IO board, a control board, a management board, and the like. There may be one or two or four processors on the processor board.
  • the control board has a unit such as a common clock.
  • On the management board there are PCH (Platform Controller Hub) chips and BMC (Baseboard Management Controller) chips.
  • the backplane is a key component for interconnecting the signal of each board. Multiple processor boards, multiple IO boards, one control board and two management boards are simultaneously inserted on the backplane to form a multi-way server. Between these boards, a large amount of signal needs to be interconnected through the backplane.
  • FIG. 4 is a schematic diagram of implementation of signal interconnection between a card and a backplane in the related art of the present disclosure.
  • the card 1' has a plurality of main chips and other circuits, and a backplane connector 3'.
  • the chip or other circuit requires a number of signal lines 2' interconnected with other boards to be directly connected to the backplane connector 3' of the board.
  • the flow of these signals can be from the chip or other circuit to the backplane connector, from the backplane connector to the chip or other circuitry, or between the chip or other circuitry and the backplane connector. flow.
  • processors in a multi-path server need to be connected according to a specific topology.
  • Some configuration pins of each processor in the topology have different configurations, such as a processor serial number identifier SOCKET_ID, a processor 0 configuration signal LEGACY_SKT, and the like.
  • SOCKET_ID a processor serial number identifier
  • LEGACY_SKT a processor 0 configuration signal
  • This implementation method can not flexibly change the slot configuration.
  • the embodiments of the present disclosure provide a backplane device, a signal interconnection method, and a device, to at least solve the problem that the connection device between the card and the backplane is excessive in the related art and affects heat dissipation of the backplane.
  • a backplane device including: a backboard; a card inserted in a card slot of the backboard; a backplane connector connected to the backplane and the board Between the cards, for signal interconnection between the backboard and the card; a signal conversion unit is connected between the connector and the card, and configured to receive the first card from the card Converting a parallel signal to a first serial signal, then transmitting the first serial signal to the backplane through the backplane connector; and/or converting a second serial signal from the backplane And being the second parallel signal, the second parallel signal is then sent to the board.
  • the signal conversion unit includes: a configuration register, which is provided to the baseboard management controller BMC for system configuration of the processor on the processor board.
  • the signal conversion unit is a complex programmable logic device CPLD chip.
  • the board comprises: a processor board, an input/output IO board, a control board, and a management board.
  • the backplane connector further includes: two serial communication lines connected between the signal conversion unit and the board, and configured to transmit an uplink signal and a downlink signal, respectively.
  • a signal interconnection method is provided, which is applied to a multi-path server backplane, including: converting a first parallel signal of a first board into a first serial signal; A serial signal is sent to the second board via the backplane connector.
  • the method further includes: receiving a second serial signal sent by the second board via the backplane connector; decoding the second serial signal to obtain a second parallel signal, and A second parallel signal is sent to the first board.
  • converting the first parallel signal of the first board into the first serial signal comprises: acquiring a first parallel signal in the board from the first board; and pressing the first parallel signal by default Serializing serialization to obtain serial data; calculating a cyclic redundancy check CRC check code for the serial data, and adding the CRC check code to the serial data to obtain overall data;
  • the first serial signal is obtained by appending a synchronization frame header to the frame.
  • decoding the second serial signal to obtain the second parallel signal comprises: detecting a synchronization frame header of the second serial signal; receiving serial data in the second serial signal; The row data calculates a CRC check code and compares it with a CRC check code attached to the second serial signal; when the comparison result is consistent, the serial data is decoded to obtain the second Parallel signal.
  • the first parallel signal comprises at least one of: a parallel signal obtained from a chip and/or a circuit pin of the first board, and a transmit configuration register from the first board The contents of the register obtained.
  • the second parallel signal comprises at least one of: a signal to be sent to a chip pin and/or a circuit pin of the first card, and a configuration pin configured to configure a processor signal.
  • the first board and the second board are disposed on the same backboard.
  • a signal interconnection apparatus which is applied to a multi-path server backplane, and includes: a first conversion module configured to convert a first parallel signal of the first board into the first string And a first transmitting module configured to send the first serial signal to the second board via the backplane connector.
  • the device further includes: a receiving module configured to receive a second serial signal sent by the second board via the backplane connector; and a second converting module configured to decode the second string The row signal obtains a second parallel signal and transmits the second parallel signal to the first board.
  • the first parallel signal comprises at least one of: a chip from the first board and/or Or the parallel signal obtained by the circuit pin, and the register contents obtained from the transmit configuration register of the first board.
  • the second parallel signal comprises at least one of: a signal to be sent to a chip pin and/or a circuit pin of the first card, and a configuration pin configured to configure a processor signal.
  • a computer readable storage medium storing computer executable instructions configured to perform the above method.
  • the backplane device of the present disclosure includes: a backboard; a card inserted in a card slot of the backboard; a backplane connector connected between the backplane and the card for the a signal interconnection between the backplane and the board; a signal conversion unit coupled between the connector and the board and configured to convert a first parallel signal from the board to a second serial Signaling, then transmitting the first serial signal to the backplane through the connector, and/or converting a second serial signal from the backplane to a second parallel signal, and then The two parallel signals are sent to the board, and the multi-channel parallel signals transmitted between the board and the back board are converted into serial signals by the signal conversion unit, thereby solving the connection device between the board and the back board in the related art.
  • FIG. 1 is a schematic diagram of a single-sided interposer backplane structure in the related art of the present disclosure
  • FIG. 2 is a schematic view showing a structure of a backplane in a double-sided pair insertion board in the related art of the present disclosure
  • FIG. 3 is a schematic view showing a structure of a backplane in a double-sided orthogonal card in the related art of the present disclosure
  • FIG. 4 is a schematic diagram of implementation of signal interconnection between a card and a backplane in the related art of the present disclosure
  • FIG. 5 is a structural diagram of a backplane device according to an embodiment of the present disclosure.
  • FIG. 6 is a flow chart of a method of signal interconnection in accordance with an embodiment of the present disclosure.
  • FIG. 7 is a structural block diagram of a signal interconnection device according to an embodiment of the present disclosure.
  • FIG. 8 is a schematic diagram of implementation of signal interconnection between a card and a backplane according to an embodiment of the present disclosure
  • FIG. 9 is a schematic diagram of a backplane serial signal frame format according to an embodiment of the present disclosure.
  • FIG. 10 is a schematic diagram of implementation of a backplane signal interconnection according to an embodiment of the present disclosure
  • FIG. 11 is a schematic diagram of a processor topology of an 8-way server 8-way configuration according to an embodiment of the present disclosure
  • FIG. 12 is a schematic diagram of a processor topology of an 8-way server dual 4-way configuration according to an embodiment of the present disclosure.
  • FIG. 5 is a structural diagram of a backplane device according to an embodiment of the present disclosure.
  • the device includes: a backplane 50; a card 52 inserted in the backplane.
  • the backplane connector 54 is connected between the backboard and the board for signal interconnection between the backboard and the board;
  • the signal conversion unit 56 is connected between the connector and the board, and configured Converting the first parallel signal from the card to a first serial signal, then transmitting the first serial signal to the backplane via a connector, and/or converting the second serial signal from the backplane into a Two parallel signals are then sent to the board.
  • the signal conversion unit converts the multiple parallel signals transmitted between the card and the backplane into serial signals, thereby solving the excessive connection device between the card and the backplane in the related art.
  • the problem of affecting the heat dissipation of the backplane reduces the number of signals from the board to the backplane, reduces the number of connectors, reduces the cost, increases the ventilation opening area of the backboard, improves the heat dissipation performance of the system, and realizes dynamic modification of the system configuration. .
  • the signal conversion unit includes: a configuration register configured to perform system configuration on the processor on the board.
  • the signal conversion unit is a complex programmable logic device CPLD chip.
  • the board of this embodiment includes: a processor board, an input/output 10 board, a control board, and a management board.
  • the backplane connector further includes: two serial communication lines connected between the signal conversion unit and the board for respectively transmitting the uplink signal and the downlink signal.
  • FIG. 6 is a flowchart of a signal interconnection method according to an embodiment of the present disclosure. As shown in FIG. 6, the method includes steps S602 and S604.
  • the first parallel signal of the first board is converted into the first serial signal.
  • the first serial signal is sent to the second board via the backplane connector.
  • the method further comprises steps S11 and S12.
  • the second serial signal is decoded to obtain a second parallel signal and sent to the first board.
  • converting the first parallel signal of the first board into the first serial signal specifically includes: acquiring a first parallel signal in the board from the first board; serially connecting the first parallel signal in a preset order And obtaining serial data; calculating a cyclic redundancy check CRC check code for the serial data, and adding a CRC check code to the serial data to obtain overall data; adding a synchronization frame header before the frame of the whole data The first serial signal is obtained.
  • decoding the second serial signal to obtain the second parallel signal specifically includes: detecting a synchronization frame header of the second serial signal; receiving serial data in the second serial signal; and calculating a CRC check code for the serial data And comparing with the CRC check code attached to the data frame; when the CRC check code is verified correctly, the serial data frame is decoded to obtain the second parallel signal.
  • the first parallel signal comprises: a parallel signal obtained from a pin of the first board, and/or a register content obtained from a transmit configuration register of the first board.
  • the second parallel signal comprises: a second parallel signal decoded from the second serial signal, and/or a decoded configuration signal.
  • the configuration signal is used to configure the processor configuration pins.
  • the first board and the second board are disposed on the same back board.
  • a signal interconnection device is also provided, which is used to implement the above-mentioned embodiments and optional embodiments, and has not been described again.
  • the term "module” can be a complex programmable logic device and/or a combination of dedicated chips and circuits that perform the predetermined functions.
  • the devices described in the following embodiments are implemented in complex programmable logic devices, implementations of other specialized chips and/or circuits are also possible and contemplated.
  • FIG. 7 is a structural block diagram of a signal interconnection apparatus according to an embodiment of the present disclosure, which is applied to a multi-path server backplane. As shown in FIG. 7, the apparatus includes:
  • the first conversion module 70 is configured to convert the first parallel signal of the first board into the first serial signal
  • the first sending module 72 is configured to send the first serial signal to the second board via the backplane connector.
  • the device further includes: a receiving module configured to receive a second serial signal sent by the second board via the backplane connector; and a second converting module configured to decode the second serial signal to obtain the second parallel signal And send the second serial signal to the first board.
  • a receiving module configured to receive a second serial signal sent by the second board via the backplane connector
  • a second converting module configured to decode the second serial signal to obtain the second parallel signal And send the second serial signal to the first board.
  • the first parallel signal comprises: a parallel signal obtained from a pin of the first board, and/or a register content obtained from a transmit configuration register of the first board.
  • the second parallel signal comprises at least one of: a signal to be sent to a chip pin and/or a circuit pin of the first card, and a configuration pin configured to configure a processor signal.
  • the configuration register content decoded by the second conversion module is used to configure a processor-specific configuration pin signal to implement dynamic configuration of the system form.
  • each of the foregoing modules may be implemented by a digital circuit, but is not limited thereto: a complex programmable logic device; or other dedicated chips and circuits.
  • This embodiment provides a method for interconnecting backplane signals of a multi-path server, which reduces the number of signals from the card to the backplane, reduces the amount of connectors used, and reduces the cost. At the same time, it can also reduce the area of the backplane PCB occupied by the connector and the signal trace, and can be used to increase the ventilation opening and improve the heat dissipation performance. Achieve flexible configuration of the system.
  • the functional unit converts a large number of signals that are interconnected in parallel to the backplane connector into a very small number of serial signals for transmission to the backplane.
  • CPLD Complex Programmable Logic Device
  • Chips or other circuits on the board require signals to be connected to the backplane, all connected to a single CPLD chip. These signals and configuration registers complete the conversion of parallel to serial signals within the CPLD chip.
  • the CPLD chip has a transmit signal connection to the backplane connector of the board to send the converted serial signal to another board to be interconnected.
  • the CPLD chip also has a receive signal connection to the backplane connector of the board to receive serial signals from other boards from the backplane.
  • the decoding of the serial signal is completed inside the CPLD to be converted into a corresponding parallel signal, and then sent to the signal pin corresponding to the chip or other circuit on the card.
  • On the backplane only two serial signal lines need to be connected between the two boards that originally used parallel signal interconnection.
  • the original CPLD on the board of the shared multi-way server reduces the number of signals from the board to the backboard, reduces the number of connectors, reduces the cost, and supports flexible configuration of the system on the basis of no cost increase.
  • the ventilation opening area of the backboard can be increased to improve the heat dissipation performance of the system.
  • FIG. 8 is a schematic diagram of implementation of signal interconnection between a card and a backplane according to an embodiment of the present disclosure.
  • the hardware structure of a card backplane signal interconnection implementation method of the multi-channel server backplane signal interconnection method provided by the present disclosure is shown in FIG. 8.
  • the board 11' includes: a plurality of main chips, other circuits, a backplane connector 13', a CPLD chip 14', interconnected parallel signal lines 12', CPLD between the main chip or other circuits and the CPLD.
  • the interconnected parallel signal line 12' may have a bidirectional type of transmitting, receiving, and transceiving.
  • the serial signal line 15' can have one transmission and one reception.
  • multiple sets of serial signal lines can be led out, each set being connected to a different board by a backplane.
  • the CPLD chip 14' that satisfies the number of pins is selected according to the number of parallel signal lines 12' on the board that need to be connected to the backplane.
  • the parallel signal line 12' is connected to the CPLD chip. Connect the serial signal line 15' from the CPLD to the backplane connector on the board.
  • the input parallel signal line 12' is converted, converted from a plurality of parallel signals into a transmission direction serial signal, and if there is a configuration register, the serial signal in the transmission direction is converted together.
  • the converted serial signal is output from the CPLD and transmitted through the interconnected serial signal line 15' between the CPLD and the backplane connector.
  • the receiving direction serial signal transmitted from the other board on the backplane is received by the CPLD through the serial signal line 15'.
  • the received serial signal is decoded inside the CPLD and restored into a parallel signal corresponding to the parallel signal line 12'. If there is a configuration register, it is decoded into a corresponding configuration signal (held in the parallel signal line 12'). And then sent to the corresponding chip or other circuit via CPLD.
  • the backplane signals of the two boards can be interconnected.
  • the CPLD acquires parallel signals in the board from the pins connected to the parallel signal line 12', and if there is a transmission configuration register, the contents of the registers are merged into the parallel signals.
  • the parallel signals are serialized in sequence to obtain serial data.
  • a CRC (Cyclic Redundancy Check) check code is calculated for the serial data, and is appended to the serial data.
  • FIG. 9 is a schematic diagram of a data frame format of a backplane serial signal according to an embodiment of the present disclosure, and the data frame format is as shown in FIG. 9.
  • the constructed data frame is sent to the transceiver module in the CPLD.
  • the transceiver module uses a state machine to control the transceiving process. After receiving the transmission direction data frame, it transmits it to the serial signal line 15'. The sending process loops.
  • the CPLD receives the serial signal from the serial signal line 15' in the receiving direction and sends it to the transceiver module.
  • the transceiver module starts receiving the serial data after detecting the synchronization frame header, and after receiving the data, the transceiver module calculates a CRC check code for the received serial data, and the CRC check code attached to the second serial signal. Make comparisons to ensure that the received serial data is complete and correct.
  • the CRC check error is incorrect, that is, the comparison result is inconsistent, the error frame count is correspondingly increased, and the error frame is No subsequent transmission. If the CRC check is correct, that is, the comparison result is the same, the serial data frame is sent to the decoding module.
  • the decoding module decodes the serial data frame and restores it to a fixed sequence of parallel signals. If there is configuration register data, revert to the configuration signal. Each bit of the parallel signal and the configuration signal (if any) is then sent to the corresponding parallel signal line 12'.
  • FIG. 10 is a schematic diagram of a backplane signal interconnection implementation according to an embodiment of the present disclosure. As shown in FIG. 10, the embodiment includes a processor board 11', a backplane 21' and a management board 31'. .
  • the processor board 11' includes: two processors (CPU), other circuits, a backplane connector 13', a CPLD chip 14', a CPU chip or other interconnected parallel signal line 12' between the CPLD (included for The signal line carrying the configuration signal), the interconnect serial signal line 15' between the CPLD and the backplane connector, and the receive configuration register 16' (connected to the configuration pin of the CPU) inside the CLPD.
  • the backboard 21' includes a processor board slot connector 23', a management board slot connector 24', and a backplane interconnect serial signal line 22'. There are other slot connectors that are omitted from the figure.
  • the management board 31' includes: a PCH chip, a BMC chip, other circuits, a backplane connector 33', a CPLD chip 34', an interconnected parallel signal line 32', a CPLD and a backplane connector between the PCH chip or other circuits and the CPLD. Between the serial signal line 36' connected to the processor board 11', the CPLD and the backplane connector are connected to the serial signal line 35' of the other processor board, the transmission configuration register 37' inside the CLPD.
  • the management board needs to be interconnected with a plurality of processing boards, wherein the parallel signal line 32' has a portion of the signal connected to the processor board 11' and a portion of the signal connected to the other processor board.
  • the two processors and other circuits have a large number of signals that need to be connected to the management board.
  • the transmission direction signals of these parallel signal lines 12' enter the CPLD chip 14' and are converted into serial signals, which are sent to the management board 31' via the serial signal lines 15'.
  • the management board CPLD chip 34' is reached via the backplane serial signal line 22' and the management board serial signal line 36'.
  • the serial signal is decoded in the CPLD chip 34' and transmitted to the received signal in the parallel signal line 32' which is required to be coupled to the processor board 11'.
  • the BMC writes the configuration information to the transmission configuration register, and the transmission signal connected to the processor board 11' in the parallel signal line 32' enters the CPLD chip 34' and is merged into the content of the transmission configuration register and converted into serial.
  • the signal is sent to the processor board 11' via the serial signal line 36'.
  • the CPLD chip 14' of the processing board 11' is passed through the backplane serial signal line 22' and the processor board serial signal line 15'.
  • the serial signal is decoded into the parallel signal and the configuration signal in the CPLD chip 14' and then transmitted to the received signal in the parallel signal line 12' and the CPU configuration pin signal.
  • the signal connected to the other processor board by the parallel signal line 32' can be processed into the CPLD chip 34' by the same method, that is, converted into a serial signal and then subjected to a serial signal.
  • Line 35' is sent to another processor board, completing the signal interconnection of management board 31' with another processor board.
  • FIG. 11 is a schematic diagram of a topology of an 8-way server 8-way configuration processor according to an embodiment of the present disclosure.
  • an 8-way server is taken as an example.
  • the management board configures the two CPUs on the processor board 1 as CPU0 and CPU1 in the 8-way topology by writing the configuration register, and configures the two CPUs on the processor board 2
  • For CPU2 and CPU3 in the 8-way topology configure the two CPUs on the processor board 3 as CPU4 and CPU5 in the 8-way topology, and configure the two CPUs on the processor board 4 as the CPU6 in the 8-way topology.
  • CPU7 The system works in an 8-way configuration.
  • FIG. 12 is a schematic diagram of a topology of an 8-way server dual 4-way configuration processor according to an embodiment of the present disclosure.
  • the management board modifies each CPU configuration pin by writing a configuration register. Signal, configure two CPUs on processor board 1 as CPU0 and CPU1 in the first 4-way topology, and configure two CPUs on processor board 2 as CPU2 and CPU3 in the first 4-way topology.
  • the two CPUs on the processor board 3 are configured as CPU0 and CPU1 in the second 4-way topology, and the two CPUs on the processor board 4 are configured as the CPU 2 and CPU3 in the second 4-way topology.
  • the CPU interconnect line shown by the dotted line in the topology is closed according to the configuration.
  • the system flexibly implements the dual 4-way configuration by the signal interconnection method of the present disclosure, and does not need to perform hardware operations, such as modifying the pull-down configuration, inserting and removing jumpers, or dialing the dial switch.
  • This embodiment further includes the following alternatives: the components for the serial-to-parallel conversion transceiver function are replaced by other special chips or circuits instead of using the CPLD; the replacement of the specific implementation of the serial-to-parallel conversion and transceiving functions in the CPLD; The data frame format of the serial signal transmitted on the line signal line is replaced; the single-ended signal of the serial signal line on the board and the backplane is replaced with a differential signal. These substitutions can be used in combination with the scheme of the above embodiments without contradiction.
  • the problem that the connection device between the board and the backboard is excessive and affects the heat dissipation of the backboard is solved, the number of signals of the board to the backboard is reduced, the number of connectors is reduced, and the number of connectors is reduced.
  • the cost can also increase the ventilation opening area of the backboard, improve the heat dissipation performance of the system, and realize the dynamic modification of the system configuration.

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Abstract

本文公布一种背板设备、信号互联方法及装置，背板设备包括：背板；板卡，插在所述背板的卡槽中；背板连接器，连接在所述背板与所述板卡之间，用于所述背板与所述板卡之间的信号互联；信号转换单元，连接在所述连接器与所述板卡之间，并配置成将来自所述板卡的并行信号转换为第一串行信号，然后通过所述连接器将所述第一串行信号发送至所述背板，和/或将来自所述背板的第二串行信号转换为第二并行信号，然后将所述第二并行信号发送给所述板卡。

Description

背板设备、信号互联方法及装置 技术领域
本公开涉及计算机技术领域，例如一种背板设备、信号互联方法及装置。
背景技术
在相关技术中的多路服务器背板系统设计中，有如下几种结构类型：单面插板背板结构、双面对插插板中置背板结构、以及双面正交插板中置背板结构。图1是本公开相关技术中的单面插板背板结构的示意图。图2是本公开的相关技术中的双面对插插板中置背板结构的示意图。图3是本公开相关技术中的双面正交插板中置背板结构的示意图。相关的机架服务器主要采用前后通风散热形式，不管是哪种结构类型，都需要在背板上开孔通风散热。
相关技术中的多路服务器设计中，一般由背板和板卡组成。板卡包括处理器板、IO板、控制板、管理板等。处理器板上可能有1个或2个或4个处理器。IO板上有PCIE(Peripheral Component Interface Express，总线和接口)设备及其他IO设备。控制板有公共时钟等单元。管理板上有PCH(Platform Controller Hub，平台控制桥接)芯片、BMC(Baseboard Management Controller，基板管理控制器)芯片。背板是实现各板卡信号互联的关键部件。多块处理器板，多块IO板，1块控制板以及2块管理板同时插在背板上组成多路服务器。在这些板卡之间，大量的信号需要通过背板进行互联。
通常，板卡上芯片或其他电路需要与其他板卡互联的信号都是直接连接到板卡上的背板连接器，以便于通过背板互联。具体地，图4是本公开相关技术中的板卡与背板之间信号互联的实现示意图。如图4所示，板卡1′上有若干主要芯片及其他电路，还有背板连接器3′。芯片或其他电路需要与其他板卡互联的若干信号线2′直接连接到板卡的背板连接器3′上。这些信号的流向可以是从芯片或其他电路到背板连接器的流动，可以是从背板连接器到芯片或其他电路的流动，也可以是在芯片或其他电路与背板连接器之间双向流动。
这些需要上背板的信号要使用大量的背板连接器，带来成本上升。同时背板连接器和大量的背板信号连线需要占用背板PCB(Printed circuit board，印制电路板)面积，减少了可用于开孔散热的面积，影响散热性能。
多路服务器中多个处理器需要按特定的拓扑连接，拓扑中每个处理器的一些配置管脚会有不同的配置，如处理器序号标识SOCKET_ID、处理器0配置信号LEGACY_SKT等。一般处理器板上将此类信号送到背板，在背板上不同槽位的处理器板对此类信号做不同的上下拉，帮助处理器进行配置。这种实现方法带来槽位配置无法灵活变动。
针对相关技术中存在的上述问题，目前尚未发现有效的解决方案。
发明内容
以下是对本文详细描述的主题的概述。本概述并非是为限制权利要求的保护范围。
本公开实施例提供了一种背板设备、信号互联方法及装置，以至少解决相关技术中板卡和背板之间的连接器件过多而影响背板散热的问题。
根据本公开的一个实施例，提供了一种背板设备，包括：背板；板卡，插在所述背板的卡槽中；背板连接器，连接在所述背板与所述板卡之间，用于所述背板与所述板卡之间的信号互联；信号转换单元，连接在所述连接器与所述板卡之间，并配置成将来自所述板卡的第一并行信号转换为第一串行信号，然后通过所述背板连接器将所述第一串行信号发送至所述背板；和/或将来自所述背板的第二串行信号转换为第二并行信号，然后将所述第二并行信号发送给所述板卡。
可选地，所述信号转换单元包括：配置寄存器，提供给基板管理控制器BMC对所述处理器板上的处理器进行系统配置。
可选地，所述信号转换单元为复杂可编程逻辑器件CPLD芯片。
可选地，所述板卡包括：处理器板、输入输出IO板、控制板、以及管理板。
可选地，所述背板连接器还包括：两条串行通信线，连接在所述信号转换单元和所述板卡之间，分别配置为传输上行信号和下行信号。
根据本公开的另一个实施例，提供了一种信号互联方法，应用在多路服务器背板上，包括：将第一板卡的第一并行信号转换为第一串行信号；将所述第一串行信号经由背板连接器发送至第二板卡。
可选地，所述方法还包括：接收所述第二板卡经由所述背板连接器发送的第二串行信号；解码所述第二串行信号得到第二并行信号，并将所述第二并行信号发送给所述第一板卡。
可选地，将第一板卡的第一并行信号转换为第一串行信号包括：从所述第一板卡获取板卡内的第一并行信号；将所述第一并行信号按预设顺序串行化得到串行数据；对所述串行数据计算循环冗余校验CRC校验码，并将所述CRC校验码附加所述串行数据之后得到整体数据；在所述整体数据的帧前附加上同步帧头得到所述第一串行信号。
可选地，解码所述第二串行信号得到第二并行信号包括：检测所述第二串行信号的同步帧头；接收所述第二串行信号内的串行数据；对所述串行数据计算CRC校验码，并与附加在所述第二串行信号中的CRC校验码进行比对；在比对结果一致时，对所述串行数据进行解码以得到所述第二并行信号。
可选地，所述第一并行信号包括以下至少之一：从所述第一板卡的芯片和/或电路管脚获取到的并行信号，和从所述第一板卡的发送配置寄存器内得到的寄存器内容。
可选地，所述第二并行信号包括以下至少之一：待发送到所述第一板卡的芯片管脚和/或电路管脚的信号，和用于配置处理器的配置管脚的配置信号。
可选地，所述第一板卡和所述第二板卡设置在同一个背板上。
根据本公开的又一个实施例，提供了一种信号互联装置，应用在多路服务器背板上，包括：第一转换模块，配置成将第一板卡的第一并行信号转换为第一串行信号；第一发送模块，配置成将所述第一串行信号经由背板连接器发送至第二板卡。
可选地，所述装置还包括：接收模块，配置成接收所述第二板卡经由所述背板连接器发送的第二串行信号；第二转换模块，配置成解码所述第二串行信号得到第二并行信号，并将所述第二并行信号发送给所述第一板卡。
可选地，所述第一并行信号包括以下至少之一：从所述第一板卡的芯片和/ 或电路管脚获取到的并行信号，和从所述第一板卡的发送配置寄存器内得到的寄存器内容。
可选地，所述第二并行信号包括以下至少之一：待发送到所述第一板卡的芯片管脚和/或电路管脚的信号，和用于配置处理器的配置管脚的配置信号。
根据本公开的一个实施例，提供了一种计算机可读存储介质，存储有计算机可执行指令，所述计算机可执行指令配置成执行上述方法。
通过本公开的背板设备，包括：背板；板卡，插在所述背板的卡槽中；背板连接器，连接在所述背板与所述板卡之间，用于所述背板与所述板卡之间的信号互联；信号转换单元，连接在所述连接器与所述板卡之间并配置成将来自所述板卡的第一并行信号转换为第二串行信号，然后通过所述连接器将所述第一串行信号发送至所述背板，和/或将来自所述背板的第二串行信号转换为第二并行信号，然后将所述第二并行信号发送给所述板卡，通过信号转换单元来将板卡和背板之间传输的多路并行信号转换为串行信号，解决了相关技术中板卡和背板之间的连接器件过多而影响背板散热的问题，减少板卡到背板的信号数量，减少连接器数量，降低成本，还可增加背板通风开孔面积，提升系统散热性能，同时实现了对系统配置的动态修改。
在阅读并理解了附图和详细描述后，可以明白其他方面。
附图概述
此处所说明的附图用来提供对本公开的进一步理解，构成本申请的一部分，本公开的示意性实施例及其说明用于解释本公开，并不构成对本公开的不当限定。
图1是本公开相关技术中的单面插板背板结构的示意图；
图2是本公开相关技术中的双面对插插板中置背板结构的示意图；
图3是本公开相关技术中的双面正交插板中置背板结构的示意图；
图4是本公开相关技术中的板卡与背板之间信号互联的实现示意图；
图5是根据本公开实施例的背板设备的结构图；
图6是根据本公开实施例的信号互联方法的流程图；
图7是根据本公开实施例的信号互联装置的结构框图；
图8是本公开实施例的一种板卡与背板之间信号互联的实现示意图；
图9是本公开实施例的一种背板串行信号帧格式的示意图；
图10是本公开实施例的一种具体实施例的背板信号互联的实现示意图；
图11是本公开实施例的一种8路服务器8路配置的处理器拓扑示意图；
图12是本公开实施例的一种8路服务器双4路配置的处理器拓扑示意图。
具体实施方式
下文中将参考附图并结合实施例来详细说明本公开。需要说明的是，本申请中的实施例及实施例中的特征可以相互组合。
需要说明的是，本公开的说明书和权利要求书及上述附图中的术语“第一”、“第二”等是用于区别类似的对象，而不必用于描述特定的顺序或先后次序。
实施例1
在本实施例中提供了一种背板设备，图5是根据本公开实施例的背板设备的结构图，如图5所示，包括：背板50；板卡52，插在背板的卡槽中；背板连接器54，连接在背板与板卡之间，用于背板与板卡之间的信号互联；信号转换单元56，连接在连接器与板卡之间，配置成将来自板卡的第一并行信号转换为第一串行信号，然后通过连接器将所述第一串行信号发送至背板，和/或将来自背板的第二串行信号转换为第二并行信号，然后将所述第二并行信号发送给板卡。
通过本实施例的背板设备，信号转换单元来将板卡和背板之间传输的多路并行信号转换为串行信号，解决了相关技术中板卡和背板之间的连接器件过多而影响背板散热的问题，减少板卡到背板的信号数量，减少连接器数量，降低成本，还可增加背板通风开孔面积，提升系统散热性能，同时实现了对系统配置的动态修改。
可选地，信号转换单元包括：配置寄存器，用于对板卡上的处理器进行系统配置。
可选地，信号转换单元为复杂可编程逻辑器件CPLD芯片。
本实施例的板卡包括：处理器板、输入输出1O板、控制板、管理板。
可选地，背板连接器还包括：两条串行通信线，连接在信号转换单元和板卡之间，分别用于传输上行信号和下行信号。
在本实施例中提供了一种信号互联方法，图6是根据本公开实施例的信号互联方法的流程图，如图6所示，该方法包括步骤S602和S604。
在S602中，将第一板卡的第一并行信号转换为第一串行信号。
在S604中，将第一串行信号经由背板连接器发送至第二板卡。
可选地，该方法还包括步骤S11和S12。
在S11中，接收第二板卡经由背板连接器发送的第二串行信号。
在S12中，解码第二串行信号得到第二并行信号并上送给第一板卡。
可选地，将第一板卡的第一并行信号转换为第一串行信号具体包括：从第一板卡获取板卡内的第一并行信号；将第一并行信号按预设顺序串行化得到串行数据；对该串行数据计算循环冗余校验CRC校验码，并将CRC校验码附加在该串行数据之后得到整体数据；在整体数据的帧前附加上同步帧头得到第一串行信号。
可选地，解码第二串行信号得到第二并行信号具体包括：检测第二串行信号的同步帧头；接收第二串行信号内的串行数据；对串行数据计算CRC校验码，并与数据帧附加的CRC校验码进行比对；在CRC校验码校验正确时，对串行数据帧进行解码以得到第二并行信号。
可选地，第一并行信号包括：从第一板卡的管脚获取到的并行信号，和/或，从第一板卡的发送配置寄存器内得到的寄存器内容。
可选地，所述第二并行信号包括：从第二串行信号解码出的第二并行信号，和/或，解码出的配置信号。配置信号用于配置处理器配置管脚。可选地，第一板卡和第二板卡设置在同一个背板上。
通过以上的实施方式的描述，本领域的技术人员可以清楚地了解到根据上述实施例的方法可借助复杂可编程逻辑器件来实现，当然也可以通过其他硬件，但很多情况下前者是典型的实施方式。
实施例2
在本实施例中还提供了一种信号互联装置，该装置用于实现上述实施例及可选实施方式，已经进行过说明的不再赘述。如以下所使用的，术语“模块”可以是实现预定功能的复杂可编程逻辑器件和/或专用芯片及电路的组合。尽管以下实施例所描述的装置以复杂可编程逻辑器件来实现，但是其他专用芯片和/或电路的实现也是可能并被构想的。
图7是根据本公开实施例的信号互联装置的结构框图，应用在多路服务器背板上，如图7所示，该装置包括：
第一转换模块70，配置成将第一板卡的第一并行信号转换为第一串行信号；
第一发送模块72，配置成将第一串行信号经由背板连接器发送至第二板卡。
可选地，该装置还包括：接收模块，配置成接收第二板卡经由背板连接器发送的第二串行信号；第二转换模块，配置成解码第二串行信号得到第二并行信号，并将第二串行信号发送给第一板卡。
可选地，第一并行信号包括：从第一板卡的管脚获取到的并行信号，和/或，从第一板卡的发送配置寄存器内得到的寄存器内容。
可选地，所述第二并行信号包括以下至少之一：待发送到所述第一板卡的芯片管脚和/或电路管脚的信号，和用于配置处理器的配置管脚的配置信号。第二转换模块解码得到的配置寄存器内容用于配置处理器特定的配置管脚信号，以实现系统形态的动态配置。
需要说明的是，上述各个模块是可以通过数字电路来实现的，但不限于此：复杂可编程逻辑器件；或者，其他专用芯片及电路。
实施例3
本实施例提供了一种多路服务器的背板信号互联方法，减少板卡到背板的信号数量，减少连接器使用量，降低成本。同时还可减少连接器与信号走线占用的背板PCB面积，可用于增加通风开孔，提升散热性能。实现系统的灵活配置。
实施例的技术方案如下：
在板卡上的芯片或其他电路与背板连接器之间加入一个信号串并转换收发 功能单元，将原本大量并行互联到背板连接器的信号变换为数量极少的串行信号，送上背板传输。
在板卡上有一片CPLD(Complex Programmable Logic Device，复杂可编程逻辑器件)芯片，可以实现信号串并转换收发的功能，同时CPLD内部实现配置寄存器，提供给BMC进行系统配置。实现串并转换收发功能的部件并不仅限于CPLD，还可以是其他专门的芯片或电路。
本实施例的多路服务器的背板信号互联方法具体说明如下：
板卡上芯片或其他电路需要连接到背板的信号，全部连接到一片CPLD芯片。这些信号以及配置寄存器在CPLD芯片内部完成并行信号到串行信号的转换。CPLD芯片具有到板卡的背板连接器的发送信号连线，以将转换后的串行信号发送到要互联的另一块板卡。CPLD芯片还具有到板卡的背板连接器的接收信号连线，以从背板接收其他板卡送过来的串行信号。在CPLD内部完成串行信号的解码，以转换为相应的并行信号，再送到板卡上芯片或其他电路对应的信号管脚。在背板上，两个原本使用并行信号互联的板卡之间只需要用2根串行信号线连接。
通过本公开实施例，共用多路服务器内板卡上原有的CPLD，在无成本增加的基础上，减少板卡到背板的信号数量，减少连接器数量，降低成本，支持系统的灵活配置。同时还可增加背板通风开孔面积，提升系统散热性能。
下面结合附图进行详细说明：
图8是本公开实施例的一种板卡与背板之间信号互联的实现示意图，本公开提供的多路服务器背板信号互联方法的一种板卡背板信号互联实现硬件构成如图8所示，在板卡11′上包括：多个主要芯片、其他电路、背板连接器13′、CPLD芯片14′、主要芯片或其他电路与CPLD之间的互联并行信号线12′、CPLD与背板连接器之间的互联串行信号线15′。其中互联并行信号线12′可以有发送、接收、收发双向类型。其中串行信号线15′可以有一根发送、一根接收。在需要与多块其他板卡互联的板卡上，可以引出多组串行信号线，每组分别通过背板连接到不同的其他板卡。
根据板卡上需要连接到背板的并行信号线12′数量，选择满足管脚数量要求的CPLD芯片14′。
将并行信号线12′连接到CPLD芯片。将串行信号线15′从CPLD连接到板卡上背板连接器。
在CPLD内部，将输入的并行信号线12′进行转换，从多个并行的信号转换为一个发送方向串行信号，如果有配置寄存器，一并转换合入发送方向串行信号。转换后的串行信号从CPLD输出，通过CPLD与背板连接器之间的互联串行信号线15′传送上背板。
同时，背板上从其它板卡传送过来的接收方向串行信号通过串行信号线15′被CPLD接收。接收到的串行信号在CPLD内部进行解码，还原成为与并行信号线12′一一对应的并行信号，如果有配置寄存器，一并解码为相应的配置信号(承载在并行信号线12′中)，再经CPLD送至对应的芯片或其他电路。
对端的板卡完成上述同样的收发过程，即可实现两块板卡的背板信号互联。
本实施例的CPLD内部的一种串并转换及收发功能的实现方法的流程描述如下。
发送方向：
CPLD从与并行信号线12′连接的管脚获取板卡内并行信号，如果有发送配置寄存器，将寄存器内容合并入并行信号。将并行信号按顺序串行化得到串行数据。再对该串行数据计算CRC(Cyclic Redundancy Check，循环冗余校验)校验码，附加在串行数据之后。再在串行数据前面附加上同步帧头，组成一个完整的串行数据帧。图9是本公开实施例的一种背板串行信号的数据帧格式示意图，数据帧格式如图9所示。
构建好的数据帧送到CPLD内的收发模块。收发模块使用一个状态机，控制收发过程，接收到发送方向数据帧后就将其发送到串行信号线15′上。发送过程循环进行。
接收方向：
CPLD从接收方向的串行信号线15′接收到串行信号后送入收发模块。收发模块检测到同步帧头后开始接收串行数据，收完数据后收发模块对接收到的串行数据计算CRC校验码，并与附加在所述第二串行信号中的CRC校验码进行比对，确保接收到的串行数据完整及正确。
如CRC校验错误，即比对结果不一致，则错帧计数相应增加，并且该错帧 不往后续传送。如CRC校验正确，即比对结果一致，则将串行数据帧送到解码模块。
解码模块对串行数据帧进行解码，将其还原为固定顺序的并行信号。如果有配置寄存器数据，还原为配置信号。再将并行信号及配置信号(如果有)每一bit送至相应的并行信号线12′。
图10是本公开实施例的一种具体实施例的背板信号互联实现示意图，如图10所示，该实施例中包括一块处理器板11′，一块背板21′和一块管理板31′。
处理器板11′包括：两个处理器(CPU)，其他电路，背板连接器13′、CPLD芯片14′、CPU芯片或其他电路与CPLD之间的互联并行信号线12′(包含用于承载配置信号的信号线)、CPLD与背板连接器之间的互联串行信号线15′、CLPD内部的接收配置寄存器16′(连接到CPU的配置管脚)。
背板21′包括：处理器板槽位连接器23′，管理板槽位连接器24′，背板互联串行信号线22′。还有其他槽位连接器在图中省略。
管理板31′包括：PCH芯片，BMC芯片，其他电路，背板连接器33′，CPLD芯片34′，PCH芯片或其他电路与CPLD之间的互联并行信号线32′、CPLD与背板连接器之间连接到处理器板11′的串行信号线36′，CPLD与背板连接器之间连接到另一块处理器板的串行信号线35′，CLPD内部的发送配置寄存器37′。管理板需要与多块处理板互联，其中并行信号线32′中有连接到处理器板11′的一部分信号，还有连接到另一块处理器板的部分信号。
处理器板11′上，两个处理器以及其他电路有大量的信号需要连接到管理板。这些并行信号线12′中发送方向信号进入CPLD芯片14′后转换为串行信号，经串行信号线15′送往管理板31′。经过背板串行信号线22′和管理板串行信号线36′，到达管理板CPLD芯片34′。串行信号在CPLD芯片34′内解码后传送给并行信号线32′中需要与处理器板11′连接的接收信号。
管理板31′上，BMC将配置信息写入发送配置寄存器，并行信号线32′中连接到处理器板11′的发送信号进入CPLD芯片34′后合并入发送配置寄存器的内容后转换为串行信号，经串行信号线36′送往处理器板11′。经过背板串行信号线22′和处理器板串行信号线15′，到达处理板11′的CPLD芯片14′。串行信号在CPLD芯片14′内解码还原为并行信号及配置信号后传送给并行信号线12′中的接收信号及CPU配置管脚信号。
特别的，在管理板31′上，并行信号线32′连接到另一块处理器板的信号，可以通过同样的方法，进入CPLD芯片34′进行处理，即转换为串行信号后经串行信号线35′送往另一块处理器板，完成管理板31′与另一块处理器板的信号互联。
下面结合图11、图12对本公开的动态配置作说明。
图11是本公开实施例的一种8路服务器8路配置处理器拓扑示意图，如图11所示，以8路服务器为例。系统中有4块相同的处理器板，每块处理器板上有2个CPU。根据处理器板插的槽位的不同，管理板通过写配置寄存器，将处理器板1上的两个CPU配置为8路拓扑中的CPU0、CPU1，将处理器板2上的两个CPU配置为8路拓扑中的CPU2、CPU3，将处理器板3上的两个CPU配置为8路拓扑中的CPU4、CPU5，将处理器板4上的两个CPU配置为8路拓扑中的CPU6、CPU7。系统工作在8路配置。
图12是本公开实施例的一种8路服务器双4路配置处理器拓扑示意图，如图12所示，系统需要配置为双4路时，管理板通过写配置寄存器，修改各CPU配置管脚信号，将处理器板1上的两个CPU配置为第一个4路拓扑中的CPU0、CPU1，将处理器板2上的两个CPU配置为第一个4路拓扑中的CPU2、CPU3，将处理器板3上的两个CPU配置为第二个4路拓扑中的CPU0、CPU1，将处理器板4上的两个CPU配置为第二个4路拓扑中的CPU2、CPU3。拓扑中虚线所示CPU互联线根据配置关闭。系统通过本公开的信号互联方法灵活地实现双4路配置，且不需要进行硬件上的操作，如修改上下拉配置、插拔跳线或拨动拨码开关等。
本实施例还包括如下替换方式：对于串并转换收发功能的部件采用其他专门的芯片或电路替换，而非使用CPLD；对于CPLD内的串并转换及收发功能的具体实现方式的替换；对于串行信号线上传送的串行信号的数据帧格式替换；对于板卡及背板上串行信号线的单端信号替换为差分信号。在不矛盾的情况下，这些替换可以与上述实施例的方案进行结合使用。
以上所述仅为本公开的优选实施例而已，并不用于限制本公开，对于本领域的技术人员来说，本公开可以有各种更改和变化。
工业实用性
在本公开的上述实施例中，解决了相关技术中板卡和背板之间的连接器件过多而影响背板散热的问题，减少板卡到背板的信号数量，减少连接器数量，降低成本，还可增加背板通风开孔面积，提升系统散热性能，同时实现了对系统配置的动态修改。

Claims (17)

  1. 一种背板设备，包括：
    背板；
    板卡，插在所述背板的卡槽中；
    背板连接器，连接在所述背板与所述板卡之间，用于所述背板与所述板卡之间的信号互联；
    信号转换单元，连接在所述背板连接器与所述板卡之间，并配置成将来自所述板卡的第一并行信号转换为第一串行信号，然后通过所述背板连接器将所述第一串行信号发送至所述背板；和/或将来自所述背板的第二串行信号转换为第二并行信号，然后将所述第二并行信号发送给所述板卡。
  2. 根据权利要求1所述的设备，其中，所述信号转换单元包括：配置寄存器，用于对所述板卡上的处理器进行系统配置。
  3. 根据权利要求1所述的设备，其中，所述信号转换单元为复杂可编程逻辑器件CPLD芯片。
  4. 根据权利要求1所述的设备，其中，所述板卡包括：处理器板、输入输出IO板、控制板、以及管理板。
  5. 根据权利要求1所述的设备，其中，所述背板连接器还包括：两条串行通信线，连接在所述信号转换单元和所述板卡之间，分别配置为传输上行信号和下行信号。
  6. 一种信号互联方法，应用在多路服务器背板上，包括：
    将第一板卡的第一并行信号转换为第一串行信号；
    将所述第一串行信号经由背板连接器发送至第二板卡。
  7. 根据权利要求6所述的方法，还包括：
    接收所述第二板卡经由所述背板连接器发送的第二串行信号；
    解码所述第二串行信号得到第二并行信号，并将所述第二并行信号发送给所述第一板卡。
  8. 根据权利要求6所述的方法，其中，将第一板卡的第一并行信号转换为第一串行信号包括：
    从所述第一板卡获取板卡内的第一并行信号；
    将所述第一并行信号按预设顺序串行化得到串行数据；
    对所述串行数据计算循环冗余校验CRC校验码，并将所述CRC校验码附加在所述串行数据之后得到整体数据；
    在所述整体数据的帧前附加上同步帧头得到所述第一串行信号。
  9. 根据权利要求7所述的方法，其中，解码所述第二串行信号得到第二并行信号包括：
    检测所述第二串行信号的同步帧头；
    接收所述第二串行信号内的串行数据；
    对所述串行数据计算循环冗余校验CRC校验码，并与附加在所述第二串行信号中的CRC校验码进行比对；
    在比对结果一致时，对所述串行数据进行解码以得到所述第二并行信号。
  10. 根据权利要求6所述的方法，其中，所述第一并行信号包括以下至少之一：从所述第一板卡的芯片管脚和/或电路管脚获取到的并行信号，和从所述第一板卡的发送配置寄存器内得到的寄存器内容。
  11. 根据权利要求6所述的方法，其中，所述第一板卡和所述第二板卡设置在同一个背板上。
  12. 根据权利要求7所述的方法，其中，所述第二并行信号包括以下至少之一：待发送到所述第一板卡的芯片管脚和/或电路管脚的信号，和用于配置处理器的配置管脚的配置信号。
  13. 一种信号互联装置，应用在多路服务器背板上，包括：
    第一转换模块，配置成将第一板卡的第一并行信号转换为第一串行信号；
    第一发送模块，配置成将所述第一串行信号经由背板连接器发送至第二板卡。
  14. 根据权利要求13所述的装置，还包括：
    接收模块，配置成接收所述第二板卡经由所述背板连接器发送的第二串行信号；
    第二转换模块，配置成解码所述第二串行信号得到第二并行信号，并将所述第二并行信号发送给所述第一板卡。
  15. 根据权利要求13所述的装置，其中，所述第一并行信号包括以下至少之一：从所述第一板卡的芯片和/或电路管脚获取到的并行信号，和从所述第一板卡的发送配置寄存器内得到的寄存器内容。
  16. 根据权利要求14所述的装置，其中，所述第二并行信号包括以下至少之一：待发送到所述第一板卡的芯片管脚和/或电路管脚的信号，和用于配置处理器的配置管脚的配置信号。
  17. 一种计算机可读存储介质，存储有计算机可执行指令，所述计算机可执行指令配置成执行权利要求6-12中任一项所述的方法。
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