KR980005662A - 반도체장치 제조방법 - Google Patents

반도체장치 제조방법 Download PDF

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Publication number
KR980005662A
KR980005662A KR1019970028199A KR19970028199A KR980005662A KR 980005662 A KR980005662 A KR 980005662A KR 1019970028199 A KR1019970028199 A KR 1019970028199A KR 19970028199 A KR19970028199 A KR 19970028199A KR 980005662 A KR980005662 A KR 980005662A
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South Korea
Prior art keywords
film
titanium
silicon substrate
sputtering method
titanium nitride
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KR1019970028199A
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English (en)
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KR100261611B1 (ko
Inventor
도시끼 신무라
Original Assignee
가네꼬 히사시
닛뽕덴끼 가부시끼가이샤
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Publication of KR980005662A publication Critical patent/KR980005662A/ko
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Publication of KR100261611B1 publication Critical patent/KR100261611B1/ko

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
    • H01L21/76855—After-treatment introducing at least one additional element into the layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H01L21/28518—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table the conductive layers comprising silicides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

접속구멍에 있어서 티타늄 실리사이드막과 질화 티타늄막을 사이에 두고 도전체막을 형성할 때, 배리어(barrier) 성 및 저항성을 확보하면서 배선의 가공성을 확보하고, 또한 이 배선과 확산층의 사이의 전기접속 특성의 저하를 회피할 수 있는 반도체장치의 제조방법을 제공한다.
접속구멍 (105) 을 형성한 후, 실리콘기판 (101) 을 350℃~450℃로 유지하여, 콜리메이터 스퍼터링법으로 티타늄막 (106) 을 형성하고, 실리콘기판 (101) 을 300~450℃ 로 유지하여 콜리메이터 스퍼링법을 이용한 반응성 스퍼터링법으로 질화 티타늄막 (107) 을 형성한다.

Description

반도체장치 제조방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제 1도는 본 발명의 일실시의 형태의 제조공정의 단면모식도.

Claims (3)

  1. 확산층을 포함하여 이루어진 반도체 소자가 형성된 실리콘기판 표면을 피복하는 절연막을 형성하고, 상기 반도체 소자에 설치하는 접속구멍을 상기 절연막에 형성하여, 상기 접속구멍의 저부에 노출된 상기 확산층 표면의 자연산화막을 제거하는 공정과, 상기 실리콘기판을 350℃ 부터 450℃ 범위의 온도로 가열하여, 상기 절연막 상면의 막두께가 제 1 의 소정 막두께 (=t1) 가 되도록, 콜리메이터 스퍼터링법으로 전면에 티타늄막을 형성하는 공정과, 상기 실리콘기판을 소요 온도로 가열하여, 상기 절연막 상면의 막두께가 제 2 의 소정 막두께 (=t2) 가 되도록, 콜리메이터 스퍼터링법으로 전면에 질화 티타늄막을 형성하는 공정과, 열처리에 의해, 상기 확산층에 도달하는 상기 접속부의 저부의 상기 티타늄막을 티타늄 실리사이드막으로 변환하는 공정과, 상기 질화 티타늄막을 피복하는 도전체막을 형성하고, 상기 도전체막, 상기 질화 티타늄막 및 상기 티타늄막을 패터닝하여 배선을 형성하는 공정을 가지는 것을 특징으로 하는 반도체장치의 제조방법.
  2. 제 1 항에 있어서, 상기 소요 온도는 300℃ 부터 450℃ 범위의 온도인 것을 특징으로 하는 반도체장치의 제조방법.
  3. 제 1 항 또는 제 2 항에 있어서, 상기 t1 이 9㎚ 보다 두껍고, 상기 t2 가 29㎚ 보다 두껍고, 또한 상기 t1 과 상기 t2 의 합이 300㎚ 보다 얇은 것을 특징으로 하는 반도체장치의 제조방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019970028199A 1996-06-27 1997-06-27 반도체장치 제조방법 KR100261611B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP8167382A JPH1012729A (ja) 1996-06-27 1996-06-27 半導体装置の製造方法
JP96-167382 1996-06-27

Publications (2)

Publication Number Publication Date
KR980005662A true KR980005662A (ko) 1998-03-30
KR100261611B1 KR100261611B1 (ko) 2000-09-01

Family

ID=15848681

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019970028199A KR100261611B1 (ko) 1996-06-27 1997-06-27 반도체장치 제조방법

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US (1) US5985756A (ko)
JP (1) JPH1012729A (ko)
KR (1) KR100261611B1 (ko)
GB (1) GB2314681B (ko)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6686288B1 (en) 1996-02-21 2004-02-03 Micron Technology, Inc. Integrated circuit having self-aligned CVD-tungsten/titanium contact plugs strapped with metal interconnect and method of manufacture
JP3221480B2 (ja) * 1997-08-22 2001-10-22 日本電気株式会社 半導体装置の製造方法
JP3221381B2 (ja) * 1997-11-21 2001-10-22 日本電気株式会社 半導体装置の製造方法
KR19990041688A (ko) * 1997-11-24 1999-06-15 김규현 티타늄 샐리사이드 형성 방법
JP3374901B2 (ja) * 1998-02-27 2003-02-10 日本電気株式会社 半導体装置
GB2357371B (en) * 1999-11-04 2004-02-11 Trikon Holdings Ltd A method of forming a barrier layer
US6688584B2 (en) * 2001-05-16 2004-02-10 Micron Technology, Inc. Compound structure for reduced contact resistance
US7329599B1 (en) * 2005-03-16 2008-02-12 Advanced Micro Devices, Inc. Method for fabricating a semiconductor device
JP2009295931A (ja) * 2008-06-09 2009-12-17 Renesas Technology Corp 半導体装置および半導体装置の製造方法
US9831183B2 (en) 2014-08-07 2017-11-28 Taiwan Semiconductor Manufacturing Company, Ltd. Contact structure and method of forming
JP6650719B2 (ja) * 2015-09-30 2020-02-19 キヤノン株式会社 撮像装置、撮像システムおよび半導体装置の製造方法
CN113223951B (zh) * 2020-01-21 2022-12-02 夏泰鑫半导体(青岛)有限公司 半导体处理工艺及半导体元器件

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5136362A (en) * 1990-11-27 1992-08-04 Grief Malcolm K Electrical contact with diffusion barrier
US5250467A (en) * 1991-03-29 1993-10-05 Applied Materials, Inc. Method for forming low resistance and low defect density tungsten contacts to silicon semiconductor wafer
JP2725944B2 (ja) * 1991-04-19 1998-03-11 インターナショナル・ビジネス・マシーンズ・コーポレイション 金属層堆積方法
JP2806757B2 (ja) * 1993-09-29 1998-09-30 日本電気株式会社 半導体装置の製造方法
JPH07201993A (ja) * 1993-12-28 1995-08-04 Mitsubishi Electric Corp 半導体装置およびその製造方法
JP2606143B2 (ja) * 1994-07-22 1997-04-30 日本電気株式会社 半導体装置及びその製造方法
JPH08107087A (ja) * 1994-10-06 1996-04-23 Mitsubishi Electric Corp 半導体装置及びその製造方法
JPH08176823A (ja) * 1994-12-26 1996-07-09 Sony Corp 高融点金属薄膜の成膜方法
US5654233A (en) * 1996-04-08 1997-08-05 Taiwan Semiconductor Manufacturing Company Ltd Step coverage enhancement process for sub half micron contact/via
US5801096A (en) * 1996-06-03 1998-09-01 Taiwan Semiconductor Manufacturing Company Ltd. Self-aligned tungsen etch back process to minimize seams in tungsten plugs

Also Published As

Publication number Publication date
KR100261611B1 (ko) 2000-09-01
GB2314681B (en) 2000-04-05
US5985756A (en) 1999-11-16
GB2314681A (en) 1998-01-07
JPH1012729A (ja) 1998-01-16
GB9713734D0 (en) 1997-09-03

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