KR960026882A - 집적 회로 및 그 제조방법 - Google Patents

집적 회로 및 그 제조방법 Download PDF

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KR960026882A
KR960026882A KR1019950061418A KR19950061418A KR960026882A KR 960026882 A KR960026882 A KR 960026882A KR 1019950061418 A KR1019950061418 A KR 1019950061418A KR 19950061418 A KR19950061418 A KR 19950061418A KR 960026882 A KR960026882 A KR 960026882A
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South Korea
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insulator
doped
patterned conductor
integrated circuit
forming
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KR1019950061418A
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KR100517389B1 (ko
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구오-후아 리
첸-후아 더글라스 유
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죤 티. 레흐버그
에이티 앤드 티 코포레이션
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H01L21/02129—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being boron or phosphorus doped silicon oxides, e.g. BPSG, BSG or PSG
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/314—Inorganic layers
    • H01L21/316—Inorganic layers composed of oxides or glassy oxides or oxide based glass
    • H01L21/31604—Deposition from a gas or vapour
    • H01L21/31625—Deposition of boron or phosphorus doped silicon oxide, e.g. BSG, PSG, BPSG
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B10/00—Static random access memory [SRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B10/00—Static random access memory [SRAM] devices
    • H10B10/15—Static random access memory [SRAM] devices comprising a resistor load element
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S257/00—Active solid-state devices, e.g. transistors, solid-state diodes
    • Y10S257/903—FET configuration adapted for use as static memory cell
    • Y10S257/904—FET configuration adapted for use as static memory cell with passive components,, e.g. polysilicon resistors

Abstract

SRAM셀의 제2폴리실리콘 레벨을 둘러싸는 인이 도핑된 글라스로 구성 인터레벨 절연체를 기재하는데, 그 제2폴리실리콘은 일반적으로 셀 로컬 상호 접속이다. 인이 도핑된 글라스 층은 도금층으로부터 효과적으로 소듐을 게터링한다. 다른 도핑된 게터링층이 회로의 보다 높은 레벨에서 이용될 수 있어도 인이 도핑된 글라스층은 이용될 수 있다.

Description

집적 화로 및 그 제조방법.
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본 발명의 실시예를 설명하는데 이용된 집적 회로의 횡단면도.

Claims (15)

  1. 집적 회로 제조방법에 있어서, 기판(11)상에 게이트(15)를 형성하는 단계; 상기 게이트(15)상에 제1절연층(17)을 형성하는 단계; 상기 제1절연체(17)상에 제1패턴된 전도체(19)를 형성하는 단계; 상기 패턴된 전도체(19)와 제1절연체(17)상에 제2도핑된 절연체(23)을 형성하는 단계; 소듐 이온을 유인하기 위해 제2도핑된 절연체(23)를 가열하는 단계; 제2도핑된 절연체(23)상에 제2패턴된 전도체(21)를 형성하는 단계와; 제3도핑된 절연체(25)가 소듐 이온을 게터링할 수 있도록, 상기 제2패턴된 전도체(21)위에 놓인 제2도핑된 절연체(25)를 형성하는 단계를 포함하는 것을 특징으로 하는 집적 회로 제조 방법.
  2. 제1항에 있어서, 상기 제2패턴된 전도체(21)와 상기 제3도핑된 절연체(25) 사이에 제4도핑 안된 절연체(27)가 형성되는 것을 특징으로 하는 집적 회로 제조 방법.
  3. 제1항에 있어서, 상기 제3도핑된 절연체(25)상에 제5도핑 안된 절연체(29)가 형성되는 것을 특징으로 하는 집적 회로 제조 방법.
  4. 제3항에 있어서, 상기 제5도핑 안된 절연체(29)상에 최소한 하나의 레벨의 금속화가 형성되는 것을 특징으로 하는 집적 회로 제조 방법.
  5. 제1항에 있어서, 상기 집적 회로는 SRAM을 포함하는 것을 특징으로 하는 집적 회로 제조 방법.
  6. 제1항에 있어서, 상기 제2도핑된 절연체(23)는 P-글라스 및 PE-PTEOS로 구성된 그룹으로부터 선택된 재료로 형성되는 것을 특징으로 하는 집적 회로 제조 방법.
  7. 제1항에 있어서, 상기 제2도핑된 절연체(23)는 800℃ 와 850℃ 사이의 온도로 가열되는 것을 특징으로 하는 집적 회로 제조 방법.
  8. 제1항에 있어서, 상기 게이트(15)와, 상기 제1패턴된 전도체(19) 및 제2패턴된 전도체(21)는 폴리실리콘으로 형성되는 것을 특징으로 하는 집적 회로 제조 방 법.
  9. 제8항에 있어서, 상기 전도체중 최소한 하나의 전도체는 도금실리사이드를 갖는 것을 특징으로 하는 집적 회로 제조 방법.
  10. 집적 회로에 있어서, 기판(11)상의 게이트(15); 상기 게이트(15) 및 상기 기판(11)상의 제1절연층(17); 상기 제1절연체(17)상의 제1패턴된 전도체(19); 상기 패턴된 전도체(19)와 제1절연체(17)상의 제2도핑된 절연층(23); 상기 제2도핑된 절연체(23)상에 있는 제2패턴된 전도체(21)와; 상기 제2패턴된 전도체(21)위에 놓인 제3도핑된 절연체(25)를 포함하는 것을 특징으로 하는 집적 회로.
  11. 제10항에 있어서, 상기 제2패턴된 전도체(21)와 상기 제3도핑된 절연체(25) 사이에 제4도핑 안된 절연체(27)를 더 포함하는 것을 특징으로 하는 집적 회로.
  12. 제10항에 있어서, 상기 제3도핑된 절연체(25)상에 제5도핑 안된 절연체(29)를 더 포함하는 것을 특징으로 하는 집적 회로.
  13. 제12항에 있어서, 상기 제5도핑 안된 절연체(29)상에 금속화의 최소한 하나의 레벨을 더 포함하는 것을 특징으로 하는 집적 회로.
  14. 제10항에 잇어서, 상기 집적 회로는 SRAM을 포함하는 것을 특징으로 하는 집적 회로.
  15. 제10항에 있어서, 상기 제2도핑된 절연체(23)는 P-글라스 및 PE-PTEOS로 구성된 그룹으로부터 선택된 재료로 형성된 것을 특징으로 하는 집적 회로.
    ※ 참고사항 : 최초출원 내용에 의하여 공개 하는 것임.
KR1019950061418A 1994-12-29 1995-12-28 집적회로및그제조방법 KR100517389B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US08/366,192 US5559052A (en) 1994-12-29 1994-12-29 Integrated circuit fabrication with interlevel dielectric
US366,192 1994-12-29

Publications (2)

Publication Number Publication Date
KR960026882A true KR960026882A (ko) 1996-07-22
KR100517389B1 KR100517389B1 (ko) 2006-05-10

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US (1) US5559052A (ko)
EP (1) EP0720222B1 (ko)
JP (2) JP3353051B2 (ko)
KR (1) KR100517389B1 (ko)
DE (1) DE69535056T2 (ko)
TW (1) TW344117B (ko)

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JPH06104268A (ja) * 1992-09-21 1994-04-15 Mitsubishi Electric Corp ゲッタリング効果を持たせた半導体基板およびその製造方法
US5605853A (en) * 1996-05-28 1997-02-25 Taiwan Semiconductor Manufacturing Company Ltd. Method of making a semiconductor device having 4 transistor SRAM and floating gate memory cells
US5990513A (en) * 1996-10-08 1999-11-23 Ramtron International Corporation Yield enhancement technique for integrated circuit processing to reduce effects of undesired dielectric moisture retention and subsequent hydrogen out-diffusion
US6242299B1 (en) 1999-04-01 2001-06-05 Ramtron International Corporation Barrier layer to protect a ferroelectric capacitor after contact has been made to the capacitor electrode
US8723654B2 (en) 2010-07-09 2014-05-13 Cypress Semiconductor Corporation Interrupt generation and acknowledgment for RFID
US9846664B2 (en) 2010-07-09 2017-12-19 Cypress Semiconductor Corporation RFID interface and interrupt
US9092582B2 (en) 2010-07-09 2015-07-28 Cypress Semiconductor Corporation Low power, low pin count interface for an RFID transponder
JP6267624B2 (ja) 2014-10-24 2018-01-24 住友電気工業株式会社 炭化珪素半導体装置

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Publication number Publication date
JP3353051B2 (ja) 2002-12-03
DE69535056D1 (de) 2006-07-27
DE69535056T2 (de) 2007-01-11
US5559052A (en) 1996-09-24
JP3009618B2 (ja) 2000-02-14
EP0720222B1 (en) 2006-06-14
JPH08236710A (ja) 1996-09-13
TW344117B (en) 1998-11-01
EP0720222A3 (en) 1997-11-12
EP0720222A2 (en) 1996-07-03
JPH08255817A (ja) 1996-10-01
KR100517389B1 (ko) 2006-05-10

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