KR900019239A - 집적회로용 로칼인터커넥트 - Google Patents

집적회로용 로칼인터커넥트 Download PDF

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Publication number
KR900019239A
KR900019239A KR1019900007526A KR900007526A KR900019239A KR 900019239 A KR900019239 A KR 900019239A KR 1019900007526 A KR1019900007526 A KR 1019900007526A KR 900007526 A KR900007526 A KR 900007526A KR 900019239 A KR900019239 A KR 900019239A
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South Korea
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gate
layer
protective cap
metal
integrated circuit
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KR1019900007526A
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English (en)
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후태 리오우
이셩 린
후센 E. 첸
Original Assignee
다니엘 퀘이삭
에스지에스 톰슨 마이크로일렉트로닉스 인코포레이티드
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Publication of KR900019239A publication Critical patent/KR900019239A/ko

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H01L21/28518—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table the conductive layers comprising silicides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3215—Doping the layers
    • H01L21/32155—Doping polycristalline - or amorphous silicon layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53271—Conductive materials containing semiconductor material, e.g. polysilicon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/015—Capping layer
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/019—Contacts of silicides
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/02—Contacts, special

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Semiconductor Memories (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

내용 없음

Description

집적회로용 로칼인터커넥트
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1-4도는 본 발명에 따른 반도체 집적회로 제조공정의 단계를 설명한다.

Claims (13)

  1. 게이트 산화물층에 게이트 다결정 실리콘층을 형성하고, 게이트 다결정 실리콘층에 금속을 포함하는 제1도전층을 형성하고, 금속을 포함하는 제1도전층에 보호캡층을 형성하고 : 게이트산화물, 게이트 다결정실리콘, 금속을 포함하는 제1도전층과 보호캡층을 패터닝하여 활성영역에 게이트를 형성하고, 게이트에 측벽 절연영역을 형성하고, 집적회로에 금속을 포함하는 제2도전층을 하고 : 그리고 금속을 포함하는 제2도전층을 패터닝하여 로칼인터커넥트를 형성하고, 여기에서 보호캡층이 그러한 패터닝단계 동안 손상되는 것으로부터 제1도전층을 보호하는 이러한 단계들을 구성하는 집접회로의 로칼인터커넥트를 형성하기 위한 방법.
  2. 제1항에 있어서 금속을 포함하는 제1, 제2도정층이 동일한 도전물질로부터 형성되는 집적회로의 로칼인터커넥트를 형성하기 위한 방법.
  3. 제2항에 있어서 도전물질이 내화물질인 집적회로의 로칼인터커넥트를 형성하기 위한 방법.
  4. 제2항에 있어서 도전물이 내화금속 실리사이드인 집적회로의 로칼인터커넥트를 형성하기 위한 방법.
  5. 제4항에 있어서 내화금속 실리사이드가 탄탈륨 디실리사이드인 집적회로의 로칼인터커넥트를 형성하기 위한 방법.
  6. 제1항에 있어서 보호캡층이 다결정실리콘으로부터 형성되는 집적회로의 로칼인터커넥트를 형성하기 위한 방법.
  7. 제6항에 있어서 상기 보호캡층이 형성단계후에, 도전률을 개선하기 위하여 불순물을 게이트다결정실리콘층과 보호캡층으로 도입하는 단계를 구성하는 집적회로의 로칼인터커넥트를 형성하기 위한 방법.
  8. 제7항에 있어서 불순물들이 하나의 이식단계에 의해 도입되는 집적회로의 로칼인터커넥트를 형성하기 위한 방법.
  9. 제7항에 있어서 도입되는 불순물들이 인을 구성하는 집적회로의 로칼인터커넥트를 형성하기 위한 방법.
  10. 활성영역을 가지는 기판과, 게이트절연체, 다결정실리콘, 금속실리사이드, 보호캡의 적재층을 가지는 활성영역의 게이트전극과, 활성영역을 연결하는 로칼인터넥트와 여기에서 상기 로칼인터넥트가 상기 게이트에서 금속실리사이드와 동일 비율로 에칭하는 물질로부터 형성되는 집적회로 트랜지스터구조.
  11. 제10항에 있어서 상기 로칼인터커넥트와 게이트 금속실리사이드가 동일 물질로부터 형성되는 집적회로 트랜지스터구조.
  12. 제11항에 있어서 그러한 동일물질이 탄탈륨 디실리사이드를 구성하는 집적회로 트랜지스터구조.
  13. 제10항에 있어서 보호캡층이 다결정 실리콘을 구성하는 집적회로 트랜지스터구조.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019900007526A 1989-05-31 1990-05-24 집적회로용 로칼인터커넥트 KR900019239A (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US359860 1989-05-31
US07/359,860 US4978637A (en) 1989-05-31 1989-05-31 Local interconnect process for integrated circuits

Publications (1)

Publication Number Publication Date
KR900019239A true KR900019239A (ko) 1990-12-24

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KR1019900007526A KR900019239A (ko) 1989-05-31 1990-05-24 집적회로용 로칼인터커넥트

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Country Link
US (2) US4978637A (ko)
EP (1) EP0400821B1 (ko)
JP (1) JP2628399B2 (ko)
KR (1) KR900019239A (ko)
DE (1) DE69014998T2 (ko)

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Also Published As

Publication number Publication date
EP0400821A2 (en) 1990-12-05
EP0400821A3 (en) 1992-09-02
EP0400821B1 (en) 1994-12-14
DE69014998D1 (de) 1995-01-26
JP2628399B2 (ja) 1997-07-09
DE69014998T2 (de) 1995-06-08
JPH0322462A (ja) 1991-01-30
US4978637A (en) 1990-12-18
USRE35111E (en) 1995-12-05

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