KR970008432A - 패키지 성형장치 - Google Patents

패키지 성형장치 Download PDF

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Publication number
KR970008432A
KR970008432A KR1019950022122A KR19950022122A KR970008432A KR 970008432 A KR970008432 A KR 970008432A KR 1019950022122 A KR1019950022122 A KR 1019950022122A KR 19950022122 A KR19950022122 A KR 19950022122A KR 970008432 A KR970008432 A KR 970008432A
Authority
KR
South Korea
Prior art keywords
package
thickness
lead frame
molding apparatus
package forming
Prior art date
Application number
KR1019950022122A
Other languages
English (en)
Other versions
KR0151828B1 (ko
Inventor
노희선
최희국
조인식
박태성
Original Assignee
김광호
삼성전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김광호, 삼성전자 주식회사 filed Critical 김광호
Priority to KR1019950022122A priority Critical patent/KR0151828B1/ko
Priority to US08/542,011 priority patent/US5811132A/en
Priority to JP26511995A priority patent/JP3179003B2/ja
Publication of KR970008432A publication Critical patent/KR970008432A/ko
Application granted granted Critical
Publication of KR0151828B1 publication Critical patent/KR0151828B1/ko

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B29—WORKING OF PLASTICS; WORKING OF SUBSTANCES IN A PLASTIC STATE IN GENERAL
    • B29C—SHAPING OR JOINING OF PLASTICS; SHAPING OF MATERIAL IN A PLASTIC STATE, NOT OTHERWISE PROVIDED FOR; AFTER-TREATMENT OF THE SHAPED PRODUCTS, e.g. REPAIRING
    • B29C45/00—Injection moulding, i.e. forcing the required volume of moulding material through a nozzle into a closed mould; Apparatus therefor
    • B29C45/14—Injection moulding, i.e. forcing the required volume of moulding material through a nozzle into a closed mould; Apparatus therefor incorporating preformed parts or layers, e.g. injection moulding around inserts or for coating articles
    • B29C45/14639—Injection moulding, i.e. forcing the required volume of moulding material through a nozzle into a closed mould; Apparatus therefor incorporating preformed parts or layers, e.g. injection moulding around inserts or for coating articles for obtaining an insulating effect, e.g. for electrical components
    • B29C45/14655—Injection moulding, i.e. forcing the required volume of moulding material through a nozzle into a closed mould; Apparatus therefor incorporating preformed parts or layers, e.g. injection moulding around inserts or for coating articles for obtaining an insulating effect, e.g. for electrical components connected to or mounted on a carrier, e.g. lead frame
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10253—Silicon [Si]

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Mechanical Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Moulds For Moulding Plastics Or The Like (AREA)
  • Injection Moulding Of Plastics Or The Like (AREA)

Abstract

본 발명은 패키지 성형장치에 관한 것으로, 성형될 패키지의 불량을 방지하기 위해 상기 패키지 성형장치의 소정 영역에 배치ㆍ형성된 주입구들의 두께가 상기 성형될 패키지의 리드프레임의 두께에 대하여 크지 않게 형성된 것으로 패키지의 신뢰성을 개선하는 동시에 패키지의 외관을 미려하게 제작할 수 있는 효과가 있다.

Description

패키지 성형장치
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제4A도는 본 발명에 의한 하부 주입구 방식의 패키지 성형장치의 단면도, 제4B도는 제4A도의 주입구 부분의 측단면도, 제4C도는 본 발명에 의한 하부주입구 방식의 패키지 성형장치의 성형 메카니즘을 나타내는 예시도, 제4D도는 제4C도의 "A"부분을 상세하게 나타내는 확대도.

Claims (5)

  1. 성형공정에 사용되는 패키지 성형장치에 있어서, 성형될 패키지의 불량을 방지하기 위해 상기 패키지 성형장치의 소정 영역에 배치.형성된 주입구들의 두께(α),(β)가 상기 성형될 패키지의 리드프레임의 두께(δ)에 대하여 크지 않게 형성된 것을 특징으로 하는 패키지 성형장치.
  2. 제1항에 있어서, 상기 패키지 성형장치의 주입구 배치 방식이 하부 주입구(bottom gate)방식, 상부 주입구(top gate)방식 및 중앙부 주입구(center gate)방식중의 어느 하나인 것을 특징으로 하는 패키지 성형장치.
  3. 제1항에 있어서, 상기 리드프레임의 두께가 6mil 내지 12mil인 것을 특징으로 하는 패키지 성형장치.
  4. 제3항에 있어서, 상기 리드프레임의 두께가 6mil 내지 10mil인 것을 특징으로 하는 패키지 성형장치.
  5. 제4항에 있어서, 상기 리드프레임의 두께가 6mil인 것을 특징으로 하는 패키지 성형장치.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019950022122A 1995-07-25 1995-07-25 패키지 성형장치 KR0151828B1 (ko)

Priority Applications (3)

Application Number Priority Date Filing Date Title
KR1019950022122A KR0151828B1 (ko) 1995-07-25 1995-07-25 패키지 성형장치
US08/542,011 US5811132A (en) 1995-07-25 1995-10-12 Mold for semiconductor packages
JP26511995A JP3179003B2 (ja) 1995-07-25 1995-10-13 Ｔｓｏｐまたはｕｔｓｏｐのような超薄型半導体パッケージの成形装置および成形方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950022122A KR0151828B1 (ko) 1995-07-25 1995-07-25 패키지 성형장치

Publications (2)

Publication Number Publication Date
KR970008432A true KR970008432A (ko) 1997-02-24
KR0151828B1 KR0151828B1 (ko) 1998-12-01

Family

ID=19421554

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019950022122A KR0151828B1 (ko) 1995-07-25 1995-07-25 패키지 성형장치

Country Status (3)

Country Link
US (1) US5811132A (ko)
JP (1) JP3179003B2 (ko)
KR (1) KR0151828B1 (ko)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100210710B1 (ko) * 1996-09-24 1999-07-15 윤종용 성형 금형

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6316089B1 (en) 1997-12-05 2001-11-13 Showa Denko K.K. Photocurable prepreg sheet for waterproofing, method and apparatus for production of prepreg sheet, and waterproofing method using the sheet
EP1075022A1 (en) * 1999-08-04 2001-02-07 STMicroelectronics S.r.l. Offset edges mold for plastic packaging of integrated semiconductor devices
DE10159522A1 (de) * 2001-12-05 2003-06-26 G L I Global Light Ind Gmbh Verfahren zur Herstellung von LED-Körpern
DE10242947B8 (de) * 2002-09-16 2009-06-18 Odelo Led Gmbh Verfahren zum Herstellen von LED-Körpern mit Hilfe einer Querschnittsverengung und Vorrichtung zur Durchführung des Herstellungsverfahrens
US7741707B2 (en) * 2006-02-27 2010-06-22 Stats Chippac Ltd. Stackable integrated circuit package system

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62173726A (ja) * 1986-01-27 1987-07-30 Rohm Co Ltd 半導体装置用樹脂成形方法
JPH0694146B2 (ja) * 1986-05-09 1994-11-24 富士通株式会社 トランスフア成形金型
US4954308A (en) * 1988-03-04 1990-09-04 Citizen Watch Co., Ltd. Resin encapsulating method
JPH04245447A (ja) * 1991-01-30 1992-09-02 Toshiba Corp 半導体素子樹脂封止用金型
JP3127555B2 (ja) * 1992-04-02 2001-01-29 富士電機株式会社 透明樹脂封止形半導体素子の成形用金型、およびその半導体素子の成形方法
US5326243A (en) * 1992-06-25 1994-07-05 Fierkens Richard H J Compression-cavity mold for plastic encapsulation of thin-package integrated circuit device
JPH06124971A (ja) * 1992-10-14 1994-05-06 Nec Corp 樹脂封止金型
JP2586831B2 (ja) * 1994-09-22 1997-03-05 日本電気株式会社 樹脂封止用金型および半導体装置の製造方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100210710B1 (ko) * 1996-09-24 1999-07-15 윤종용 성형 금형

Also Published As

Publication number Publication date
KR0151828B1 (ko) 1998-12-01
JPH0936157A (ja) 1997-02-07
JP3179003B2 (ja) 2001-06-25
US5811132A (en) 1998-09-22

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