KR890013766A - 개량된 리드프레임 및 개량된 리드프레임을 사용하는 전자부품을 제조하는 방법 - Google Patents
개량된 리드프레임 및 개량된 리드프레임을 사용하는 전자부품을 제조하는 방법 Download PDFInfo
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- KR890013766A KR890013766A KR1019890002203A KR890002203A KR890013766A KR 890013766 A KR890013766 A KR 890013766A KR 1019890002203 A KR1019890002203 A KR 1019890002203A KR 890002203 A KR890002203 A KR 890002203A KR 890013766 A KR890013766 A KR 890013766A
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- 238000005452 bending Methods 0.000 claims 4
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- 229910045601 alloy Inorganic materials 0.000 claims 2
- 238000009713 electroplating Methods 0.000 claims 2
- 239000000463 material Substances 0.000 claims 2
- 238000009966 trimming Methods 0.000 claims 2
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
- H01L21/4842—Mechanical treatment, e.g. punching, cutting, deforming, cold welding
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- H—ELECTRICITY
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01021—Scandium [Sc]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49121—Beam lead frame or beam lead device
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Lead Frames For Integrated Circuits (AREA)
- Fixed Capacitors And Capacitor Manufacturing Machines (AREA)
Abstract
내용 없음.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본 발명에 따라 배치된 리드프레임을 포함하는 리드 프레임 스트립의 일부의 상세 평면도.
제2도는 제1도의 수정실시예를 보여주는 평면도.
제3도는 제1도의 리드프레임 스트립을 사용하는 전자부품을 제조하는 방법을 설명하기 위한 흐름도.
Claims (8)
- 전자부품의 제조에 사용되는 리드프레임에 있어서, 그 안에 형성된 중심개구를 갖는 외측프레임부; 상기 외측프레임부에 의하여 지지되며, 그의 상기 중심개구내에 배열되며, 전자소자가 장착될 장착부 ; 상기 장착부의 측을 따라 각각 배열되며, 모두가 공통타이바 소자에 의하여 서로 접속된 상기 어레이내에 포함된 적어도 하나의 리드소자어레이 ; 및 상기 외측프레임부와 상기 리드소자 어레이 사이에 연장되어 상기 외측프레임부에 의하여 상기 리드소자 어레이를 지지하며, 그의 각각이 변형에 의하여 신장될 수 있는 형상부를 포함하는 적어도 2개의 확장 가능한 타이바소자로 구성되어 있는 것을 특징으로 하는 리드 프레임.
- 제1항에 있어서, 상기 공통 타이바소자가 상기 어레이내에 포함된 상기 리드소자의 외측단과 일체적이며, 상기 확장가능한 타이바 소자의 각각이 그의 일단에 상기 외측 프레임부와 접속되며 그의 타단에 상기 공통타이바소자에 접속되는 것을 특징으로 하는 리드프레임.
- 제1항에 있어서, 상기 확장 가능한 타이바소자중 하나는 일단에 상기 외측프레임부에 접속되며, 타단에 상기 어레이내의 리드소자중 최외각의 것과 접속되고, 나머지 확장 가능한 타이바소자는 타단에서 상기 외측프레임부와 리드소자중 나머지 최외각의 것과 접속되는 것을 특징으로 하는 리드프레임.
- 제1항에 있어서, 상기 외측프레임부에 의하여 상기 리드소자어레이를 지지하는 상기 확장 가능한 타이바 소자가 상기 리드소자 어레이의 중심에 대칭적으로 배열되는 것을 특징으로 하는 리드프레임.
- 그안에 중심개구가 형성되어 있는 외측프레임부, 외측프레임부에 의해 지지되며 그의 상기 중심개구내에 배열되는 장착부, 및 장착부의 측면에 따라 배열된 적어도 하나의 리드소자 어레이를 포함하는 리드프레임을 사용하는 전자부품 제조방법에 있어서, 상기 리드프레임의 장착부상에 전자소자를 장착하는 단계; 상기 리드프레임의 장착부, 그위에 장착된 전자소자 및 상기 리드소자 어레이에 포함된 리드소자의 내측단부를 적당한 물질로 시일링하는 단계; 프레스에 의하여 시일링부로부터 연장된 리드소자의 외측부를 벤딩하는 단계; 상기 리드 프레임의 절곡된 리드소자를 적당한 합금층으로 코칭하기 위해 전해도금 공정을 실행하는 단계, 및 상기 리드프레임의 절곡되어 도금된 리드소자를 트리밍하는 단계로 구성되는 것을 특징으로 하는 방법.
- 제5항에 있어서, 벤딩단계가 장착단계전에 실행되는 것을 특징으로 하는 방법.
- 제1항에 기재된 리드프레임을 사용하는 전자부품을 제조하는 방법에 있어서, 상기 리드프레임의 장착부 상에 전자소자를 장착하는 단계; 상기 리드프레임의 장착부 그위에 장착된 상기 전자소자, 및 상기 리드 프레임의 리드 소자의 내측단부를 적당한 물질로 시일링 하는 단계; 상기 외측프레임부로부터 상기 리드소자어레이를 지지하는 상기 확장 가능한 타이바의 형성부가 리드소자 어레이와 외측 프레임부 사이에 유지하도록 신장되며 프레스에 의하여 밀봉된 부분으로부터 연장한 리드소자의 외각부를 벤딩하는 단계; 상기 리드프레임의 절곡된 리드소자를 적당한 합금층으로 코팅하도록 전해도금 공정을 실행하는 단계; 및 상기 리드프레임의 절곡되고 도금된 리드소자를 트리밍하는 단계로 구성되는 것을 특징으로 하는 방법.
- 제7항에 있어서, 상기 벤딩단계가 장착단계에 앞서 실행되는 방법.※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP63-042815 | 1988-02-24 | ||
JP63042815A JPH0828455B2 (ja) | 1988-02-24 | 1988-02-24 | リードフレーム及びそれを用いた電子部品の製造方法 |
JP?63-42815 | 1988-02-24 |
Publications (2)
Publication Number | Publication Date |
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KR890013766A true KR890013766A (ko) | 1989-09-25 |
KR920010198B1 KR920010198B1 (ko) | 1992-11-21 |
Family
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Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019890002203A KR920010198B1 (ko) | 1988-02-24 | 1989-02-24 | 개량된 리드프레임 및 개량된 리드프레임을 사용하는 전자부품을 제조하는 방법 |
Country Status (5)
Country | Link |
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US (2) | US4977442A (ko) |
EP (1) | EP0330512B1 (ko) |
JP (1) | JPH0828455B2 (ko) |
KR (1) | KR920010198B1 (ko) |
DE (1) | DE68928185T2 (ko) |
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JPH0793400B2 (ja) * | 1990-03-06 | 1995-10-09 | 株式会社東芝 | 半導体装置 |
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EP0452634B1 (en) * | 1990-03-16 | 1997-05-02 | Sumitomo Electric Industries, Ltd. | Lead frame for semiconductor device |
JPH0464256A (ja) * | 1990-07-04 | 1992-02-28 | Mitsubishi Electric Corp | 半導体装置の製造方法 |
AU631000B2 (en) * | 1990-08-28 | 1992-11-12 | Sumitomo Electric Industries, Ltd. | Optical module |
US5192681A (en) * | 1990-08-31 | 1993-03-09 | Texas Instruments Incorporated | Low cost erasable programmable read only memory package |
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JP2608192B2 (ja) * | 1991-04-26 | 1997-05-07 | 三菱電機株式会社 | リードフレーム |
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EP0537982A2 (en) * | 1991-10-14 | 1993-04-21 | Fujitsu Limited | Semiconductor device having improved leads |
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JP3016658B2 (ja) * | 1992-04-28 | 2000-03-06 | ローム株式会社 | リードフレーム並びに半導体装置およびその製法 |
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JP2000188366A (ja) * | 1998-12-24 | 2000-07-04 | Hitachi Ltd | 半導体装置 |
US7132734B2 (en) * | 2003-01-06 | 2006-11-07 | Micron Technology, Inc. | Microelectronic component assemblies and microelectronic component lead frame structures |
DE10303455B4 (de) * | 2003-01-29 | 2007-11-29 | Osram Opto Semiconductors Gmbh | Leiterrahmenband und Verfahren zum Herstellen einer Mehrzahl von Leiterrahmen-basierten Leuchtdiodenbauelementen |
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US7183485B2 (en) * | 2003-03-11 | 2007-02-27 | Micron Technology, Inc. | Microelectronic component assemblies having lead frames adapted to reduce package bow |
WO2007102041A1 (en) * | 2006-03-09 | 2007-09-13 | Infineon Technologies Ag | Lead fingers of a semiconductor chip with an even layer of coating |
JP4921016B2 (ja) * | 2006-03-31 | 2012-04-18 | ルネサスエレクトロニクス株式会社 | リードカット装置および半導体装置の製造方法 |
CN101312112B (zh) * | 2007-05-21 | 2011-10-05 | 中芯国际集成电路制造(上海)有限公司 | 芯片封装外引线成型模具 |
Family Cites Families (16)
Publication number | Priority date | Publication date | Assignee | Title |
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US4012766A (en) * | 1973-08-28 | 1977-03-15 | Western Digital Corporation | Semiconductor package and method of manufacture thereof |
JPS5212573A (en) * | 1975-07-21 | 1977-01-31 | Hitachi Ltd | Reed frame |
JPS5521128A (en) * | 1978-08-02 | 1980-02-15 | Hitachi Ltd | Lead frame used for semiconductor device and its assembling |
US4214364A (en) * | 1979-05-21 | 1980-07-29 | Northern Telecom Limited | Hermetic and non-hermetic packaging of devices |
CA1145860A (en) * | 1981-01-29 | 1983-05-03 | John C. Walker | Leadframe for leaded semiconductor chip carriers |
US4477827A (en) * | 1981-02-02 | 1984-10-16 | Northern Telecom Limited | Lead frame for leaded semiconductor chip carriers |
US4441118A (en) * | 1983-01-13 | 1984-04-03 | Olin Corporation | Composite copper nickel alloys with improved solderability shelf life |
JPS615557A (ja) * | 1984-06-20 | 1986-01-11 | Hitachi Ltd | リ−ドフレ−ム |
JPS61269345A (ja) * | 1985-05-24 | 1986-11-28 | Hitachi Ltd | 半導体装置 |
JPH0656870B2 (ja) * | 1985-06-05 | 1994-07-27 | 住友電気工業株式会社 | Ic用リ−ドフレ−ム |
JPS6273554U (ko) * | 1985-10-28 | 1987-05-11 | ||
US4905074A (en) * | 1985-11-29 | 1990-02-27 | Olin Corporation | Interdiffusion resistant Fe-Ni alloys having improved glass sealing property |
US4721993A (en) * | 1986-01-31 | 1988-01-26 | Olin Corporation | Interconnect tape for use in tape automated bonding |
US4829362A (en) * | 1986-04-28 | 1989-05-09 | Motorola, Inc. | Lead frame with die bond flag for ceramic packages |
JPS63148670A (ja) * | 1986-12-12 | 1988-06-21 | Texas Instr Japan Ltd | リ−ドフレ−ム材 |
JPH01145839A (ja) * | 1987-12-02 | 1989-06-07 | Rhythm Watch Co Ltd | リードフレーム |
-
1988
- 1988-02-24 JP JP63042815A patent/JPH0828455B2/ja not_active Expired - Lifetime
-
1989
- 1989-02-24 EP EP89301889A patent/EP0330512B1/en not_active Expired - Lifetime
- 1989-02-24 KR KR1019890002203A patent/KR920010198B1/ko not_active IP Right Cessation
- 1989-02-24 US US07/314,793 patent/US4977442A/en not_active Expired - Lifetime
- 1989-02-24 DE DE68928185T patent/DE68928185T2/de not_active Expired - Fee Related
-
1990
- 1990-10-03 US US07/592,324 patent/US5094982A/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
EP0330512A2 (en) | 1989-08-30 |
JPH0828455B2 (ja) | 1996-03-21 |
EP0330512A3 (en) | 1992-05-06 |
DE68928185T2 (de) | 1997-11-13 |
US4977442A (en) | 1990-12-11 |
JPH01216564A (ja) | 1989-08-30 |
US5094982A (en) | 1992-03-10 |
KR920010198B1 (ko) | 1992-11-21 |
EP0330512B1 (en) | 1997-07-23 |
DE68928185D1 (de) | 1997-08-28 |
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