KR970053752A - 엘.오.씨(LOC:Lead On Chip) 패키지 및 그 제조방법 - Google Patents
엘.오.씨(LOC:Lead On Chip) 패키지 및 그 제조방법 Download PDFInfo
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- KR970053752A KR970053752A KR1019950051426A KR19950051426A KR970053752A KR 970053752 A KR970053752 A KR 970053752A KR 1019950051426 A KR1019950051426 A KR 1019950051426A KR 19950051426 A KR19950051426 A KR 19950051426A KR 970053752 A KR970053752 A KR 970053752A
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- package
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- semiconductor chip
- lead frame
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49503—Lead-frames or other flat leads characterised by the die pad
- H01L23/4951—Chip-on-leads or leads-on-chip techniques, i.e. inner lead fingers being used as die pad
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- H01—ELECTRIC ELEMENTS
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/4826—Connecting between the body and an opposite side of the item with respect to the body
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73215—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Lead Frames For Integrated Circuits (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
본 발명은 엘.오.씨(LOC) 패키지 및 그 제조방법에 관한 것이다. 본 발명의 엘.오.씨(LOC) 반도체 패키지는 반도체 칩과, 반도체 칩의 소정부위에 층(Layer)의 형태로 부착되는 복수개의 양면 테이프와, 양면 테이프의 형태와 부합되게 단차를 갖도록 형성된 리드 프레임과, 리드 프레임의 인너리드와 반도체 칩의 패드를 전기적으로 연결하기 위한 와이어와, 반도체 칩과, 리드 프레임 및 와이어를 둘러싸는 코팅액으로 구성된다. 또한, 엘.오.씨(LOC) 패키지 제조방법은, 칩사이즈 패키지용 엘.오.씨(LOC) 리드 프레임을 제공하는 공정과; 리드 프레임의 소정부위에 복수개의 양면 테이프를 부착시키는 공정과; 양면 테이프에 반도체 칩을 부착시키는 공정과; 반도체 칩의 패드와 리드 프레임의 인너리드를 도전수단으로 와이 본딩하는 공정과; 리드 프레임들의 내부에 코팅액을 주사하는 포팅공정으로 구성된다. 이와 같이 구성된 엘.오.씨(LOC) 패키지 및 그 제조방법은 제조공정을 단순화함과 아울러 패키지의 원가를 절감할 수 있다.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제3도는 본 발명의 일 실시예에 따른 엘.오.씨(LOC) 패키지의 리드 프레임을 나타낸 평면도.
Claims (7)
- 반도체 칩과; 상기 반도체 칩의 소정부위에 층(Layer)의 형태로 부착되는 복수개의 양면 테이프와; 상기 양면 테이프의 형태와 부합되게 단차를 갖도록 형성된 리드 프레임과; 상기 리드 프레임의 인너리드와 반도체 칩의 패드를 전기적으로 연결하기 위한 와이어와; 상기 반도체 칩과, 리드 프레임 및 와이어를 둘러싸는 코팅액으로 구성된 것을 특징으로 하는 엘.오.씨(LOC) 패키지.
- 제1항에 있어서, 상기 양면 테이프는 서로 다른 크기로 형성되는 것을 특징으로 하는 엘.오.씨(LOC) 패키지.
- 제1항에 있어서, 상기 양면 테이프의 양단에는 코팅액의 흐름을 방지하기 위하여 양면 테이프 댐바가 형성되는 것을 특징으로 하는 엘.오.씨(LOC) 패키지.
- 제1항에 있어서, 상기 코팅액은 폴리이미드 계열 중의 하나로 이루어진 것을 특징으로 하는 엘.오.씨(LOC) 패키지.
- 칩사이즈 패키지용 엘.오.씨(LOC) 리드 프레임을 제공하는 공정과; 상기 리드 프레임의 소정부위에 복수개의 양면 테이프를 부착시키는 공정과; 상기 양면 테이프에 반도체 칩을 부착시키는 공정과; 상기 반도체 칩의 패드와 리드 프레임의 인너리드를 도전수단으로 와이 본딩하는 공정과; 상기 리드 프레임들의 내부에 코팅액을 주사하는 포팅공정으로 구성되는 것을 특징으로 하는 엘.오.씨(LOC) 패키지 제조방법.
- 제5항에 있어서, 상기 포팅공정후, 상기 코팅액을 소정시간 경화시키는 공정과; 양면 테이프 댐바를 절단하는 공정을 더 포함하는 것을 특징으로 하는 엘.오.씨(LOC) 패키지 제조방법.
- 제5항에 있어서, 상기 코팅액은 폴리이미드 계열중의 하나를 사용하는 것을 특징으로 하는 엘.오.씨(LOC) 패키지 제조방법.※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019950051426A KR0167297B1 (ko) | 1995-12-18 | 1995-12-18 | 엘.오.씨 패키지 및 그 제조방법 |
US08/588,789 US5834830A (en) | 1995-12-18 | 1996-01-19 | LOC (lead on chip) package and fabricating method thereof |
JP1764496A JP2826718B2 (ja) | 1995-12-18 | 1996-02-02 | Loc半導体パッケージ及びその製造方法 |
CN96120356A CN1129186C (zh) | 1995-12-18 | 1996-10-28 | Loc半导体封装及其制造方法 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019950051426A KR0167297B1 (ko) | 1995-12-18 | 1995-12-18 | 엘.오.씨 패키지 및 그 제조방법 |
Publications (2)
Publication Number | Publication Date |
---|---|
KR970053752A true KR970053752A (ko) | 1997-07-31 |
KR0167297B1 KR0167297B1 (ko) | 1998-12-15 |
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ID=19441030
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019950051426A KR0167297B1 (ko) | 1995-12-18 | 1995-12-18 | 엘.오.씨 패키지 및 그 제조방법 |
Country Status (4)
Country | Link |
---|---|
US (1) | US5834830A (ko) |
JP (1) | JP2826718B2 (ko) |
KR (1) | KR0167297B1 (ko) |
CN (1) | CN1129186C (ko) |
Families Citing this family (75)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3026426B2 (ja) * | 1996-08-29 | 2000-03-27 | 沖電気工業株式会社 | 樹脂封止型半導体装置とその製造方法及びその金型構造 |
JP2908350B2 (ja) * | 1996-10-09 | 1999-06-21 | 九州日本電気株式会社 | 半導体装置 |
US6005286A (en) * | 1997-10-06 | 1999-12-21 | Micron Technology, Inc. | Increasing the gap between a lead frame and a semiconductor die |
US6143981A (en) | 1998-06-24 | 2000-11-07 | Amkor Technology, Inc. | Plastic integrated circuit package and method and leadframe for making the package |
US6181569B1 (en) | 1999-06-07 | 2001-01-30 | Kishore K. Chakravorty | Low cost chip size package and method of fabricating the same |
US6387732B1 (en) | 1999-06-18 | 2002-05-14 | Micron Technology, Inc. | Methods of attaching a semiconductor chip to a leadframe with a footprint of about the same size as the chip and packages formed thereby |
KR100566781B1 (ko) | 1999-11-10 | 2006-04-03 | 삼성전자주식회사 | 리드 온 칩 타입 반도체 패키지 |
US6322903B1 (en) | 1999-12-06 | 2001-11-27 | Tru-Si Technologies, Inc. | Package of integrated circuits and vertical integration |
US6639308B1 (en) | 1999-12-16 | 2003-10-28 | Amkor Technology, Inc. | Near chip size semiconductor package |
DE10014304B4 (de) * | 2000-03-23 | 2007-08-02 | Infineon Technologies Ag | Halbleiterbauelement und Verfahren zu dessen Herstellung |
US7042068B2 (en) | 2000-04-27 | 2006-05-09 | Amkor Technology, Inc. | Leadframe and semiconductor package made using the leadframe |
US6531335B1 (en) * | 2000-04-28 | 2003-03-11 | Micron Technology, Inc. | Interposers including upwardly protruding dams, semiconductor device assemblies including the interposers, and methods |
US6545345B1 (en) | 2001-03-20 | 2003-04-08 | Amkor Technology, Inc. | Mounting for a package containing a chip |
KR100369393B1 (ko) | 2001-03-27 | 2003-02-05 | 앰코 테크놀로지 코리아 주식회사 | 리드프레임 및 이를 이용한 반도체패키지와 그 제조 방법 |
US6608366B1 (en) | 2002-04-15 | 2003-08-19 | Harry J. Fogelson | Lead frame with plated end leads |
US6905914B1 (en) | 2002-11-08 | 2005-06-14 | Amkor Technology, Inc. | Wafer level package and fabrication method |
US7723210B2 (en) | 2002-11-08 | 2010-05-25 | Amkor Technology, Inc. | Direct-write wafer level chip scale package |
US6798047B1 (en) | 2002-12-26 | 2004-09-28 | Amkor Technology, Inc. | Pre-molded leadframe |
US6750545B1 (en) | 2003-02-28 | 2004-06-15 | Amkor Technology, Inc. | Semiconductor package capable of die stacking |
US6927483B1 (en) | 2003-03-07 | 2005-08-09 | Amkor Technology, Inc. | Semiconductor package exhibiting efficient lead placement |
US6794740B1 (en) | 2003-03-13 | 2004-09-21 | Amkor Technology, Inc. | Leadframe package for semiconductor devices |
US6879034B1 (en) | 2003-05-01 | 2005-04-12 | Amkor Technology, Inc. | Semiconductor package including low temperature co-fired ceramic substrate |
US6921967B2 (en) | 2003-09-24 | 2005-07-26 | Amkor Technology, Inc. | Reinforced die pad support structure |
US7507603B1 (en) | 2005-12-02 | 2009-03-24 | Amkor Technology, Inc. | Etch singulated semiconductor package |
US7572681B1 (en) | 2005-12-08 | 2009-08-11 | Amkor Technology, Inc. | Embedded electronic component package |
US7902660B1 (en) | 2006-05-24 | 2011-03-08 | Amkor Technology, Inc. | Substrate for semiconductor device and manufacturing method thereof |
US7968998B1 (en) | 2006-06-21 | 2011-06-28 | Amkor Technology, Inc. | Side leaded, bottom exposed pad and bottom exposed lead fusion quad flat semiconductor package |
US7687893B2 (en) | 2006-12-27 | 2010-03-30 | Amkor Technology, Inc. | Semiconductor package having leadframe with exposed anchor pads |
US7829990B1 (en) | 2007-01-18 | 2010-11-09 | Amkor Technology, Inc. | Stackable semiconductor package including laminate interposer |
US7982297B1 (en) | 2007-03-06 | 2011-07-19 | Amkor Technology, Inc. | Stackable semiconductor package having partially exposed semiconductor die and method of fabricating the same |
US7977774B2 (en) | 2007-07-10 | 2011-07-12 | Amkor Technology, Inc. | Fusion quad flat semiconductor package |
US7687899B1 (en) | 2007-08-07 | 2010-03-30 | Amkor Technology, Inc. | Dual laminate package structure with embedded elements |
US7777351B1 (en) | 2007-10-01 | 2010-08-17 | Amkor Technology, Inc. | Thin stacked interposer package |
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US9679831B2 (en) * | 2015-08-13 | 2017-06-13 | Cypress Semiconductor Corporation | Tape chip on lead using paste die attach material |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS60165742A (ja) * | 1984-02-08 | 1985-08-28 | Hitachi Tokyo Electronics Co Ltd | 半導体装置 |
JPH0322465A (ja) * | 1989-06-20 | 1991-01-30 | Sumitomo Bakelite Co Ltd | 樹脂封止型半導体装置 |
US5583375A (en) * | 1990-06-11 | 1996-12-10 | Hitachi, Ltd. | Semiconductor device with lead structure within the planar area of the device |
US5227661A (en) * | 1990-09-24 | 1993-07-13 | Texas Instruments Incorporated | Integrated circuit device having an aminopropyltriethoxysilane coating |
JP3238004B2 (ja) * | 1993-07-29 | 2001-12-10 | 株式会社東芝 | 半導体装置の製造方法 |
US5585600A (en) * | 1993-09-02 | 1996-12-17 | International Business Machines Corporation | Encapsulated semiconductor chip module and method of forming the same |
JPH07297345A (ja) * | 1994-04-28 | 1995-11-10 | Hitachi Cable Ltd | 半導体装置用リードフレーム |
-
1995
- 1995-12-18 KR KR1019950051426A patent/KR0167297B1/ko not_active IP Right Cessation
-
1996
- 1996-01-19 US US08/588,789 patent/US5834830A/en not_active Expired - Lifetime
- 1996-02-02 JP JP1764496A patent/JP2826718B2/ja not_active Expired - Fee Related
- 1996-10-28 CN CN96120356A patent/CN1129186C/zh not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
CN1153998A (zh) | 1997-07-09 |
CN1129186C (zh) | 2003-11-26 |
JPH09213842A (ja) | 1997-08-15 |
KR0167297B1 (ko) | 1998-12-15 |
US5834830A (en) | 1998-11-10 |
JP2826718B2 (ja) | 1998-11-18 |
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