JPS61104629A - 半導体装置 - Google Patents

半導体装置

Info

Publication number
JPS61104629A
JPS61104629A JP22704784A JP22704784A JPS61104629A JP S61104629 A JPS61104629 A JP S61104629A JP 22704784 A JP22704784 A JP 22704784A JP 22704784 A JP22704784 A JP 22704784A JP S61104629 A JPS61104629 A JP S61104629A
Authority
JP
Japan
Prior art keywords
stage
paste
chip
leads
pattern
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP22704784A
Other languages
English (en)
Inventor
Tadanobu Terui
照井　忠信
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP22704784A priority Critical patent/JPS61104629A/ja
Publication of JPS61104629A publication Critical patent/JPS61104629A/ja
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/2612—Auxiliary members for layer connectors, e.g. spacers
    • H01L2224/26152—Auxiliary members for layer connectors, e.g. spacers being formed on an item to be connected not being a semiconductor or solid-state body
    • H01L2224/26175—Flow barriers
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    • H01L2224/27—Manufacturing methods
    • H01L2224/27011—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature
    • H01L2224/27013—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature for holding or confining the layer connector, e.g. solder flow barrier
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    • H01L2224/293—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29338—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/29339—Silver [Ag] as principal constituent
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    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
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    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/83009—Pre-treatment of the layer connector or the bonding area
    • H01L2224/83051—Forming additional members, e.g. dam structures
    • H—ELECTRICITY
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    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H—ELECTRICITY
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
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    • H01L2924/06—Polymers
    • H01L2924/078—Adhesive characteristics other than chemical
    • H01L2924/07802—Adhesive characteristics other than chemical not being an ohmic electrical conductor
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
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    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/15165—Monolayer substrate

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体装置、詳しくは基板上に印刷されたステ
ージに半導体チップをダイス付けしてなる装置における
改良に関する。
第３図の部分的な断面図に示されるモジュールは、チッ
プ・オン・ボード方式の構造の一例である。同図におい
て、２１は基板、２２と２３は基板２１に印刷されたイ
ンナーリード（以下単にリードという）とステージ、２
４は半導体チップ（以下単にチツブという）、２５はチ
ップ２４の電極とり−ド２２とを接続するワイヤ、２６
はチップ２４をダイス付けするｔＭ、（Ａｇ）ペースト
、２７はチップ２４を封止する樹脂を示す。厚さに割附
の有る分野に利用価値が大きく、例えば、キャッシュカ
ード、ガソリンスタンドなどで用いられている磁気カー
ドに代るべきものとして、ＩＣカード等が注目されてい
る。
Ｃ発明が解決しようとする問題点〕 前記したチップ２４をステージにダイス付けするには、
Ａｇペーストをステージ２３上に塗布し、チップ２４を
その上にのせてスクラブ（こすり付け）または、押し付
けてペーストを拡げる。
かかるスクラブまたは押し付けによってＡｇペーストを
拡げようとすると、軸ペーストが第３図に示される如く
ステージからはみ出ることがある。
ここでステージからはみ出るＡｇペーストの量が多し）
と、へｇペーストがリード２２に達することがあり、絶
縁性保持の観点から問題がある。
また、厚さに制限の有るモジュールは、各部が薄くまた
は低く形成される。そこで、ワイヤ２５を低く張ろうと
すると、ワイヤの垂れ下がりが発生ずるおそれがあり、
そうなるとＡｇペースト２６が僅かばかりはみ出たとき
でもワイヤとＡｇペーストが接触し短絡を生ずる問題が
ある。ワイヤに代る接続手段について研究はなされてい
るが、現在のところ可撓性（ｆｌｅｘｉｂｉｌｉｔｙ　
）の点でワイヤボンディング法が有望と見られるため、
前記した問題の解決が要望されている。またチップの厚
さも通常の厚さよりも薄くなっているためダイス（−１
時のＡｇペーストのはい」二かりも問題となっている。
〔問題点を解決するための手段〕
本発明は、」二記問題点を解消したＡｇペース１−を用
いる半導体チップのダイス付けのときのＡｇペース１〜
のはみ出しおよびはい上がりに対する対策を講した半導
体装置を提供するもので、その手段は、基板上に半導体
チップ搭載用ステージと、該ステージのまわりに配設さ
れたリードを有し、前記ステージに半導体チップが接着
され、前記ステージと前記リードの間の前記基板」二に
前記ステージから所定の間隔をおいて枠状パターンが設
けられてなることを特徴とする半導体装置によってなさ
れる。
〔作用〕
上記装置においては、ステージのまわりに枠状にパター
ンが形成されているので、Ａｇペーストがステージから
はみ出したとしても、枠状パターンによってそれがリー
ドに到達することが防止され、また多量のＡｇペースト
がはみ出したときでも、それはステージと枠状パターン
の間の隙間に流出するため、Ａｇペーストのチップへの
はい上がりも防止され、ワイヤとの接触も回避されるも
のである。
〔実施例〕
以下、図面を参照して本発明の実施例を詳細に説明する
。
第１図と第２図に、本発明実施例が平面図と断面図で示
され、これらの図において、１】は基板（例えばエポキ
シ樹脂製のもの）、１２と１３は導電性材料をプリント
して作ったリードとステージ、１４は半導体チップ（半
導体チップは第２図にのみ示される）、１５は半導体チ
ップ（以下単にチップという）の電極とり一ド１２とを
接続するワイヤ（ワイヤ１５も第２図にのみ示される）
、をそれぞれ示す。
図示の実施例においては、ステージ１３から所定の距離
をおいて、ステージを囲む所定の幅の枠状パターン１６
を形成する。枠状パターン１６は、ステージ、リードを
印刷する（パターニングする）ときに同時に印刷するこ
とによって形成する。そして、枠状パターンの幅および
枠状パターンとステージとの間の間隔は、通常、ステー
ジ、リードなどの厚さおよびチップサイズを考慮して適
宜設定する。そして、第２図に示されるように、ステー
ジ寸法を第３図に示される従来例よりも小に、すなわち
チップの寸法とほぼ同し大きさに設定することによって
、枠状パターンを設けることが半導体装置の小型化に悪
影響を及ぼすことのないよう゛にする。
ダイス付けのときＡｇペースト１７が第２図に示される
如くステージ１３からはみ出したとしても、それは枠状
パターン１６によって阻止されてリード１２に達するこ
とがない。そして、はみ出したＡｇペーストは、チップ
にはい上がることなく枠状パターン１６とステージ１３
との間の溝に流出することもあって、ワイヤ１５とＡｇ
ペースト１７との短絡が防止される。
チップのダイス付けの後には、従来技術の場合と同様に
樹脂１８をポツティングして封止する。
〔発明の効果〕
以上説明したように本発明によれば、印刷によってステ
ージとリードとが印刷され、ステージにチップがダイス
付けされたチップ・オン・ボード方式の半導体装置にお
いて、ステージなどの印刷のとき同時にステージのまわ
りに枠状パターンを形成し、このパターンとステージと
の間に溝を形成することによって、チップのダイス付け
のときのＡｇペーストのはみ出しが前記溝内に流出する
ので、半導体装置における絶縁性が十分保たれ、またＡ
ｇペーストとチップの電極とリード間の接続用ワイヤと
の短絡が防止され、しかも、かかる枠状パターンは容易
に、かつ、半導体装置の小型化を妨げることなく形成可
能である。
【図面の簡単な説明】
第１図と第２図は本発明実施例の平面図と断面図、第３
図は従来例の断面図である。 図中、１１は基板、１２はリード、１３はステージ、１
４は半導体チップ、１５はワイヤ、１６は枠状パターン
、１７はＡｇペースト、１８は樹脂、をそれぞれ示す。 第１図 第２図 第３図

Claims (1)

    【特許請求の範囲】
  1. 　基板上に半導体チップ搭載用ステージと、該ステージ
    のまわりに配設されたリードを有し、前記ステージに半
    導体チップが接着され、前記ステージと前記リードの間
    の前記基板上に前記ステージから所定の間隔をおいて枠
    状パターンが設けられてなることを特徴とする半導体装
    置。
JP22704784A 1984-10-29 1984-10-29 半導体装置 Pending JPS61104629A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP22704784A JPS61104629A (ja) 1984-10-29 1984-10-29 半導体装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP22704784A JPS61104629A (ja) 1984-10-29 1984-10-29 半導体装置

Publications (1)

Publication Number Publication Date
JPS61104629A true JPS61104629A (ja) 1986-05-22

Family

ID=16854693

Family Applications (1)

Application Number Title Priority Date Filing Date
JP22704784A Pending JPS61104629A (ja) 1984-10-29 1984-10-29 半導体装置

Country Status (1)

Country Link
JP (1) JPS61104629A (ja)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH027534A (ja) * 1988-06-27 1990-01-11 Fujitsu Ltd 半導体装置
EP1249870A3 (en) * 2001-04-11 2005-03-30 Sharp Kabushiki Kaisha Semiconductor device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH027534A (ja) * 1988-06-27 1990-01-11 Fujitsu Ltd 半導体装置
JP2530002B2 (ja) * 1988-06-27 1996-09-04 富士通株式会社 半導体装置
EP1249870A3 (en) * 2001-04-11 2005-03-30 Sharp Kabushiki Kaisha Semiconductor device

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