KR960005898A - 반도체기판 및 반도체기판의 제조방법 - Google Patents

반도체기판 및 반도체기판의 제조방법 Download PDF

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KR960005898A
KR960005898A KR1019950021530A KR19950021530A KR960005898A KR 960005898 A KR960005898 A KR 960005898A KR 1019950021530 A KR1019950021530 A KR 1019950021530A KR 19950021530 A KR19950021530 A KR 19950021530A KR 960005898 A KR960005898 A KR 960005898A
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South Korea
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substrate
heat treatment
oxide film
support substrate
semiconductor substrate
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KR1019950021530A
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KR100288815B1 (ko
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요코 이노우에
슈이치 사마타
요시아키 마츠시카
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사토 후미오
가부시키가이샤 도시바
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/322—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections
    • H01L21/3221—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections of silicon bodies, e.g. for gettering
    • H01L21/3226—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections of silicon bodies, e.g. for gettering of silicon on insulator
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/34—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies not provided for in groups H01L21/0405, H01L21/0445, H01L21/06, H01L21/16 and H01L21/18 with or without impurities, e.g. doping materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • H01L21/2003—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy characterised by the substrate
    • H01L21/2007—Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Element Separation (AREA)
  • Formation Of Insulating Films (AREA)

Abstract

본 발명은, 게터링 능력이 우수하고, 열 도너와 결정결함이 없는 반도체 기판 및, 이와 같은 반도체 기판을 복잡한 공정의 추가와 도펀트 불순물농도의 저하를 수반하지 않고 제작하기 위한 반도체기판의 제작방법을 제공한다.
본 발명은, 지지기판(11)으로서 비저항이 0.1Ω·cm 이하로 되도록 보론을 도입한 고종도 P형 기판을 사용한다. 또한, 제조공정으로서, 지지기판(11)을 환원성 분위기에서의 열처리를 1100℃ 이상에서 30분 이상 행하는 제1열처리공정과, 이 제1열처리 공정 후의 지지기판(11)에 한쪽의 표면에 산화막(12)을 형성한 고농도 P형 실리콘기판을 지지기판(11)과 산화막(12)이 접하도록 접착하는 접착공정, 이 접착공정 후의 지지기판(11)과 산화막(12) 및 실리콘기판의 열처리를 950℃ 이상에서 10분 이상 행하는 제2열처리 공정 및, 이 제2열처리 공정후의 실리콘기판을 박막화하는 박막화 공정을 구비한다.

Description

반도체 기판 및 반도체기판의 제조 방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본 발명의 각 실시 예 1~3에 따른 반도체기판의 구성을 개략적으로 나타내는 단면도이다.

Claims (4)

  1. 단결성 실리콘으로 이루어진 지지기판(11)과, 이 지지기판(11) 상에 형성된 산화막(12)과, 이 산화막(12)상에 형성된 P형 또는 I형의 단결정 실리콘으로 이루어진 박막(13)을 갖춘 반도체기판에 있어서, 상기 지지기판(11)은 비저항이 0.1Ω· cm 이하로 되도록 보론을 도입한 고농도 P형 기판인 것을 특징으로 하는 반도체기판.
  2. 제1항에 있어서, 상기 박막(13)의 산소농도를 5 X 1017cm-3이하로 하는 것을 특징으로 하는 반도체기판.
  3. 보론을 도입한 고농도 P형 단결정 실리콘으로 이루어진 지지기판(11)과, 이 지지기판 상에 형성된 산화막(12) 및, 이 산화막(12) 상에 형성된P형, N형 또는I형 단결정 실리콘으로 이루어진 박막(13)을 갖춘 반도체기판의 제조 방법에 있어서, 상기 지지기판에 대한 환원성 분위기에서의 열처리를 1100℃ 이상에서 30분 이상 행하는 제1열처리 공정도, 이 제1열처리 공정후의 상기 지지기판(11)도, 상기 박막을 형성하기 위한 고농도 P형 실리콘기판을 어느 하나의 기판의 표면에 형성된 상기 산화막(12)을 매기로 접하도록 접착하는 접착공정, 이 접착공정 후의 상기 지지기판(11)과 상기 산화막(12) 및 상기 실리콘 기판의 열처리를 950℃ 이상에서 10분 이상 행하는 제2열처리 공정 및, 이 제2열처리 공정 후의 상기 실리콘기판을 박막화하는 박막화 공정을 구비하여 이루어진 것을 특징으로 하는 반도체 기판의 제조방법.
  4. 제3항에 있어서, 상기 기판상에 두께가 10nm 이상 5mm 이하의 상기 산화막(12)을 형성하는 공정을 갖춘 것을 특징으로 하는 반도체기판의 제조방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019950021530A 1994-07-21 1995-07-21 반도체기판의제조방법 KR100288815B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP94-169588 1994-07-21
JP6169588A JPH0837286A (ja) 1994-07-21 1994-07-21 半導体基板および半導体基板の製造方法

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KR960005898A true KR960005898A (ko) 1996-02-23
KR100288815B1 KR100288815B1 (ko) 2001-11-26

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EP (1) EP0697713A1 (ko)
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KR (1) KR100288815B1 (ko)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2806277B2 (ja) * 1994-10-13 1998-09-30 日本電気株式会社 半導体装置及びその製造方法
JP2755185B2 (ja) * 1994-11-07 1998-05-20 日本電気株式会社 Ｓｏｉ基板
US6054369A (en) * 1997-06-30 2000-04-25 Intersil Corporation Lifetime control for semiconductor devices
FR2777115B1 (fr) * 1998-04-07 2001-07-13 Commissariat Energie Atomique Procede de traitement de substrats semi-conducteurs et structures obtenues par ce procede
JP3762144B2 (ja) * 1998-06-18 2006-04-05 キヤノン株式会社 Ｓｏｉ基板の作製方法
JP2000294549A (ja) * 1999-02-02 2000-10-20 Nec Corp 半導体装置及びその製造方法
JP4765157B2 (ja) * 1999-11-17 2011-09-07 株式会社デンソー 半導体基板の製造方法
JP2003204048A (ja) * 2002-01-09 2003-07-18 Shin Etsu Handotai Co Ltd Ｓｏｉウエーハの製造方法及びｓｏｉウエーハ
US7713838B2 (en) 2003-09-08 2010-05-11 Sumco Corporation SOI wafer and its manufacturing method
JP2007059704A (ja) * 2005-08-25 2007-03-08 Sumco Corp 貼合せ基板の製造方法及び貼合せ基板
JP5194508B2 (ja) * 2007-03-26 2013-05-08 信越半導体株式会社 Ｓｏｉウエーハの製造方法
JP2008263087A (ja) 2007-04-12 2008-10-30 Shin Etsu Chem Co Ltd Ｓｏｉ基板の製造方法
JP5272329B2 (ja) 2007-05-22 2013-08-28 信越半導体株式会社 Ｓｏｉウエーハの製造方法
JP7334698B2 (ja) 2020-09-11 2023-08-29 信越半導体株式会社 Ｓｏｉウェーハの製造方法及びｓｏｉウェーハ

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GB2206445A (en) * 1987-07-01 1989-01-05 Spectrol Reliance Ltd Method of manufacturing dielectrically isolated integrated circuits and circuit elements
JP2685819B2 (ja) * 1988-03-31 1997-12-03 株式会社東芝 誘電体分離半導体基板とその製造方法
JPH0237771A (ja) * 1988-07-28 1990-02-07 Fujitsu Ltd Ｓｏｉ基板
JPH0246770A (ja) * 1988-08-08 1990-02-16 Seiko Epson Corp 半導体装置
JP2801704B2 (ja) * 1989-12-11 1998-09-21 株式会社東芝 半導体基板の製造方法
JPH05160090A (ja) * 1991-12-11 1993-06-25 Fujitsu Ltd 半導体基板の製造方法

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JPH0837286A (ja) 1996-02-06
EP0697713A1 (en) 1996-02-21
KR100288815B1 (ko) 2001-11-26

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