KR850002168A - 반도체장치 및 노출층을 이용한 제조공정 - Google Patents

반도체장치 및 노출층을 이용한 제조공정 Download PDF

Info

Publication number
KR850002168A
KR850002168A KR1019840003082A KR840003082A KR850002168A KR 850002168 A KR850002168 A KR 850002168A KR 1019840003082 A KR1019840003082 A KR 1019840003082A KR 840003082 A KR840003082 A KR 840003082A KR 850002168 A KR850002168 A KR 850002168A
Authority
KR
South Korea
Prior art keywords
wafer
temperature
reducing atmosphere
oxygen
elevated temperature
Prior art date
Application number
KR1019840003082A
Other languages
English (en)
Other versions
KR900005782B1 (ko
Inventor
제이. 토빈 필립
Original Assignee
빈센트 제이. 라우너
모터로라 인코오포레이티드
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Family has litigation
First worldwide family litigation filed litigation Critical https://patents.darts-ip.com/?family=23990700&utm_source=google_patent&utm_medium=platform_link&utm_campaign=public_patent_search&patent=KR850002168(A) "Global patent litigation dataset” by Darts-ip is licensed under a Creative Commons Attribution 4.0 International License.
Application filed by 빈센트 제이. 라우너, 모터로라 인코오포레이티드 filed Critical 빈센트 제이. 라우너
Publication of KR850002168A publication Critical patent/KR850002168A/ko
Application granted granted Critical
Publication of KR900005782B1 publication Critical patent/KR900005782B1/ko

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/322—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections
    • H01L21/3221—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections of silicon bodies, e.g. for gettering
    • H01L21/3225—Thermally inducing defects using oxygen present in the silicon body for intrinsic gettering
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/023—Deep level dopants
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/024—Defect control-gettering and annealing

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
  • Formation Of Insulating Films (AREA)

Abstract

내용 없음

Description

반도체장치 및 노출층을 이용한 제조공정
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도 및 제2도는 본 발명에 따른 노출공정을 도시함, 제3도는 본 발명에 따라 마련된 실리콘 웨이퍼의 단면도.

Claims (9)

  1. 결합된 산소농도를 갖는 실리콘 웨이퍼를 제공하는 단계와, 상기 웨이퍼 표면의 산소 침전물을 실질적으로 제거하는 동안 환원분위기에서 상승온도로 상기 웨이퍼를 가열시키는 단계로 구성되는 것을 특징으로 하는 실리콘 웨이퍼의 표면층을 노출시키는 공정.
  2. 제1항에 있어서, 상기 환원분위기는 수소를 포함하는 것을 특징으로 하는 공정.
  3. 제2항에 있어서, 상기 환원분위기는 아르곤 또는 헬륨으로 희석된 수소를 포함하는 것을 특징으로 하는 공정.
  4. 약 1.3×1018cm-3결합농도 보다 짙은 산소농도를 갖는 실리콘웨이퍼를 제공하는 단계와, 상기 웨이퍼 표면에 노출층을 생성하기 위해 환원분위기에서 약 1000-12000℃의 온도로 상기 웨이퍼를 가열시키는 단계와, 환원분위기에서 상기 웨이퍼를 냉각시키는 단계로 구성되는 것을 특징으로 한 실리콘 웨이퍼의 표면층을 노출시키는 공정.
  5. 제4항에 있어서, 환원분위기가 수소 또는 아르곤과 혼합된 수소를 구비한 것을 특징으로 하는 공정.
  6. 결합된 산소 농도를 갖는 실리콘 기판을 제공하는 단계와, 환원분위기에서 제1상승온도로 상기 기판을 가열하는 단계와, 제1상승온도보다 낮은 제2상승온도로 상기 기판의 온도를 낮추는 단계와, 상기 웨이퍼의 벌크에서 산소침전물의 핵생성을 허락하는 시간동안 제2상승온도로 상기 기판을 유지시키는 단계로 구성된 것을 특징으로 하는 장치 제조용 실리콘 기판을 제공하는 공정.
  7. 고농도의 산소침전물의 벌크영역과 환원분위기에서 노출된 제1전도형 표면층을 포함한 실리콘 기판과, 상기 표면층의 두께보다 얇은 깊이로 상기 표면층에 형성된 제2전도형영역을 구비하는 것을 특징으로 한 반도체 장치.
  8. 산소가 결합된 제1전도형 실리콘 웨이퍼를 제공하는 단계와, 상기 웨이퍼에 노출표면층을 형성하도록 충분한 시간동안 환원 분위기에서 약 1000도 내지 1200도의 온도로 상기 웨이퍼를 가열시키고 그리고 상기 웨이퍼의 벌크에서 산소 침전물을 핵형성할 수 있는 600℃ 내지 800℃의 제2온도로 상기 웨이퍼의 온도를 낮추는 단계와, 상기 표면층의 두께보다 얇은 깊이로 상기 노출층에 제2전도형 영역을 형성하는 단계로 구성된 것을 특징으로 하는 반도체 장치 제조공정.
  9. 산소가 약 1.3×1018cm-3보다 짙은 농도로 결합된 실리콘웨이퍼를 제공하는 단계와, 제1상승온도로 상기 웨이퍼를 가열하는 단계와, 환원분위기에서 약 1-4시간동안 상기 제1상승온도로 가열냉각시키는 단계와 상기 제1상승온도 보다 낮은 제2온도로 상기 웨이퍼를 식히는 단계와, 상기 웨이퍼위에 산화물층을 형성하도록 산화분위기에서 상기 웨이퍼를 제2온도로 유지시키는 단계와, 상기 제2온도보다 낮은 제3온도로 상기 웨이퍼를 식히는 추가단계와, 미소침전물의 핵형성을 위해 충분한 시간동안 상기 웨이퍼를 제3온도로 유지시키는 단계로 구성된 것을 특징으로 한 반도체장치 제조용 실리콘 기판을 제공하는 공정.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019840003082A 1983-06-03 1984-06-02 실리콘 웨이퍼의 표면층 노출공정 및 그 표면층상에 형성된 반도체장치 KR900005782B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US500735 1983-06-03
US06/500,735 US4548654A (en) 1983-06-03 1983-06-03 Surface denuding of silicon wafer
US500,735 1983-06-03

Publications (2)

Publication Number Publication Date
KR850002168A true KR850002168A (ko) 1985-05-06
KR900005782B1 KR900005782B1 (ko) 1990-08-11

Family

ID=23990700

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019840003082A KR900005782B1 (ko) 1983-06-03 1984-06-02 실리콘 웨이퍼의 표면층 노출공정 및 그 표면층상에 형성된 반도체장치

Country Status (4)

Country Link
US (1) US4548654A (ko)
EP (1) EP0131717A3 (ko)
JP (1) JPH0680673B2 (ko)
KR (1) KR900005782B1 (ko)

Families Citing this family (69)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4666532A (en) * 1984-05-04 1987-05-19 Monsanto Company Denuding silicon substrates with oxygen and halogen
USH569H (en) 1984-09-28 1989-01-03 Motorola Inc. Charge storage depletion region discharge protection
US4659400A (en) * 1985-06-27 1987-04-21 General Instrument Corp. Method for forming high yield epitaxial wafers
FR2623332B1 (fr) * 1987-11-18 1994-09-23 Intersil Inc Circuit integre cmos et procede de fabrication
JP2666945B2 (ja) * 1988-02-08 1997-10-22 株式会社東芝 半導体装置の製造方法
US4868133A (en) * 1988-02-11 1989-09-19 Dns Electronic Materials, Inc. Semiconductor wafer fabrication with improved control of internal gettering sites using RTA
US4851358A (en) * 1988-02-11 1989-07-25 Dns Electronic Materials, Inc. Semiconductor wafer fabrication with improved control of internal gettering sites using rapid thermal annealing
JPH02224249A (ja) * 1988-11-29 1990-09-06 Nec Corp Ｓｉ基板の製造方法
DE68925879T2 (de) * 1988-12-21 1996-10-02 At & T Corp Thermisches Oxydierungsverfahren mit verändertem Wachstum für dünne Oxide
JPH02177541A (ja) * 1988-12-28 1990-07-10 Toshiba Ceramics Co Ltd シリコンウェハ及びシリコンウェハの熱処理方法
JPH02263792A (ja) * 1989-03-31 1990-10-26 Shin Etsu Handotai Co Ltd シリコンの熱処理方法
JP2671494B2 (ja) * 1989-05-16 1997-10-29 富士通株式会社 ゲッタリング方法
US5066359A (en) * 1990-09-04 1991-11-19 Motorola, Inc. Method for producing semiconductor devices having bulk defects therein
IT1242014B (it) * 1990-11-15 1994-02-02 Memc Electronic Materials Procedimento per il trattamento di fette di silicio per ottenere in esse profili di precipitazione controllati per la produzione di componenti elettronici.
JP2613498B2 (ja) * 1991-03-15 1997-05-28 信越半導体株式会社 Ｓｉ単結晶ウエーハの熱処理方法
JP2535701B2 (ja) * 1992-03-27 1996-09-18 株式会社東芝 半導体装置
CA2064486C (en) * 1992-03-31 2001-08-21 Alain Comeau Method of preparing semiconductor wafer with good intrinsic gettering
JP2560178B2 (ja) * 1992-06-29 1996-12-04 九州電子金属株式会社 半導体ウェーハの製造方法
JPH0684925A (ja) * 1992-07-17 1994-03-25 Toshiba Corp 半導体基板およびその処理方法
KR0139730B1 (ko) * 1993-02-23 1998-06-01 사또오 후미오 반도체 기판 및 그 제조방법
US5401669A (en) * 1993-05-13 1995-03-28 Memc Electronic Materials, Spa Process for the preparation of silicon wafers having controlled distribution of oxygen precipitate nucleation centers
JPH0786289A (ja) * 1993-07-22 1995-03-31 Toshiba Corp 半導体シリコンウェハおよびその製造方法
US5352615A (en) * 1994-01-24 1994-10-04 Motorola, Inc. Denuding a semiconductor substrate
US5445975A (en) * 1994-03-07 1995-08-29 Advanced Micro Devices, Inc. Semiconductor wafer with enhanced pre-process denudation and process-induced gettering
JPH07247197A (ja) * 1994-03-09 1995-09-26 Fujitsu Ltd 半導体装置とその製造方法
JP2874834B2 (ja) * 1994-07-29 1999-03-24 三菱マテリアル株式会社 シリコンウェーハのイントリンシックゲッタリング処理法
JPH08130214A (ja) * 1994-09-07 1996-05-21 Seiko Instr Inc 半導体装置およびその製造方法
US5478762A (en) * 1995-03-16 1995-12-26 Taiwan Semiconductor Manufacturing Company Method for producing patterning alignment marks in oxide
TW319916B (ko) * 1995-06-05 1997-11-11 Hewlett Packard Co
US6004868A (en) * 1996-01-17 1999-12-21 Micron Technology, Inc. Method for CMOS well drive in a non-inert ambient
AU3628297A (en) * 1996-09-30 1998-04-24 Symbios, Inc. Semiconductor fabrication
JP2973960B2 (ja) * 1997-01-29 1999-11-08 日本電気株式会社 半導体装置の製造方法
US5994761A (en) 1997-02-26 1999-11-30 Memc Electronic Materials Spa Ideal oxygen precipitating silicon wafers and oxygen out-diffusion-less process therefor
WO1998042010A1 (en) * 1997-03-17 1998-09-24 Genus, Inc. Bonded soi wafers using high energy implant
US6190631B1 (en) * 1997-04-09 2001-02-20 Memc Electronic Materials, Inc. Low defect density, ideal oxygen precipitating silicon
US5882989A (en) * 1997-09-22 1999-03-16 Memc Electronic Materials, Inc. Process for the preparation of silicon wafers having a controlled distribution of oxygen precipitate nucleation centers
US6828690B1 (en) * 1998-08-05 2004-12-07 Memc Electronic Materials, Inc. Non-uniform minority carrier lifetime distributions in high performance silicon power devices
WO2000013209A2 (en) * 1998-09-02 2000-03-09 Memc Electronic Materials, Inc. Thermally annealed silicon wafers having improved intrinsic gettering
EP1624482B1 (en) * 1998-09-02 2009-07-29 MEMC Electronic Materials, Inc. Thermally annealed silicon wafers having improved intrinsic gettering
WO2000013226A1 (en) 1998-09-02 2000-03-09 Memc Electronic Materials, Inc. Process for preparing an ideal oxygen precipitating silicon wafer
EP1114454A2 (en) * 1998-09-02 2001-07-11 MEMC Electronic Materials, Inc. Silicon on insulator structure from low defect density single crystal silicon
US6336968B1 (en) 1998-09-02 2002-01-08 Memc Electronic Materials, Inc. Non-oxygen precipitating czochralski silicon wafers
CN1296526C (zh) * 1998-10-14 2007-01-24 Memc电子材料有限公司 热退火后的低缺陷密度单晶硅
JP2000154070A (ja) * 1998-11-16 2000-06-06 Suminoe Textile Co Ltd セラミックス三次元構造体及びその製造方法
US6284384B1 (en) * 1998-12-09 2001-09-04 Memc Electronic Materials, Inc. Epitaxial silicon wafer with intrinsic gettering
JP2000294549A (ja) * 1999-02-02 2000-10-20 Nec Corp 半導体装置及びその製造方法
JP2000277404A (ja) * 1999-03-26 2000-10-06 Mitsubishi Materials Silicon Corp シリコンウェーハ
US20030051656A1 (en) 1999-06-14 2003-03-20 Charles Chiun-Chieh Yang Method for the preparation of an epitaxial silicon wafer with intrinsic gettering
US6635587B1 (en) 1999-09-23 2003-10-21 Memc Electronic Materials, Inc. Method for producing czochralski silicon free of agglomerated self-interstitial defects
US6376395B2 (en) * 2000-01-11 2002-04-23 Memc Electronic Materials, Inc. Semiconductor wafer manufacturing process
CN1161516C (zh) 2000-02-17 2004-08-11 积水树脂株式会社 道路标线装置及其所用的自发光标线系统
KR20030021185A (ko) * 2000-06-30 2003-03-12 엠이엠씨 일렉트로닉 머티리얼즈 인코포레이티드 디누디드 존을 갖는 실리콘 웨이퍼를 형성하는 방법 및 장치
US6339016B1 (en) 2000-06-30 2002-01-15 Memc Electronic Materials, Inc. Method and apparatus for forming an epitaxial silicon wafer with a denuded zone
US6599815B1 (en) 2000-06-30 2003-07-29 Memc Electronic Materials, Inc. Method and apparatus for forming a silicon wafer with a denuded zone
JP4822582B2 (ja) * 2000-12-22 2011-11-24 Ｓｕｍｃｏ Ｔｅｃｈｘｉｖ株式会社 ボロンドープされたシリコンウエハの熱処理方法
WO2002084728A1 (en) * 2001-04-11 2002-10-24 Memc Electronic Materials, Inc. Control of thermal donor formation in high resistivity cz silicon
TW541581B (en) * 2001-04-20 2003-07-11 Memc Electronic Materials Method for the preparation of a semiconductor substrate with a non-uniform distribution of stabilized oxygen precipitates
US20040259321A1 (en) * 2003-06-19 2004-12-23 Mehran Aminzadeh Reducing processing induced stress
JP4617751B2 (ja) * 2004-07-22 2011-01-26 株式会社Ｓｕｍｃｏ シリコンウェーハおよびその製造方法
US7485928B2 (en) * 2005-11-09 2009-02-03 Memc Electronic Materials, Inc. Arsenic and phosphorus doped silicon wafer substrates having intrinsic gettering
US20090004426A1 (en) * 2007-06-29 2009-01-01 Memc Electronic Materials, Inc. Suppression of Oxygen Precipitation in Heavily Doped Single Crystal Silicon Substrates
US20090004458A1 (en) * 2007-06-29 2009-01-01 Memc Electronic Materials, Inc. Diffusion Control in Heavily Doped Substrates
US7858501B2 (en) * 2007-08-23 2010-12-28 Infineon Technologies Austria Ag Semiconductor wafer for semiconductor components and production method
US8378384B2 (en) * 2007-09-28 2013-02-19 Infineon Technologies Ag Wafer and method for producing a wafer
JP5984448B2 (ja) * 2012-03-26 2016-09-06 グローバルウェーハズ・ジャパン株式会社 シリコンウェーハ
JP2013206981A (ja) * 2012-03-27 2013-10-07 Globalwafers Japan Co Ltd シリコンウェーハ
GB2574879B (en) * 2018-06-22 2022-12-28 X Fab Semiconductor Foundries Gmbh Substrates for III-nitride epitaxy
AU2020328504A1 (en) 2019-08-09 2022-02-17 Leading Edge Equipment Technologies, Inc. Producing a ribbon or wafer with regions of low oxygen concentration
US20220325438A1 (en) * 2019-08-09 2022-10-13 Leading Edge Equipment Technologies, Inc. Wafer with regions of low oxygen concentration

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5297666A (en) * 1976-02-12 1977-08-16 Hitachi Ltd Production of semiconductor device containing pn junctions
US4154873A (en) * 1977-11-10 1979-05-15 Burr-Brown Research Corporation Method of increasing field inversion threshold voltage and reducing leakage current and electrical noise in semiconductor devices
US4153486A (en) * 1978-06-05 1979-05-08 International Business Machines Corporation Silicon tetrachloride epitaxial process for producing very sharp autodoping profiles and very low defect densities on substrates with high concentration buried impurity layers utilizing a preheating in hydrogen
FR2435818A1 (fr) * 1978-09-08 1980-04-04 Ibm France Procede pour accroitre l'effet de piegeage interne des corps semi-conducteurs
JPS583375B2 (ja) * 1979-01-19 1983-01-21 超エル・エス・アイ技術研究組合 シリコン単結晶ウエハ−の製造方法
JPS5680139A (en) * 1979-12-05 1981-07-01 Chiyou Lsi Gijutsu Kenkyu Kumiai Manufacture of semiconductor device
GB2080780B (en) * 1980-07-18 1983-06-29 Secr Defence Heat treatment of silicon slices
US4364779A (en) * 1980-08-04 1982-12-21 Bell Telephone Laboratories, Incorporated Fabrication of semiconductor devices including double annealing steps for radiation hardening
DE3280219D1 (de) * 1981-03-11 1990-08-30 Fujitsu Ltd Verfahren zur herstellung einer halbleiteranordnung mit ausgluehen eines halbleiterkoerpers.
JPS57197827A (en) * 1981-05-29 1982-12-04 Hitachi Ltd Semiconductor substrate
US4437922A (en) * 1982-03-26 1984-03-20 International Business Machines Corporation Method for tailoring oxygen precipitate particle density and distribution silicon wafers
EP0093848A3 (en) * 1982-05-12 1986-03-26 International Business Machines Corporation Semiconductor device fabrication process utilizing an added annealing step
JPS59202640A (ja) * 1983-05-02 1984-11-16 Toshiba Corp 半導体ウエハの処理方法

Also Published As

Publication number Publication date
EP0131717A3 (en) 1986-07-23
KR900005782B1 (ko) 1990-08-11
US4548654A (en) 1985-10-22
EP0131717A2 (en) 1985-01-23
JPS603130A (ja) 1985-01-09
JPH0680673B2 (ja) 1994-10-12

Similar Documents

Publication Publication Date Title
KR850002168A (ko) 반도체장치 및 노출층을 이용한 제조공정
US3386865A (en) Process of making planar semiconductor devices isolated by encapsulating oxide filled channels
JPS64768A (en) Manufacture of semiconductor element
US3617398A (en) A process for fabricating semiconductor devices having compensated barrier zones between np-junctions
KR920005271A (ko) 반도체장치의 제조방법
KR900007051A (ko) 반도체장치의 제조방법
US3783050A (en) Method of making semiconductor device using polycrystal thin film for impurity diffusion
US3541676A (en) Method of forming field-effect transistors utilizing doped insulators as activator source
Lane Stress at the Si—SiO 2 interface and its relationship to interface states
KR850005139A (ko) 반도체 장치의 제조방법
EP0322921A3 (en) Method of forming shallow junction and semiconductor device having said shallow junction
KR880013232A (ko) 반도체장치 및 그 제조방법
KR840008210A (ko) 집적회로의 반도체기판 물질에 관한 게터링(Gettering) 공법
JPS5795625A (en) Manufacture of semiconductor device
FR2131406A5 (ko)
US3718503A (en) Method of forming a diffusion mask barrier on a silicon substrate
KR880011888A (ko) 반도체장치의 제조방법
JPS52147992A (en) Manufacture of semiconductor device
JPS56155547A (en) Semiconductor device
Gottlieb et al. The epitaxial deposition of silicon on insulating substrates for MOS circuitry
KR830008393A (ko) 반도체기판의 제조방법
JPS5742146A (en) Manufacture of semiconductor device
KR880003418A (ko) 반도체 웨이퍼의 불순물 확산방법
JPS56133869A (en) Mos type semiconductor device and manufacture thereof
KR880009444A (ko) 반도체 장치의 제조방법

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
G160 Decision to publish patent application
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20030711

Year of fee payment: 14

EXPY Expiration of term