KR840008210A - 집적회로의 반도체기판 물질에 관한 게터링(Gettering) 공법 - Google Patents

집적회로의 반도체기판 물질에 관한 게터링(Gettering) 공법 Download PDF

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KR840008210A
KR840008210A KR1019840000672A KR840000672A KR840008210A KR 840008210 A KR840008210 A KR 840008210A KR 1019840000672 A KR1019840000672 A KR 1019840000672A KR 840000672 A KR840000672 A KR 840000672A KR 840008210 A KR840008210 A KR 840008210A
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substrate
mentioned
thickness
silicon
doped
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KR1019840000672A
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KR870000315B1 (ko
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유진 힐 데일
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아놀드 하베이 콜
몬산토 캄파니
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/322—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/322—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections
    • H01L21/3221—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections of silicon bodies, e.g. for gettering
    • H01L21/3225—Thermally inducing defects using oxygen present in the silicon body for intrinsic gettering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02381—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/322—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections
    • H01L21/3221—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections of silicon bodies, e.g. for gettering

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
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  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Formation Of Insulating Films (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

내용 없음.

Description

집적회로의 반도체기판 물질에 관한 게터링(Guttering)공법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음

Claims (20)

  1. 다바이스영역으로부터 배면에 0.05-5.0μ두께의 폴리실리콘층을 가지는 반도체물질로 구성된 활성디바이스 영역으로 부터 떨어진 영역에서 전자 디바이스에 유해한 결함, 오염물질, 불순물을 게터링하는 능력을 가진 반도체기판.
  2. 제1항의 기판에 있어서, 언급한 폴리실리콘층의 두께는 0.2-2.0μ로 한 것.
  3. 제1항의 기판에 있어서, 언급한 층은 산소로 도프된 것.
  4. 제1항의 기판에 있어서, 언급한 층은 질소로 도프된 것.
  5. 제1항의 기판에 있어서, 도프된 원소는 언급한층에 언급한층의 약 0.1-40wt% 존재하도록 한 것.
  6. 제1항의 기판에 있어서, 도프된 원소는 언급한층에 언급한층의 약 2-20wt% 존재하도록 한 것.
  7. 제1항의 기판에 있어서, 반도체물질은 실리콘으로 한 것.
  8. 제1항의 기판에 있어서, 언급한 폴리실콘용은 실리콘함유물질의 화학적 증기 적층(CVD)에 의해서 언급한 반도체 물질로 사용한다는 것.
  9. 제8항의 기판에 있어서 언급한 실리콘함유물질은 실란(silane)으로 한 것.
  10. 제8항의 기판에 있어서, 도프된 물질로 존재시키는 것.
  11. 제10항의 기판에 있어서, 언급한 실리콘함유물질은 실란이고 언급한 도펜트물질은 산소산화물로 하는 것.
  12. 일면은 거울과 같은 표면과 다른면은 0.5-5.0μ 두께의 폴리실콘층으로된 실리콘웨이퍼로 구성된 활성디바이스 영역으로부터 떨어진 영역에서의 전자디바이스에 유해한 결함, 오염물질, 불순물을 게터링하는 능력을 가진 반도체기판.
  13. 제12항의 기판에 있어서 언급한 폴리실콘은 산소를 0.1-40wt% 함유한 것.
  14. 제12항의 기판에 있어서 언급한층의 두께는 0.6-1.0μ로 한 것.
  15. 배면 폴리실콘층의 두께가 0.05-5.0μ인 반도체 물질로 구성된 기판의 일면에 디바이스를 형성시키는 열적공정조건을 사용하는 전자 디바이스의 제조공정.
  16. 제15항의 공정에 있어서 언급한 두께는 0.2-2.0μ으로한 것.
  17. 제15항의 공정에 있어서 언급한 반도 체물질은 실리콘으로 한 것.
  18. 제15항의 공정에 있어서 언급한출은 산소가 0.1-40wt%로 도프되도록 한 것.
  19. 이면의 두께가 0.5-5.0μ인 폴리실콘층으로된 실리콘웨이퍼의 일표면이나 표면가까이에서 열적조건에 의하여 디바이스를 형성시키는 전자디바이스의 제조방법.
  20. 제19항의 공정에 있어서 언급한 폴리실콘의 산소 함량은 0.1-40wt%으로 한 것.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019840000672A 1983-02-14 1984-02-13 반도체 기판재료 및 전자디바이스의 제조방법 KR870000315B1 (ko)

Applications Claiming Priority (6)

Application Number Priority Date Filing Date Title
US46624983A 1983-02-14 1983-02-14
US466249 1983-02-14
US48159783A 1983-04-04 1983-04-04
US481597 1983-04-04
US481,597 1983-04-04
US466,249 1990-01-17

Publications (2)

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KR840008210A true KR840008210A (ko) 1984-12-13
KR870000315B1 KR870000315B1 (ko) 1987-02-26

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EP (1) EP0120830B1 (ko)
KR (1) KR870000315B1 (ko)
DE (1) DE3485808T2 (ko)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0162830A1 (en) * 1984-04-19 1985-11-27 Monsanto Company Improved semiconductor substrates
IT1230028B (it) * 1988-12-16 1991-09-24 Sgs Thomson Microelectronics Procedimento di fabbricazione di dispositivi semiconduttori mos avvalentesi di un trattamento "gettering" di migliorare caratteristiche, e dispositivi semiconduttori mos con esso ottenuti
JPH05275436A (ja) * 1992-03-24 1993-10-22 Shin Etsu Handotai Co Ltd シリコンウエーハの熱処理方法
JP3491463B2 (ja) * 1996-08-19 2004-01-26 信越半導体株式会社 シリコン鏡面ウェーハの製造方法およびシリコンウェーハの加工装置
JP3454033B2 (ja) * 1996-08-19 2003-10-06 信越半導体株式会社 シリコンウェーハおよびその製造方法
US6689668B1 (en) * 2000-08-31 2004-02-10 Samsung Austin Semiconductor, L.P. Methods to improve density and uniformity of hemispherical grain silicon layers
JP2006073580A (ja) * 2004-08-31 2006-03-16 Sumco Corp シリコンエピタキシャルウェーハ及びその製造方法
CN113178388B (zh) * 2021-03-31 2023-04-21 青岛惠科微电子有限公司 耐高压芯片的制造方法和耐高压芯片

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4053335A (en) * 1976-04-02 1977-10-11 International Business Machines Corporation Method of gettering using backside polycrystalline silicon

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DE3485808T2 (de) 1993-03-04
DE3485808D1 (de) 1992-08-20
KR870000315B1 (ko) 1987-02-26
EP0120830A3 (en) 1986-07-23
EP0120830A2 (en) 1984-10-03
EP0120830B1 (en) 1992-07-15

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