KR920001620A - 반도체장치 및 그의 제조방법 - Google Patents
반도체장치 및 그의 제조방법 Download PDFInfo
- Publication number
- KR920001620A KR920001620A KR1019910005741A KR910005741A KR920001620A KR 920001620 A KR920001620 A KR 920001620A KR 1019910005741 A KR1019910005741 A KR 1019910005741A KR 910005741 A KR910005741 A KR 910005741A KR 920001620 A KR920001620 A KR 920001620A
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- South Korea
- Prior art keywords
- semiconductor device
- manufacturing
- plasma
- chemical vapor
- insulating film
- Prior art date
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- 239000004065 semiconductor Substances 0.000 title claims description 10
- 238000004519 manufacturing process Methods 0.000 title claims description 4
- 230000001681 protective effect Effects 0.000 claims description 4
- 239000000126 substance Substances 0.000 claims description 3
- 230000008021 deposition Effects 0.000 claims description 2
- 238000000034 method Methods 0.000 claims 3
- 150000004767 nitrides Chemical class 0.000 claims 2
- 239000000758 substrate Substances 0.000 claims 2
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 claims 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims 1
- 239000002253 acid Substances 0.000 claims 1
- 238000005229 chemical vapour deposition Methods 0.000 claims 1
- 238000000151 deposition Methods 0.000 claims 1
- 238000005121 nitriding Methods 0.000 claims 1
- 150000001282 organosilanes Chemical class 0.000 claims 1
- 229910000077 silane Inorganic materials 0.000 claims 1
- 229910052710 silicon Inorganic materials 0.000 claims 1
- 239000010703 silicon Substances 0.000 claims 1
- 229910052814 silicon oxide Inorganic materials 0.000 claims 1
- -1 silicon oxide nitride Chemical class 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 1
Classifications
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- H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
- H01L21/0214—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being a silicon oxynitride, e.g. SiON or SiON:H
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
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- Power Engineering (AREA)
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Ceramic Engineering (AREA)
- Plasma & Fusion (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Formation Of Insulating Films (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Chemical Vapour Deposition (AREA)
- Local Oxidation Of Silicon (AREA)
Abstract
내용 없음
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 이 발명의 1실시예에 관한 반도체장치의 단면도,
제2A~제2F도는 제1도에 표시하는 반도체장치의 제조공정의 단면도,
제3도는 보호절연막의 퇴적에 사용되는 화학기상 성장장치의 개략도.
Claims (2)
- 소자가 수분·응력등의 외부환경에 의해 변화를 일으키지 않도록 하기 위해 소자표면부에 보호절연막이 피복되어 되는 반도체장치에 있어, 상기 소자가 형성된 반도체 기판과, 당해 반도체장치의 최상층부에 설치되어 상기 소자와 전기접속되는 배선패턴과, 상기 배선패턴을 피복하도록 상기 반도체 기판상에 퇴적된 실리콘산 질화막을 비치하고, 상기 실리콘산 질화막은, 유기실란과 질화성 가스를 포함하는 가스를 사용하여 플라즈마를 이용한 화학기상 성장법으로 퇴적되어 있는 반도체장치.
- 소자가 수분·응력등의 외부환경에 의해 변화를 일으키지 않도록 하기 위해 소자표면부에 보호절연막이 피복되어 있는 반도체장치의 제조방법에 있어서, 상기보호절연막을 유기실란과 질화성 가스를 포함하는 혼합가스를 사용하여 플라즈마를 이용한 화학기상 성장법 혼합가스를 사용하여 플라즈마를 이용한 화학기상 성장법으로 퇴적하는 것을 특징으로 하는 반도체장치의 제조방법.※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP90-148185 | 1990-06-05 | ||
JP2-148185 | 1990-06-05 | ||
JP2148185A JP2814009B2 (ja) | 1990-06-05 | 1990-06-05 | 半導体装置の製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
KR920001620A true KR920001620A (ko) | 1992-01-30 |
KR940008373B1 KR940008373B1 (ko) | 1994-09-12 |
Family
ID=15447146
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019910005741A KR940008373B1 (ko) | 1990-06-05 | 1991-04-10 | 반도체 장치의 제조방법 |
Country Status (4)
Country | Link |
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US (2) | US5260600A (ko) |
JP (1) | JP2814009B2 (ko) |
KR (1) | KR940008373B1 (ko) |
DE (1) | DE4118165C2 (ko) |
Families Citing this family (34)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH04162428A (ja) * | 1990-10-24 | 1992-06-05 | Nec Corp | 半導体装置の製造方法 |
US5356722A (en) * | 1992-06-10 | 1994-10-18 | Applied Materials, Inc. | Method for depositing ozone/TEOS silicon oxide films of reduced surface sensitivity |
US5825078A (en) * | 1992-09-23 | 1998-10-20 | Dow Corning Corporation | Hermetic protection for integrated circuits |
US5438022A (en) | 1993-12-14 | 1995-08-01 | At&T Global Information Solutions Company | Method for using low dielectric constant material in integrated circuit fabrication |
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-
1990
- 1990-06-05 JP JP2148185A patent/JP2814009B2/ja not_active Expired - Fee Related
-
1991
- 1991-04-10 KR KR1019910005741A patent/KR940008373B1/ko not_active IP Right Cessation
- 1991-05-23 US US07/704,422 patent/US5260600A/en not_active Expired - Lifetime
- 1991-06-03 DE DE4118165A patent/DE4118165C2/de not_active Expired - Fee Related
-
1993
- 1993-05-24 US US08/065,305 patent/US5362686A/en not_active Expired - Lifetime
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US5362686A (en) | 1994-11-08 |
US5260600A (en) | 1993-11-09 |
DE4118165A1 (de) | 1991-12-12 |
JP2814009B2 (ja) | 1998-10-22 |
JPH0439934A (ja) | 1992-02-10 |
KR940008373B1 (ko) | 1994-09-12 |
DE4118165C2 (de) | 1996-05-23 |
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