KR950021138A - 반도체 장치의 제조 방법 - Google Patents

반도체 장치의 제조 방법 Download PDF

Info

Publication number
KR950021138A
KR950021138A KR1019940034638A KR19940034638A KR950021138A KR 950021138 A KR950021138 A KR 950021138A KR 1019940034638 A KR1019940034638 A KR 1019940034638A KR 19940034638 A KR19940034638 A KR 19940034638A KR 950021138 A KR950021138 A KR 950021138A
Authority
KR
South Korea
Prior art keywords
gas
semiconductor device
manufacturing
sih
film
Prior art date
Application number
KR1019940034638A
Other languages
English (en)
Inventor
고이찌 안도
Original Assignee
가네꼬 히사시
닛본덴기 가부시끼가이샤
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 가네꼬 히사시, 닛본덴기 가부시끼가이샤 filed Critical 가네꼬 히사시
Publication of KR950021138A publication Critical patent/KR950021138A/ko

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/314—Inorganic layers
    • H01L21/318—Inorganic layers composed of nitrides
    • H01L21/3185—Inorganic layers composed of nitrides of siliconnitrides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/014—Capacitor
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/017—Clean surfaces
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/112—Nitridation, direct, of silicon
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/913—Diverse treatments performed in unitary chamber
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/974—Substrate surface preparation

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Drying Of Semiconductors (AREA)
  • Semiconductor Memories (AREA)
  • Formation Of Insulating Films (AREA)
  • Chemical Vapour Deposition (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

반도체 장치를 제조하는 방법은 캐패시터를 형성하는 단계를 포함한다. 이 단계는 반도체 기판상의 선정된 절연막의 표면을 선택적으로 덮는 다결정 실리콘막으로 구성된 하부 전극을 형성하는 단계, 및 SiH4가스를 함유하는 분위기중에서 가열을 수행하여 하부 전극의 표면상에 자연산화막을 제거하고, 이어서 산소 분위기에 노출하지 않고 질화실리콘막의 형성을 수행하는 단계를 포함한다.

Description

반도체 장치의 제조 방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제2A도 내지 제2E도는 본 발명의 실시예를 나타내기 위해 제조 단계를 도시한 단면도.

Claims (10)

  1. 반도체 기판상의 선정된 절연막의 표면을 선택적으로 덮는 다결정 실리콘막으로 구성된 하부 전극을 형성하는 단계, 및 SiH4가스를 함유하는 분위기중에서 가열을 수행하여 상기 하부 전극의 표면상에서 자연산화막을 제거하고, 이어서 산소 분위기중에서 노출하지 않고 질화실리콘막의 형성을 수행하는 단계를 포함하는 캐패시터를 형성하는 단계를 포함하는 것을 특징으로 하는 반도체 장치의 제조 방법.
  2. 제1항에 있어서, 상기 자연산화막의 제거 및 상기 질화실리콘막의 형성이 동일 반응로내에서 순차적으로 수행되는 것을 특징으로 하는 반도체 장치의 제조 방법.
  3. 제1항에 있어서, 상기 질화실리콘막은 SiH4가스와 NH3가스를 혼합한 가스를 사용하여 형성되는 것을 특징으로 하는 반도체 장치의 제조 방법.
  4. 제2항에 있어서, 상기 질화실리콘막은 SiH4가스와 NH3가스를 혼합한 가스를 사용하여 형성되는 것을 특징으로 하는 반도체 장치의 제조 방법.
  5. 제1항에 있어서, 상기 자연산화막의 제거는 SiH4가스와 H2가스를 함유하는 분위기중에서 수행되는 것을 특징으로 하는 반도체 장치의 제조 방법.
  6. 제2항에 있어서, 상기 자연산화막의 제거는 SiH4가스와 H2가스를 함유하는 분위기중에서 수행되는 것을 특징으로 하는 반도체 장치의 제조 방법.
  7. 제1항에 있어서, 상기 자연산화막의 제거는 SiH4가스가 분당 1ml공급되고, 실리콘 기판이 0.13Pa 이하의 압력에서 800℃ 이하의 온도로 가열되는 조건하에서 수행되는 것을 특징으로 하는 반도체 장치의 제조 방법.
  8. 제4항에 있어서, 상기 질화실리콘막의 형성은 NH3가스가 분당 1ℓ로 공급되고, SiH4가스가 분당 20ml로공급되며, 실리콘 기판이 133 내지 1330Pa의 압력에서 700 내지 800℃의 온도로 가열되는 조건하에서 수행되는 것을 특징으로 하는 반도체 장치의 제조 방법.
  9. 제5항에 있어서, 상기 H2가스는 133 내지 1330Pa의 압력에서 분당 10ℓ로 공급되는 것을 특징으로 하는 반도체 장치의 제조 방법.
  10. 제6항에 있어서, 상기 H2가스는 133 내지 1330Pa의 압력에서 분당 10ℓ로 공급되는 것을 특징으로 하는 반도체 장치의 제조 방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019940034638A 1993-12-17 1994-12-16 반도체 장치의 제조 방법 KR950021138A (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP93-318621 1993-12-17
JP5318621A JPH07176627A (ja) 1993-12-17 1993-12-17 半導体装置の製造方法

Publications (1)

Publication Number Publication Date
KR950021138A true KR950021138A (ko) 1995-07-26

Family

ID=18101185

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019940034638A KR950021138A (ko) 1993-12-17 1994-12-16 반도체 장치의 제조 방법

Country Status (3)

Country Link
US (1) US5492854A (ko)
JP (1) JPH07176627A (ko)
KR (1) KR950021138A (ko)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2871580B2 (ja) * 1996-03-29 1999-03-17 日本電気株式会社 半導体装置の製造方法
US6027970A (en) 1996-05-17 2000-02-22 Micron Technology, Inc. Method of increasing capacitance of memory cells incorporating hemispherical grained silicon
US5670431A (en) * 1996-06-13 1997-09-23 Taiwan Semiconductor Manufacturing Company Ltd. Method of forming an ultra thin dielectric film for a capacitor
US5843830A (en) * 1996-06-26 1998-12-01 Micron Technology, Inc. Capacitor, and methods for forming a capacitor
US5849624A (en) * 1996-07-30 1998-12-15 Mircon Technology, Inc. Method of fabricating a bottom electrode with rounded corners for an integrated memory cell capacitor
US6528436B1 (en) 1996-10-21 2003-03-04 Micron Technology. Inc. Method of forming silicon nitride layer directly on HSG polysilicon
US6893980B1 (en) 1996-12-03 2005-05-17 Kabushiki Kaisha Toshiba Semiconductor device and manufacturing method therefor
US6749687B1 (en) 1998-01-09 2004-06-15 Asm America, Inc. In situ growth of oxide and silicon layers
US6130132A (en) 1998-04-06 2000-10-10 Taiwan Semiconductor Manufacturing Company Clean process for manufacturing of split-gate flash memory device having floating gate electrode with sharp peak
US6465370B1 (en) * 1998-06-26 2002-10-15 Infineon Technologies Ag Low leakage, low capacitance isolation material
US6417041B1 (en) * 1999-03-26 2002-07-09 Advanced Micro Devices, Inc. Method for fabricating high permitivity dielectric stacks having low buffer oxide
US7022623B2 (en) * 1999-04-22 2006-04-04 Micron Technology, Inc. Method of fabricating a semiconductor device with a dielectric film using a wet oxidation with steam process
US6348420B1 (en) 1999-12-23 2002-02-19 Asm America, Inc. Situ dielectric stacks
US6365518B1 (en) * 2001-03-26 2002-04-02 Applied Materials, Inc. Method of processing a substrate in a processing chamber
DE10130936B4 (de) * 2001-06-27 2004-04-29 Infineon Technologies Ag Herstellungsverfahren für ein Halbleiterbauelement mittels Atomschichtabscheidung/ALD
US8039966B2 (en) * 2009-09-03 2011-10-18 International Business Machines Corporation Structures of and methods and tools for forming in-situ metallic/dielectric caps for interconnects

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4181751A (en) * 1978-05-24 1980-01-01 Hughes Aircraft Company Process for the preparation of low temperature silicon nitride films by photochemical vapor deposition
JPS55125635A (en) * 1979-03-23 1980-09-27 Hitachi Ltd Semiconductor device
US4277320A (en) * 1979-10-01 1981-07-07 Rockwell International Corporation Process for direct thermal nitridation of silicon semiconductor devices
US4855258A (en) * 1987-10-22 1989-08-08 Ncr Corporation Native oxide reduction for sealing nitride deposition
JPH02150029A (ja) * 1988-11-30 1990-06-08 Oki Electric Ind Co Ltd 絶縁膜形成方法及び絶縁膜形成装置
JPH02186632A (ja) * 1989-01-12 1990-07-20 Nec Corp 絶縁膜の製造方法
JPH02290050A (ja) * 1989-02-23 1990-11-29 Mitsubishi Electric Corp 半導体装置およびその製造方法
US5104694A (en) * 1989-04-21 1992-04-14 Nippon Telephone & Telegraph Corporation Selective chemical vapor deposition of a metallic film on the silicon surface
JP2874262B2 (ja) * 1990-03-20 1999-03-24 富士通株式会社 半導体装置の製造方法
US5089441A (en) * 1990-04-16 1992-02-18 Texas Instruments Incorporated Low-temperature in-situ dry cleaning process for semiconductor wafers
US5032545A (en) * 1990-10-30 1991-07-16 Micron Technology, Inc. Process for preventing a native oxide from forming on the surface of a semiconductor material and integrated circuit capacitors produced thereby
JP3079575B2 (ja) * 1990-12-20 2000-08-21 株式会社日立製作所 半導体装置の製造方法
JPH04348524A (ja) * 1991-05-27 1992-12-03 Nec Corp 半導体装置の製造方法
JPH05109981A (ja) * 1991-10-21 1993-04-30 Nec Corp 半導体装置の製造方法
JPH05121655A (ja) * 1991-10-25 1993-05-18 Nec Corp 半導体装置の製造方法
JPH05308064A (ja) * 1992-04-30 1993-11-19 Mitsubishi Electric Corp シリコン自然酸化膜の「その場」除去方法及びその装置
US5362632A (en) * 1994-02-08 1994-11-08 Micron Semiconductor, Inc. Barrier process for Ta2 O5 capacitor

Also Published As

Publication number Publication date
JPH07176627A (ja) 1995-07-14
US5492854A (en) 1996-02-20

Similar Documents

Publication Publication Date Title
KR950021138A (ko) 반도체 장치의 제조 방법
KR890011081A (ko) 집적회로 제조방법
KR900002316A (ko) 반도체장치의 제조방법
KR950034775A (ko) 반도체장치 및 그 제조방법
KR950021655A (ko) 반도체 장치 제조 방법
KR840007307A (ko) 반도체 장치의 제조방법
KR880005666A (ko) 선택적으로 산화된 실리콘 기판상에 에피택셜 실리콘 층과 다결정 실리콘 층을 동시에 성장시키는 증착방법
KR920007116A (ko) 내층 절연막 형성방법
KR950034506A (ko) 반도체 영역을 선택적으로 형성하는 방법
KR970067542A (ko) 반도체장치의 제조방법
KR920005271A (ko) 반도체장치의 제조방법
KR950007123A (ko) 메모리 커패시터를 구비한 반도체 장치의 제조 방법
KR940007970A (ko) 반도체 기판 처리 방법
KR960005852A (ko) 반도체장치의 제조방법
KR970003719A (ko) 반도체소자의 제조방법
KR970063565A (ko) 반도체 장치의 층간 절연막 형성 방법
KR960026374A (ko) 실리콘 기판 산화 방법
KR960005863A (ko) 반도체 소자의 질화막 형성방법
KR960026588A (ko) 반도체소자의 소자분리 방법
KR920000124A (ko) 반도체 기판 표면 처리 방법
KR960039190A (ko) 반도체 소자의 유전체막 형성방법
KR970052218A (ko) 반도체 소자의 폴리실리콘층 형성방법
KR880004549A (ko) 불순물을 함유하는 레지스트와 산소를 함유하는 플라즈마를 사용하는 불순물 도우핑 방법
KR930003327A (ko) 게이트 산화막 제조방법
KR960039194A (ko) 평탄화 절연막 형성방법

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
E601 Decision to refuse application