KR960039194A - 평탄화 절연막 형성방법 - Google Patents

평탄화 절연막 형성방법 Download PDF

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Publication number
KR960039194A
KR960039194A KR1019950008391A KR19950008391A KR960039194A KR 960039194 A KR960039194 A KR 960039194A KR 1019950008391 A KR1019950008391 A KR 1019950008391A KR 19950008391 A KR19950008391 A KR 19950008391A KR 960039194 A KR960039194 A KR 960039194A
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KR
South Korea
Prior art keywords
insulating film
planarization insulating
forming
film
planarization
Prior art date
Application number
KR1019950008391A
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English (en)
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KR100345663B1 (ko
Inventor
김천수
Original Assignee
김주용
현대전자산업 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by 김주용, 현대전자산업 주식회사 filed Critical 김주용
Priority to KR1019950008391A priority Critical patent/KR100345663B1/ko
Publication of KR960039194A publication Critical patent/KR960039194A/ko
Application granted granted Critical
Publication of KR100345663B1 publication Critical patent/KR100345663B1/ko

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/31051—Planarisation of the insulating layers
    • H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Formation Of Insulating Films (AREA)

Abstract

본 발명은 간단한 방법으로 좁은 지역으로 보이드 없이 채우고 평탄화 할 수 있느 평탄화 절연막 형성방법에 관한 것으로, 반도체 소자 제조공정중 소자간의 전기적 절연 및 평탄화를 위한 평탄화 절연막 형성방법에 있어서, 평탄화용 절연막으로 Si-OH 결합그룹으로 구성된 막을 형성하는 것을 특징으로 한다.

Description

평탄화 절연막 형성방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음

Claims (5)

  1. 반도체 소자 제조공정중 소자간의 전기적 절연 및 평탄화를 위한 평탄화 절연막 형성방법에 있어서, 평탄화용 절연막으로 Si-OH 결합그룹으로 구성된 막을 형성하는 것을 특징으로 하는 평탄화 절연막 형성방법.
  2. 제1항에 있어서, 상기 Si-OH 결합그룹으로 구성된 막은 SiH4와 H2O2를 혼합 사용하여 형성하는 것을 특징으로 하는 평탄화 절연막 형성방법.
  3. 제2항에 있어서, 상기 평탄화 절연막은 화학기상증착 챔버에서 형성되는 것을 특징으로 하는 평탄화 절연막 형성방법.
  4. 제3항에 있어서, 상기 화학기상증착 챔버 내부를 400 내지 600mTorr 저압, 0℃ 범위의 낮은 온도를 유지하면서 반응가스를 주입하는 것을 특징으로 하는 평탄화 절연막 형성방법.
  5. 제4항에 있어서, 상기 평탄화 절연막 형성후 N2분위기에서 400℃, 30분간 열처리하는 단계를 더 포함하여 이루어지는 것을 특징으로 하는 평탄화 절연막 형성방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019950008391A 1995-04-11 1995-04-11 반도체소자의층간절연막평탄화방법 KR100345663B1 (ko)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950008391A KR100345663B1 (ko) 1995-04-11 1995-04-11 반도체소자의층간절연막평탄화방법

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950008391A KR100345663B1 (ko) 1995-04-11 1995-04-11 반도체소자의층간절연막평탄화방법

Publications (2)

Publication Number Publication Date
KR960039194A true KR960039194A (ko) 1996-11-21
KR100345663B1 KR100345663B1 (ko) 2002-10-30

Family

ID=37488597

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019950008391A KR100345663B1 (ko) 1995-04-11 1995-04-11 반도체소자의층간절연막평탄화방법

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KR (1) KR100345663B1 (ko)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100309662B1 (ko) * 1997-06-26 2001-11-15 다니구찌 이찌로오, 기타오카 다카시 반도체장치및그제조방법

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20030095630A (ko) * 2002-06-12 2003-12-24 삼성전자주식회사 매립 특성이 우수한 실리콘 산화물 형성 방법

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1992012535A1 (en) * 1991-01-08 1992-07-23 Fujitsu Limited Process for forming silicon oxide film
JP2737478B2 (ja) * 1991-09-30 1998-04-08 日本電気株式会社 半導体装置の表面保護膜の形成方法
JPH05251572A (ja) * 1992-03-06 1993-09-28 Nec Corp 半導体装置およびその製造方法
US5874367A (en) * 1992-07-04 1999-02-23 Trikon Technologies Limited Method of treating a semi-conductor wafer

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100309662B1 (ko) * 1997-06-26 2001-11-15 다니구찌 이찌로오, 기타오카 다카시 반도체장치및그제조방법

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