KR970030452A - 산화막과 질화막으로 이루어진 충간절연막의 식각방법 - Google Patents

산화막과 질화막으로 이루어진 충간절연막의 식각방법 Download PDF

Info

Publication number
KR970030452A
KR970030452A KR1019950043738A KR19950043738A KR970030452A KR 970030452 A KR970030452 A KR 970030452A KR 1019950043738 A KR1019950043738 A KR 1019950043738A KR 19950043738 A KR19950043738 A KR 19950043738A KR 970030452 A KR970030452 A KR 970030452A
Authority
KR
South Korea
Prior art keywords
interlayer insulating
insulating film
film
etching
nitride
Prior art date
Application number
KR1019950043738A
Other languages
English (en)
Other versions
KR0171094B1 (ko
Inventor
안재영
Original Assignee
문정환
엘지반도체 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 문정환, 엘지반도체 주식회사 filed Critical 문정환
Priority to KR1019950043738A priority Critical patent/KR0171094B1/ko
Publication of KR970030452A publication Critical patent/KR970030452A/ko
Application granted granted Critical
Publication of KR0171094B1 publication Critical patent/KR0171094B1/ko

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105After-treatment
    • H01L21/311Etching the insulating layers by chemical or physical means
    • H01L21/31105Etching inorganic layers
    • H01L21/31111Etching inorganic layers by chemical means
    • H01L21/31116Etching inorganic layers by chemical means by dry-etching
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105After-treatment
    • H01L21/311Etching the insulating layers by chemical or physical means
    • H01L21/31127Etching organic layers
    • H01L21/31133Etching organic layers by chemical means
    • H01L21/31138Etching organic layers by chemical means by dry-etching
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105After-treatment
    • H01L21/311Etching the insulating layers by chemical or physical means
    • H01L21/31144Etching the insulating layers by chemical or physical means using masks

Landscapes

  • Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Chemical & Material Sciences (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • General Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Inorganic Chemistry (AREA)
  • Drying Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

본 발명은 실리콘기판상에 형성되고, 고밀도 플라즈마 장비의 챔버 내에서 진행되는 산화막과 질화막으로 이루어지는 층간절연막의 식각방법에 있어서, 층간절연막에서 질화막을 C2F6, 에 O2가스를 첨가한 반응가스로 식각시키는 단계와, 층간절연막에서 산화막을 C2F6, C3F8, C4F8중 하나 이상의 반응가스로 식각시키는 단계를 포함하여 이루어진다.

Description

산화막과 질화막으로 이루어진 충간절연막의 식각방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제2도는 본 발명에 의한 산화막과 질화막으로 이루어진 층간절연막의 식각 방법을 설명하기 위한 도면.

Claims (4)

  1. 실리콘기판상에 형성되고, 고밀도 플라즈마 장비의 챔버 내에서 진행되는 산화막과 질화막으로 이루어지는 층간절연막의 식각방법에 있어서, 상기 층간절연막에서 질화막을 C2F6, 에 O2가스를 첨가한 반응가스로 식각시키는 단계와, 상기 층간절연막에서 상기 산화막을 C2F6, C3F8, C4F8중 하나 이상의 반응가스로 식각시키는 단계를 포함하여 이루어지는 산화막과 질화막으로 이루어진 층간절연막의 식각방법.
  2. 제1항에 있어서, 상기 층간절연막에서 질화막을 식각시키는 상기 반응가스는 25∼30[sccm] 정도의 C2F6가스에 5[sccm] 정도의 O2가스를 첨가한 것임을 특징으로 하는 산화막과 질화막으로 이루어진 층간절연막의 식각방법.
  3. 제1항에 있어서, 상기 층간절연막에서 상기 실리콘기판과 접하면서 형성된 산화막을 식각시키는 상기 반응가스는 40∼50[sccm] 정도의 유량범위를 갖는 C2F6, C3F8, C4F8중 하나 이상인 것을 특징으로 하는 산화막과 질화막으로 이루어진 층간절연막의 식각방법.
  4. 제1항, 제2항 또는 제3항에 있어서, 상기 층간절연막에서 상기 질화막 또는 상기 산화막의 식각은 상기 챔버의 내부온도를 220℃에서 285℃의 범위로 변화시키면서 진행시키는 것을 특징으로 하는 산화막과 질화막으로 이루어진 층간절연막의 식각방법.
KR1019950043738A 1995-11-25 1995-11-25 산화막과 질화막으로 이루어진 층간절연막의 식각방법 KR0171094B1 (ko)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950043738A KR0171094B1 (ko) 1995-11-25 1995-11-25 산화막과 질화막으로 이루어진 층간절연막의 식각방법

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950043738A KR0171094B1 (ko) 1995-11-25 1995-11-25 산화막과 질화막으로 이루어진 층간절연막의 식각방법

Publications (2)

Publication Number Publication Date
KR970030452A true KR970030452A (ko) 1997-06-26
KR0171094B1 KR0171094B1 (ko) 1999-03-30

Family

ID=19435720

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019950043738A KR0171094B1 (ko) 1995-11-25 1995-11-25 산화막과 질화막으로 이루어진 층간절연막의 식각방법

Country Status (1)

Country Link
KR (1) KR0171094B1 (ko)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100296137B1 (ko) * 1998-06-16 2001-08-07 박종섭 보호막으로서고밀도플라즈마화학기상증착에의한절연막을갖는반도체소자제조방법

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101909110B1 (ko) * 2016-08-18 2018-10-18 피에스케이 주식회사 기판 처리 방법

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100296137B1 (ko) * 1998-06-16 2001-08-07 박종섭 보호막으로서고밀도플라즈마화학기상증착에의한절연막을갖는반도체소자제조방법

Also Published As

Publication number Publication date
KR0171094B1 (ko) 1999-03-30

Similar Documents

Publication Publication Date Title
KR970030652A (ko) 소자분리반도체기판 및 그 제조방법
WO2002054495A3 (en) Metal oxynitrides on monocrystalline substrates
KR960026671A (ko) 반도체장치의 제조방법
KR960036060A (ko) 반도체 장치의 고유전막/전극 및 그 제조방법
KR940006197A (ko) 반도체장치의 콘택부 형성방법
KR970030452A (ko) 산화막과 질화막으로 이루어진 충간절연막의 식각방법
KR970067603A (ko) 비정질 탄소 박막 및 그것의 형성 방법, 그리고 비정질 탄소 박막을 사용한 반도체 디바이스
KR940008049A (ko) 집적 회로 제조 방법
KR930006831A (ko) 접점 형성의 공정
KR970063761A (ko) 피막 제조 방법
KR970067720A (ko) 신뢰성있는 반도체 소자를 제조하기 위한 방법
KR980005823A (ko) 반도체 소자의 층간절연막 평탄화방법
KR960039152A (ko) 반도체 소자의 콘택 형성방법
KR970072170A (ko) 플라즈마에칭장치 및 플라즈마에칭방법
KR910010642A (ko) 반도체 장치에 도핑된 산화물층 형성 공정
KR950021102A (ko) 반도체 소자의 금속배선 형성방법
KR970023853A (ko) 폴리실리콘층간의 절연층의 제조방법
KR970052480A (ko) 폴리사이드 구조의 게이트 형성방법
KR100224706B1 (ko) 반도체 소자의 층간 절연층 형성방법
KR960005798A (ko) 저저항 콘택을 갖는 비트라인 및 그 제조방법
KR970052911A (ko) 반도체 소자의 평탄화 방법
KR940021758A (ko) 텅스텐 박막의 증착 방법
KR980005810A (ko) 반도체 소자의 층간 절연막 형성 방법
KR960002472A (ko) 화학기상증착법에 의한 산화막 형성방법
KR970030342A (ko) 전하저장전극 콘택홀 형성방법

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20081006

Year of fee payment: 11

LAPS Lapse due to unpaid annual fee