KR940006197A - 반도체장치의 콘택부 형성방법 - Google Patents

반도체장치의 콘택부 형성방법 Download PDF

Info

Publication number
KR940006197A
KR940006197A KR1019930008225A KR930008225A KR940006197A KR 940006197 A KR940006197 A KR 940006197A KR 1019930008225 A KR1019930008225 A KR 1019930008225A KR 930008225 A KR930008225 A KR 930008225A KR 940006197 A KR940006197 A KR 940006197A
Authority
KR
South Korea
Prior art keywords
forming
silicon
refractory material
layer
material film
Prior art date
Application number
KR1019930008225A
Other languages
English (en)
Other versions
KR960016223B1 (en
Inventor
다까오 기노시따
사또시 사이또
Original Assignee
쓰지 하루오
샤프 가부시끼가이샤
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 쓰지 하루오, 샤프 가부시끼가이샤 filed Critical 쓰지 하루오
Publication of KR940006197A publication Critical patent/KR940006197A/ko
Application granted granted Critical
Publication of KR960016223B1 publication Critical patent/KR960016223B1/ko

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H01L21/28556—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/147—Silicides

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

반도체장치의 콘택부를 형성하는 방법을 개시하고 있다.
본 발명의 방법은 실리콘 화합물상에 절연층을 형성하는 공정과, 상기 절연층에 콘택홀을 형성하되 상기 콘택홀이 상기 실리콘 화합물에 도달하게 하는 공정과, 상기 콘택홀의 내측벽과 상기 절연층외 표면상에 적어도 한층의 내화물질막을 형성하는 공정과, CVD방법에 의해 상기 내화물질막상에 실리콘함유의 텅스텐층을 형성하는 공정과, CVD방법에 의해 상기 실리콘 함유의 텅스텐층상에 텅스텐을 성장하여 상기 콘택홀에 상기 텅스텐으로 채워 넣는 공정을 포함한다.

Description

반도체장치의 콘택부 형성방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1A도 내지 제1D도는 본 발명에 의한 반도체장치의 콘택(contact)을 형성하는 방법의 제조공정들을 예시하는 단면도이다.

Claims (8)

  1. 실리콘 화합물상에 절연층을 형성하는 공정과, 상기 절연층에 콘택홀을 형성하되 상기 콘택홀이 상기 실리콘 화합물에 도달하게 하는 공정과, 상기 콘택홀의 내측벽과 상기 절연층의 표면상에 적어도 한층의 내화물질막을 형성하는 공정과, CVD 방법에 의해 상기 내화물질막상에 실리콘 함유의 텅스텐층을 형정하는 공정과, CVD 방법에 의해 상기 실리콘 함유의 텅스텐층상에 텅스텐을 성장하여 상기 콘택홀에 상기 텅스텐으로 채워넣는 공정을 포함하는 콘택부 형성방법.
  2. 제1항에 있어서, 상기 내화물질막상에 상기의 실리콘 함유의 텅스텐층을 형성하는 공정은 적어도 WF6및 SiH4를 함유하는 제1개스를 사용하여 수행되고, 상기 실리콘 함유의 텅스텐층상에 상기 텅스텐을 성장하는 공정은 적어도 WF6및 H2를 함유하는 제2 개스를 사용하여 수행되는 콘택부 형성방법.
  3. 제2항에 있어서, 상기 내화물질막상에 상기의 실리콘 함유의 텅스텐층을 형성하는 공정에서, SiH4/WF6의 비가 6 이상인 콘택부 형성방법.
  4. 제2항에 있어서, 상기 내화물질막상에 상기 실리콘함유의 텅스텐층을 형성하는 공정과 상기 실리콘함유의 텅스텐층상에 상기 텅스턴을 성장하는 공정은 동일한 CVD 챔버에서 연속적으로 수행되는 콘택부 형성방법.
  5. 제1항에 있어서, 상기 내화물질막을 형성하는 공정은 상기 콘택홀의 내측벽과 상기 절연층의 표면상에 내화 금속막을 형성하는 공정을 포함하는 콘택부 형성방법.
  6. 제5항에 있어서, 상기 내화물질막을 형성하는 공정은 상기 내화금속막상에 나이트라이드막을 형성하는 공정을 부가한 콘택부 형성방법.
  7. 제6항에 있어서, 상기 내화물질막은 티타늄으로 이루어지고, 그리고 상기 나이트라이드막은 티타늄 나이트 라이드막으로 이루어진 콘택부 형성방법.
  8. 제1항에 있어서, 상기 실리콘 함유의 텅스텐층은 0.6 Wt.%에서 20 Wt.%의 범위에서 실리콘을 함유하는 콘택부 형성방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR93008225A 1992-05-14 1993-05-13 Method of forming a contact KR960016223B1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP92-121802 1992-05-14
JP4121802A JP2889430B2 (ja) 1992-05-14 1992-05-14 コンタクト部形成方法

Publications (2)

Publication Number Publication Date
KR940006197A true KR940006197A (ko) 1994-03-23
KR960016223B1 KR960016223B1 (en) 1996-12-07

Family

ID=14820290

Family Applications (1)

Application Number Title Priority Date Filing Date
KR93008225A KR960016223B1 (en) 1992-05-14 1993-05-13 Method of forming a contact

Country Status (3)

Country Link
US (1) US5332691A (ko)
JP (1) JP2889430B2 (ko)
KR (1) KR960016223B1 (ko)

Families Citing this family (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3294413B2 (ja) * 1993-12-28 2002-06-24 富士通株式会社 半導体装置の製造方法及び製造装置
US5552339A (en) * 1994-08-29 1996-09-03 Taiwan Semiconductor Manufacturing Company Furnace amorphous-SI cap layer to prevent tungsten volcano effect
US5599739A (en) * 1994-12-30 1997-02-04 Lucent Technologies Inc. Barrier layer treatments for tungsten plug
KR0165813B1 (ko) * 1995-04-12 1999-02-01 문정환 접속홀의 플러그 형성 방법
US5747379A (en) * 1996-01-11 1998-05-05 Taiwan Semiconductor Manufacturing Company, Ltd. Method of fabricating seamless tungsten plug employing tungsten redeposition and etch back
US5994220A (en) 1996-02-02 1999-11-30 Micron Technology, Inc. Method for forming a semiconductor connection with a top surface having an enlarged recess
US5656545A (en) * 1996-02-26 1997-08-12 Taiwan Semiconductor Manufacturing Company, Ltd Elimination of tungsten dimple for stacked contact or via application
US5712207A (en) * 1996-02-29 1998-01-27 Taiwan Semiconductor Manufacturing Company, Ltd. Profile improvement of a metal interconnect structure on a tungsten plug
US5622894A (en) * 1996-03-15 1997-04-22 Taiwan Semiconductor Manufacturing Company Ltd Process to minimize a seam in tungsten filled contact holes
US5672543A (en) * 1996-04-29 1997-09-30 Taiwan Semiconductor Manufacturing Company, Ltd. Volcano defect-free tungsten plug
US20040224501A1 (en) * 1996-05-22 2004-11-11 Yung-Tsun Lo Manufacturing method for making tungsten-plug in an intergrated circuit device without volcano phenomena
US5801096A (en) * 1996-06-03 1998-09-01 Taiwan Semiconductor Manufacturing Company Ltd. Self-aligned tungsen etch back process to minimize seams in tungsten plugs
US5677237A (en) * 1996-06-21 1997-10-14 Taiwan Semiconductor Manufacturing Company Ltd. Process for removing seams in tungsten plugs
US5700726A (en) * 1996-06-21 1997-12-23 Taiwan Semiconductor Manufacturing Company Ltd Multi-layered tungsten depositions for contact hole filling
JP2800788B2 (ja) * 1996-06-27 1998-09-21 日本電気株式会社 半導体装置の製造方法
US5858873A (en) * 1997-03-12 1999-01-12 Lucent Technologies Inc. Integrated circuit having amorphous silicide layer in contacts and vias and method of manufacture thereof
US5821168A (en) * 1997-07-16 1998-10-13 Motorola, Inc. Process for forming a semiconductor device
KR100290781B1 (ko) * 1998-06-30 2001-06-01 박종섭 반도체 소자 및 그 제조방법
US6066366A (en) * 1998-07-22 2000-05-23 Applied Materials, Inc. Method for depositing uniform tungsten layers by CVD
US6245654B1 (en) * 1999-03-31 2001-06-12 Taiwan Semiconductor Manufacturing Company, Ltd Method for preventing tungsten contact/via plug loss after a backside pressure fault
US6284636B1 (en) * 2000-01-21 2001-09-04 Advanced Micro Devices, Inc. Tungsten gate method and apparatus
US6218301B1 (en) * 2000-07-31 2001-04-17 Applied Materials, Inc. Deposition of tungsten films from W(CO)6
US20020190379A1 (en) * 2001-03-28 2002-12-19 Applied Materials, Inc. W-CVD with fluorine-free tungsten nucleation
JP4785030B2 (ja) 2005-01-18 2011-10-05 富士通セミコンダクター株式会社 半導体装置とその製造方法
US20160086805A1 (en) * 2014-09-24 2016-03-24 Qualcomm Incorporated Metal-gate with an amorphous metal layer

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4851295A (en) * 1984-03-16 1989-07-25 Genus, Inc. Low resistivity tungsten silicon composite film
US5130266A (en) * 1990-08-28 1992-07-14 United Microelectronics Corporation Polycide gate MOSFET process for integrated circuits

Also Published As

Publication number Publication date
KR960016223B1 (en) 1996-12-07
JP2889430B2 (ja) 1999-05-10
JPH05315284A (ja) 1993-11-26
US5332691A (en) 1994-07-26

Similar Documents

Publication Publication Date Title
KR940006197A (ko) 반도체장치의 콘택부 형성방법
KR900002316A (ko) 반도체장치의 제조방법
KR900013588A (ko) 막 형성 방법
KR930005115A (ko) 저온,고압 상태에서의 실리콘 증착방법
ES2088783T3 (es) Procedimiento de dos fases para la fabricacion de una capa de oxido sobre una superficie escalonada de una oblea de semiconductor.
KR940016484A (ko) 반도체장치 및 그 제조방법
EP1347506A4 (en) SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
KR920022405A (ko) 층의 형성방법
KR900005589A (ko) 반도체 집적회로 장치 및 그 제조방법
KR900010993A (ko) Vlsi장치의 n+ 및 p+저항영역에 저저항 접속방법
KR950030308A (ko) 반도체 장치 제조방법
KR950025868A (ko) 반도체 소자의 비트라인 형성방법
KR940021758A (ko) 텅스텐 박막의 증착 방법
KR930005179A (ko) 반도체장치의 제조방법
KR920001710A (ko) 선택적 화학증착시 텅스텐의 차별 성장방법
KR940016690A (ko) 반도체장치의 콘택플러그 형성방법
KR980005677A (ko) 반도체 소자의 실리사이드 형성방법
KR950007026A (ko) 반도체 소자의 산화막 형성방법
KR960005797A (ko) 반도체소자 배선 형성방법
KR950034629A (ko) 반도체 소자의 게이트 전극 형성방법
KR970052893A (ko) 반도체 소자의 텅스텐 실리사이드층 형성 방법
KR940001279A (ko) 반도체의 금속배선 형성방법
KR980005438A (ko) 도전층 형성 방법
KR970030452A (ko) 산화막과 질화막으로 이루어진 충간절연막의 식각방법
KR960026390A (ko) 반도체 소자의 질화티타늄층 형성방법

Legal Events

Date Code Title Description
A201 Request for examination
G160 Decision to publish patent application
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20121121

Year of fee payment: 17

EXPY Expiration of term