KR920022405A - 층의 형성방법 - Google Patents

층의 형성방법 Download PDF

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Publication number
KR920022405A
KR920022405A KR1019920009093A KR920009093A KR920022405A KR 920022405 A KR920022405 A KR 920022405A KR 1019920009093 A KR1019920009093 A KR 1019920009093A KR 920009093 A KR920009093 A KR 920009093A KR 920022405 A KR920022405 A KR 920022405A
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KR
South Korea
Prior art keywords
layer
recess
article
semiconductor wafer
metal
Prior art date
Application number
KR1019920009093A
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English (en)
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KR100242602B1 (ko
Inventor
데이비드 도브슨 크리스토퍼
Original Assignee
원본미기재
일렉트로테크 리미티드
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from GB919111440A external-priority patent/GB9111440D0/en
Priority claimed from GB929202745A external-priority patent/GB9202745D0/en
Application filed by 원본미기재, 일렉트로테크 리미티드 filed Critical 원본미기재
Publication of KR920022405A publication Critical patent/KR920022405A/ko
Application granted granted Critical
Publication of KR100242602B1 publication Critical patent/KR100242602B1/ko

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67155—Apparatus for manufacturing or treating in a plurality of work-stations
    • H01L21/67161—Apparatus for manufacturing or treating in a plurality of work-stations characterized by the layout of the process chambers
    • H01L21/67167—Apparatus for manufacturing or treating in a plurality of work-stations characterized by the layout of the process chambers surrounding a central transfer chamber
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/32115—Planarisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67155—Apparatus for manufacturing or treating in a plurality of work-stations
    • H01L21/67207—Apparatus for manufacturing or treating in a plurality of work-stations comprising a chamber adapted to a particular process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76819—Smoothing of the dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H01L21/76882—Reflowing or applying of pressure to better fill the contact hole
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4038—Through-connections; Vertical interconnect access [VIA] connections
    • H05K3/4084—Through-connections; Vertical interconnect access [VIA] connections by deforming at least one of the conductive layers
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/03—Conductive materials
    • H05K2201/0332—Structure of the conductor
    • H05K2201/0335—Layered conductors or foils
    • H05K2201/0355—Metal foils
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/02—Details related to mechanical or acoustic processing, e.g. drilling, punching, cutting, using ultrasound
    • H05K2203/0278—Flat pressure, e.g. for connecting terminals with anisotropic conductive adhesive
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/11—Treatments characterised by their effect, e.g. heating, cooling, roughening
    • H05K2203/1105—Heating or thermal processing not related to soldering, firing, curing or laminating, e.g. for shaping the substrate or during finish plating

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Physical Vapour Deposition (AREA)
  • Element Separation (AREA)
  • Chemical Vapour Deposition (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)

Abstract

내용 없음.

Description

층의 형성방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본 발명에 따른 층의 형성에 앞서 반도체 웨이퍼의 단면도,
제2도는 본 발명에 따른 층의 형성 중간단계에서 제1도의 웨이퍼의 단면도,
제3도는 층이 완성된 이후 웨이퍼의 단면도.

Claims (8)

  1. 내부에 최소 하나의 리세스를 가진 표면부를 구비하는 아티클 처리방법에 잇어서, 상기 표면부의 최소 부분에 상기 리세스 상으로 연장하는 층을 형성하는 단계와, 상기 층의 부분이 상기 리세스를 충진하기 위해 변형할 정도로 상기아티클 및 상기 층을 충분히 사용된 압력 및 온도로 가하는 단계를 포함하는 것을 특징으로 하는 아티클 처리방법.
  2. 제1항에 있어서, 상기 층의 형성은 증착에 의해 형성되는 것을 특징으로 하는 아티클 처리 방법.
  3. 제1항에 있어서 상기 층의 형성은 상승된 온도로 증착함으로써 형성되는 것을 특징으로 하는 아티클 처리 방법.
  4. 제1항에 있어서, 상기 아티클은 반도체 웨이퍼이며, 상기 리세스는 일련의 홀, 트랜치 및 상기 반도체 웨이퍼의 비어로 부터 선택되는 것을 특징으로 하는 아티클 처리방법.
  5. 제4항에 있어서, 상기 층은 금속인 것을 특징으로 하는 아티클 처리 방법.
  6. 제5항에 있어서, 상기 금속은 알루미늄 및 알루미늄 합금으로 부터 선택되는 것을 특징으로 하는 아티클 처리방법.
  7. 제4항에 있어서, 상기 리세스는 상기 반도체 웨이퍼의 절연층 내에 있는 것을 특징으로 하는 아티클 처리방법.
  8. 제4항에 있어서, 상기 층은 절연 금속으로 구성되는 것을 특징으로 하는 아티클 처리방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개되는 것임.
KR1019920009093A 1991-05-28 1992-05-28 층의 형성방법 KR100242602B1 (ko)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
GB9111440.5 1991-05-28
GB919111440A GB9111440D0 (en) 1991-05-28 1991-05-28 Forming a layer
GB929202745A GB9202745D0 (en) 1992-02-10 1992-02-10 Forming a layer
GB9202745.7 1992-02-10

Publications (2)

Publication Number Publication Date
KR920022405A true KR920022405A (ko) 1992-12-19
KR100242602B1 KR100242602B1 (ko) 2000-02-01

Family

ID=26298966

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019920009093A KR100242602B1 (ko) 1991-05-28 1992-05-28 층의 형성방법

Country Status (6)

Country Link
EP (1) EP0516344B1 (ko)
JP (1) JP3105643B2 (ko)
KR (1) KR100242602B1 (ko)
AT (1) ATE251342T1 (ko)
DE (1) DE69233222T2 (ko)
TW (1) TW221521B (ko)

Families Citing this family (25)

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GB9414145D0 (en) * 1994-07-13 1994-08-31 Electrotech Ltd Forming a layer
US5932289A (en) * 1991-05-28 1999-08-03 Trikon Technologies Limited Method for filling substrate recesses using pressure and heat treatment
GB9402486D0 (en) * 1994-02-09 1994-03-30 Electrotech Ltd Forming a layer
KR960026249A (ko) * 1994-12-12 1996-07-22 윌리엄 이. 힐러 고압, 저온 반도체 갭 충진 프로세스
EP0793268A3 (en) * 1995-05-23 1999-03-03 Texas Instruments Incorporated Process for filling a cavity in a semiconductor device
US5857368A (en) * 1995-10-06 1999-01-12 Applied Materials, Inc. Apparatus and method for fabricating metal paths in semiconductor substrates through high pressure extrusion
GB9619461D0 (en) 1996-09-18 1996-10-30 Electrotech Ltd Method of processing a workpiece
GB2319533B (en) 1996-11-22 2001-06-06 Trikon Equip Ltd Methods of forming a barrier layer
GB2319532B (en) 1996-11-22 2001-01-31 Trikon Equip Ltd Method and apparatus for treating a semiconductor wafer
US6218277B1 (en) 1998-01-26 2001-04-17 Texas Instruments Incorporated Method for filling a via opening or contact opening in an integrated circuit
JP4357486B2 (ja) 2003-06-18 2009-11-04 ロジャー・ピー・ジャクソン スプライン捕捉連結部を備えた多軸骨ねじ
US7322981B2 (en) 2003-08-28 2008-01-29 Jackson Roger P Polyaxial bone screw with split retainer ring
US7160300B2 (en) 2004-02-27 2007-01-09 Jackson Roger P Orthopedic implant rod reduction tool set and method
US10049927B2 (en) 2016-06-10 2018-08-14 Applied Materials, Inc. Seam-healing method upon supra-atmospheric process in diffusion promoting ambient
US10622214B2 (en) 2017-05-25 2020-04-14 Applied Materials, Inc. Tungsten defluorination by high pressure treatment
US10276411B2 (en) 2017-08-18 2019-04-30 Applied Materials, Inc. High pressure and high temperature anneal chamber
WO2019036157A1 (en) 2017-08-18 2019-02-21 Applied Materials, Inc. HIGH PRESSURE AND HIGH TEMPERATURE RECOVERY CHAMBER
EP4321649A3 (en) 2017-11-11 2024-05-15 Micromaterials LLC Gas delivery system for high pressure processing chamber
CN111432920A (zh) 2017-11-17 2020-07-17 应用材料公司 用于高压处理系统的冷凝器系统
SG11202008256WA (en) 2018-03-09 2020-09-29 Applied Materials Inc High pressure annealing process for metal containing materials
US10950429B2 (en) 2018-05-08 2021-03-16 Applied Materials, Inc. Methods of forming amorphous carbon hard mask layers and hard mask layers formed therefrom
US10748783B2 (en) 2018-07-25 2020-08-18 Applied Materials, Inc. Gas delivery module
WO2020117462A1 (en) 2018-12-07 2020-06-11 Applied Materials, Inc. Semiconductor processing system
US11901222B2 (en) 2020-02-17 2024-02-13 Applied Materials, Inc. Multi-step process for flowable gap-fill film
CN113543527B (zh) * 2021-07-09 2022-12-30 广东工业大学 载板填孔工艺的填充基材选型方法及载板填孔工艺

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* Cited by examiner, † Cited by third party
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DE69023382T2 (de) * 1989-04-17 1996-06-20 Ibm Laminierungsverfahren zum Überdecken der Seitenwände einer Höhlung in einem Substrat sowie zur Füllung dieser Höhlung.
US5011793A (en) * 1990-06-19 1991-04-30 Nihon Shinku Gijutsu Kabushiki Kaisha Vacuum deposition using pressurized reflow process

Also Published As

Publication number Publication date
DE69233222T2 (de) 2004-08-26
JPH07193063A (ja) 1995-07-28
KR100242602B1 (ko) 2000-02-01
TW221521B (ko) 1994-03-01
EP0516344A1 (en) 1992-12-02
DE69233222D1 (de) 2003-11-06
JP3105643B2 (ja) 2000-11-06
ATE251342T1 (de) 2003-10-15
EP0516344B1 (en) 2003-10-01

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