KR880005666A - 선택적으로 산화된 실리콘 기판상에 에피택셜 실리콘 층과 다결정 실리콘 층을 동시에 성장시키는 증착방법 - Google Patents

선택적으로 산화된 실리콘 기판상에 에피택셜 실리콘 층과 다결정 실리콘 층을 동시에 성장시키는 증착방법 Download PDF

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KR880005666A
KR880005666A KR870011063A KR870011063A KR880005666A KR 880005666 A KR880005666 A KR 880005666A KR 870011063 A KR870011063 A KR 870011063A KR 870011063 A KR870011063 A KR 870011063A KR 880005666 A KR880005666 A KR 880005666A
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silicon
layer
silicon layer
substrate
silicon substrate
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KR870011063A
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KR900007686B1 (ko
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후미다께 미에노
가주유끼 구리다
신지 나까무라
아두오 시미즈
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야마모도 다꾸마
후지쓰 가부시끼가이샤
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Priority claimed from JP61239910A external-priority patent/JPS6394684A/ja
Priority claimed from JP61276958A external-priority patent/JPS63129613A/ja
Priority claimed from JP27694886A external-priority patent/JPS63129612A/ja
Priority claimed from JP61276972A external-priority patent/JPS63129614A/ja
Priority claimed from JP61276945A external-priority patent/JPS63129611A/ja
Priority claimed from JP61281004A external-priority patent/JPS63133615A/ja
Application filed by 야마모도 다꾸마, 후지쓰 가부시끼가이샤 filed Critical 야마모도 다꾸마
Publication of KR880005666A publication Critical patent/KR880005666A/ko
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • H01L21/205—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy using reduction or decomposition of a gaseous compound yielding a solid condensate, i.e. chemical deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02381—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/02433—Crystal orientation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/0257—Doping during depositing
    • H01L21/02573—Conductivity type
    • H01L21/02576—N-type
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/0257—Doping during depositing
    • H01L21/02573—Conductivity type
    • H01L21/02579—P-type
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/02636—Selective deposition, e.g. simultaneous growth of mono- and non-monocrystalline semiconductor materials
    • H01L21/02639—Preparation of substrate for selective deposition
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/017—Clean surfaces
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/026—Deposition thru hole in mask

Abstract

내용 없음

Description

선택적으로 산화된 실리콘 기판상에 에피택셜 실리콘 층과 다결정 실리콘 층을 동시에 성장시키는 증착방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 에리베이티드(elevated) 소오스-드레인 영역을 지닌 MOSFET의 구조를 설명한 단면도.
제2도는 에리베이티드 베이스 접촉영역을 지진 바이폴라 IC를 설명한 단면도.

Claims (10)

  1. 반도체 장치를 제조하는 방법에 있어서, (a) 실리콘(Si) 기판의 표면상에 이산화 실리콘(SiO2)을 형성하는 단계와, (b) 기판 온도 780°-950℃, 통상의 가스 압력 이하의 가스 압력하에서 수산화 규산가스를 이용한 기상 증착 공정으로 상기 실리콘 기판의 상기 표면상에 에피택셜 실리콘 층들과, 상기 이산화 실리콘 층상에 폴리 실리콘 층을 동시에 형성하는 단계로 이루어져 있는 반도체 장치를 제조하는 방법.
  2. 청구범위 제1항에 있어서, 상기 수산화 규산가스가 다실란(Si2H6) 가스인 방법.
  3. 청구범위 제2항에 있어서, 상기 실리콘 기판이 면지수(100)를 지닌 주요표면을 가지고, 그것으로서 상기 에피택셜 실리콘 층의 확장 상측표면이 상기 에피택셜 실리콘 층의 하측 표면의 영역보다 더 넓은 영역을 지닌 방법.
  4. 청구범위 제2항에 있어서, 상기 실리콘 기판이 면지수(111)를 지닌 주요표면을 가지고, 그것으로서 상기 다결정 실리콘 층을 얻는 방법.
  5. 청구범위 제2항에 있어서, 상기 가스 압력의 범위가 30-300Torr인 방법.
  6. 청구범위 제1항에 있어서, 상기 반도체 장치가 MOS 전계 효과 트랜지스터인 방법.
  7. 청구범위 제1항에 있어서, 상기 반도체 장치가 바이폴라 트랜지스터인 방법.
  8. 청구범위 제1항에 있어서, 상기 반도체 장치가 MOS 전계 효과 트랜지스터와 바이폴라 트랜지스터를 포함하는 방법.
  9. 청구범위 제1항에 있어서, 상기 단계(a)와 상기 단계(b)와의 사이에 이온들을 사용하여 상기 실리콘 기판 및 상기 이산화 실리콘 층의 표면에 스퓨터링하는 단계를 포함하는 방법.
  10. 청구범위 제1항에 있어서, 상기 단계(a)와 상기 단계(b)와의 사이에 상기 실리콘 기판 및 상기 이산화 실리콘 층의 표면을 세척하는 화학 공정을 함유하는 단계를 더 포함하는 방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019870011063A 1986-10-08 1987-10-02 선택적으로 산화된 실리콘 기판상에 에피택셜 실리콘층과 다결정 실리콘층을 동시에 성장시키는 기상 증착방법 KR900007686B1 (ko)

Applications Claiming Priority (18)

Application Number Priority Date Filing Date Title
JP239910 1986-10-08
JP61-239910 1986-10-08
JP61239910A JPS6394684A (ja) 1986-10-08 1986-10-08 半導体装置の製造方法
JP61-276972 1986-11-20
JP61276958A JPS63129613A (ja) 1986-11-20 1986-11-20 気相成長方法
JP61-276958 1986-11-20
JP276948 1986-11-20
JP27694886A JPS63129612A (ja) 1986-11-20 1986-11-20 気相成長方法
JP61-276948 1986-11-20
JP61276972A JPS63129614A (ja) 1986-11-20 1986-11-20 気相成長方法
JP61-276945 1986-11-20
JP61276945A JPS63129611A (ja) 1986-11-20 1986-11-20 気相成長方法
JP61281004A JPS63133615A (ja) 1986-11-26 1986-11-26 気相成長方法
JP61-281004 1986-11-26
JP276972 1987-11-26
JP276945 1987-11-26
JP276958 1987-11-26
JP281004 1987-11-26

Publications (2)

Publication Number Publication Date
KR880005666A true KR880005666A (ko) 1988-06-29
KR900007686B1 KR900007686B1 (ko) 1990-10-18

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KR1019870011063A KR900007686B1 (ko) 1986-10-08 1987-10-02 선택적으로 산화된 실리콘 기판상에 에피택셜 실리콘층과 다결정 실리콘층을 동시에 성장시키는 기상 증착방법

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US (1) US4966861A (ko)
EP (1) EP0267082B1 (ko)
KR (1) KR900007686B1 (ko)
DE (1) DE3789852D1 (ko)

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DE3789852D1 (de) 1994-06-23
EP0267082B1 (en) 1994-05-18
US4966861A (en) 1990-10-30
EP0267082A1 (en) 1988-05-11
KR900007686B1 (ko) 1990-10-18

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