KR890011081A - 집적회로 제조방법 - Google Patents

집적회로 제조방법 Download PDF

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KR890011081A
KR890011081A KR1019880017446A KR880017446A KR890011081A KR 890011081 A KR890011081 A KR 890011081A KR 1019880017446 A KR1019880017446 A KR 1019880017446A KR 880017446 A KR880017446 A KR 880017446A KR 890011081 A KR890011081 A KR 890011081A
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South Korea
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layer
dielectric layer
oxide layer
substrate
deposition
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KR1019880017446A
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KR930003271B1 (ko
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에이취. 도클란 레이몬드
폴 마틴 2세 에드워드
쿠마 로이 프라딥
프란시스 쉬브 스코트
쿠마 신하 아스혹
Original Assignee
엘리 와이스
아메리칸 텔리폰 앤드 텔레그라프 캄파니
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Publication of KR890011081A publication Critical patent/KR890011081A/ko
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Publication of KR930003271B1 publication Critical patent/KR930003271B1/ko

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    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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Abstract

내용 없음

Description

집적회로 제조방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제 1 도는 본 발명에 따른 구조의 개략도.
제 2 도는 산화 단계에 대한 일반적 열이력(The general thermal history) 도시도.
제 3 도는 어닐링(annealing) 전후의 산화물에 대한 전형적인 FTIR 흡수(Si-O) 스펙트럼 도시도.
* 도면의 주요부분에 대한 부호의 설명
1 : 실리콘 기판 3 : 제 1 열적 산화물층
5 : 유전체층 9 : 부가 열적 산화물층

Claims (8)

  1. (1) 기판의 노출된 표면 부분에 결함구조를 포함하는 제 1 열적 산화물층(3)을 성장시키는 단계와, (2) 상기 제 1 열적 산화물층 위에 유전체층(5)을 증착하는 단계로서, 상기 유전체층은 산화종을 투과하는 조성이며 결함구조를 포함하고, 상기 제 1 열적 산화물층과 상기 유전체층이 조합된 이중층 사이에 계면이 한정되는 상기 증착 단계를 구비한, 기판상에 성장된 얇고 평평한 산화물층으로 이루어지며, 응력이 없는 계면이 그 사이에 형성되게 직접 회로를 제조하는 방법에 있어서, (3) 상기 유전체(5) 및 제 1 산화물층(3)을 통해 산화종을 확산시킴으로써, 상기 기판에 대해 평평하고 응력이 없는 계면을 만드는 비교적 얇은층인 부가열적 산화물층(9)을 상기 제 1 열적 산화물층 아래에 성장시키는 단계를 포함하는 것을 특징으로 하는 집적회로 제조방법.
  2. 제 1 항에 있어서, 상기 단계(2)를 수행하는데 있어서, 상기 유전체층의 결함구조가 상기 단계(1)에서 성장된 상기 제 1 열적 산화물의 결함구조와 비정합되게 상기 유전체 층이 형성되는 것을 특징으로 하는 집적회로 제조방법.
  3. 제 1 항 또는 2항에 있어서, 상기 단계(2)의 유전체층이 증착 산화물층을 포함하는 것을 특징으로 하는 집적회로 제조방법.
  4. 제 3 항에 있어서, 상기 단계(2)를 수행하는데 있어서, 상기 산화물이 테트라에톡시실란(TEOS)의 저압 CVD 증착에 의해 형성되는 것을 특징으로 하는 집적회로 제조방법.
  5. 제 4 항에 있어서, 상기 단계(2)의 증착을 수행하는데 있어, 증착 온도는 약 625℃ 내지 750℃ 사이의 범위에 있으며, 증착 압력은 약 150밀리토르와 400밀리토르 사이에 있는 것을 특징으로 하는 집적회로 제조방법.
  6. 제 1 항 또는 2항에 있어서, 상기 단계(2)를 수행하는데 있어, 상기 유전체층이 실리콘 옥시니트라이드를 형성하도록, 완전하게 산화된 증착 실리콘 질화물층을 포함하는 것을 특징으로 하는 집적회로 제조방법.
  7. 제 1 항 또는 2항에 있어서, 상기 단계(2)를 수행하는데 있어, 상기 유전체층이 계속해서 산화되는 증착 폴리실리콘층을 포함하는 것을 특징으로 하는 집적회로 제조방법.
  8. 제 1 항에 있어서, 상기 단계(3)은, (3-1) 약 750℃의 주위 온도로 상기 기판을 노출시키는 단계와, (3-2) 상기 주위 온도를 약 850℃ 내지 900℃의 범위내까지 증가시키는 단계와, (3-3) 기판 주위 분위기로 산화종을 포함한 가스를 도입시키는 단계와, (3-4) 상기 제 2 산화물층의 소망 두께와 관련된 소정 시간 주기동안 산소 분위기에서 상기 기판을 유지시키는 단계와, (3-5) 산소 분위기를 제거하고 주위 온도를 약 750℃까지 감소시키는 단계 및, (3-6) 기판을 냉각시키는 단계로 수행되는 것을 특징으로 하는 집적회로 제조방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019880017446A 1987-12-28 1988-12-26 집적회로 제조방법 KR930003271B1 (ko)

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KR930003271B1 (ko) 1993-04-24
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JPH0626211B2 (ja) 1994-04-06
EP0323071B1 (en) 1995-04-26
US4851370A (en) 1989-07-25
ES2071619T3 (es) 1995-07-01
JPH01204435A (ja) 1989-08-17
DE3853668D1 (de) 1995-06-01
EP0323071A2 (en) 1989-07-05
CA1284236C (en) 1991-05-14
DE3853668T2 (de) 1995-12-21

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