KR930005134A - 증착된 반도체상에 형성된 개선된 유전체 - Google Patents

증착된 반도체상에 형성된 개선된 유전체 Download PDF

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KR930005134A
KR930005134A KR1019920014891A KR920014891A KR930005134A KR 930005134 A KR930005134 A KR 930005134A KR 1019920014891 A KR1019920014891 A KR 1019920014891A KR 920014891 A KR920014891 A KR 920014891A KR 930005134 A KR930005134 A KR 930005134A
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silicon
sublayer
semiconductor
deposition
varying
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KR970009976B1 (ko
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루돌프 라도세비치 죠셉
쿠마 로이 프래딥
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제임스 에이취. 폭스
아메리칸 텔리폰 앤드 텔레그라프 캄파니
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/32055Deposition of semiconductive layers, e.g. poly - or amorphous silicon layers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008Making conductor-insulator-semiconductor electrodes
    • H01L21/28017Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158Making the insulator
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401Multistep manufacturing processes
    • H01L29/4011Multistep manufacturing processes for data storage electrodes
    • H01L29/40114Multistep manufacturing processes for data storage electrodes the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

내용 없음.

Description

증착된 반도체상에 형성된 개선된 유전체
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 증착된 반도체 층으로 형성된 종래기술의 커패시터의 도시도,
제2도는 시간 함수로서의 폴리 실리콘 증착속도에 있어서의 주기적 변화의 일례의 도시도,
제3도는 증착된 반도체 서브 층 및 그 위의 유전층의 도시도,
제4도는 예1에 대한 폴리실리콘 증착 속도에 있어서의 변화의 도시도.

Claims (13)

  1. 증착 가스로부터 반도체 층을 증착하는 단계와 상기 반도체층의 노출된 표면상에 유전체(35)을 형성하는 단계로 구성되는 반도체 장치를 만드는 방법에 있어서, 반도체 층(31,32,33,34)을 증착하는 상기 단계가 반도체의 증착 속도를 변화시킴에 의하여 실현되고 상기 변화는 부분압 및 증착 가스의 흐름속도로 이루어지는 그룹으로 부터 인자들중 적어도 하나를 변화시켜서 이루어지는 것을 특징으로 하는 방법.
  2. 제1항에 있어서, 상기 증착 동안에 상기 반도체 층내에 도펀트를 포함하여 적어도 하나의 다른 서브층과 비교하여 적어도 하나의 서브층내의 상기 도펀트의 농도를 변화시키는 단계를 더 포함하고 있는 방법.
  3. 제1항에 있어서, 상기 반도체가 실리콘인 방법.
  4. 제3항에 있어서, 상기 유전체 (35)가 실리콘 이산화물인 방법.
  5. 제1항에 있어서, 상기 형성이 단결정 실리콘상에 산화물을 형성하는 공정 동시에 실현하는 방법.
  6. 제5항에 있어서, 단결정 실리콘상에 형성된 산화물이 게이트 산화물인 방법.
  7. 제1항에 있어서, 상부 서브층(34)이 그 밑의 서브층보다 낮게 도핑되는 방법.
  8. 제1항에 있어서, 하부 서브층(31)이 그위의 서브층 보다 낮게 도핑되는 방법.
  9. 제1항에 있어서, 상기 증착동안에 반도체의 온도를 변화시키는 단계를 더 포함하고 있는 방법.
  10. 제1항에 있어서, 적어도 4개의 서브층(31,32,33,34)이 증착되는 방법.
  11. 실리콘을 포함하는 반응 가스의 분해에 의해 실리콘층을 증착하는 단계와 상기 실리콘충의 노출된 표면에 유전체 (35)를 형성하는 단계를 포함하는 반도체 장치를 만드는 방법에 있어서, 실리콘층을 증착하는 상기 단계가 실리콘의 증착 속도를 변화시켜 실현되고, 상기 변화는 실리콘을 포함하는 반응 가스의 부분압 및 실리콘을 포함하는 반응가스의 흐름속도로 이루어지는 그룹으로 부터 선택된 인자들중 적어도 하나를 변화시켜서 실현되며 이것에 의해 상기 반도체의 서브층(31,32,33,34)이 형성되고 상기 증착동안에 상기 실리콘 층내에 도펀트를 포함하는 단계와 적어도 하나의 다른 서브층과 비교할 때 상기 적어도 하나의 서브층내의 상기 도펀트의 농도를 변화시키는 단계를 더 포함하는 것을 특징으로 하는 방법.
  12. 제11항에 있어서, 상기 유전층이 실리콘 이산화물인 방법.
  13. 제11항에 있어서, 상기 도펀트가 인(phosphours)인 방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019920014891A 1991-08-26 1992-08-19 증착된 반도체상에 형성된 개선된 유전체 KR970009976B1 (ko)

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US74976591A 1991-08-26 1991-08-26
US749,765 1991-08-26

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KR970009976B1 KR970009976B1 (ko) 1997-06-19

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US (1) US5298436A (ko)
EP (1) EP0529951A3 (ko)
JP (1) JPH05206473A (ko)
KR (1) KR970009976B1 (ko)
SG (1) SG49595A1 (ko)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100444303B1 (ko) * 2001-12-31 2004-08-16 주식회사 하이닉스반도체 반도체소자의 캐패시터 형성방법

Families Citing this family (35)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5444302A (en) * 1992-12-25 1995-08-22 Hitachi, Ltd. Semiconductor device including multi-layer conductive thin film of polycrystalline material
KR0135166B1 (ko) * 1993-07-20 1998-04-25 문정환 반도체장치의 게이트 형성방법
US5663077A (en) * 1993-07-27 1997-09-02 Semiconductor Energy Laboratory Co., Ltd. Method of manufacturing a thin film transistor in which the gate insulator comprises two oxide films
US6897100B2 (en) 1993-11-05 2005-05-24 Semiconductor Energy Laboratory Co., Ltd. Method for processing semiconductor device apparatus for processing a semiconductor and apparatus for processing semiconductor device
CN1052566C (zh) * 1993-11-05 2000-05-17 株式会社半导体能源研究所 制造半导体器件的方法
JP3029235B2 (ja) * 1993-12-29 2000-04-04 現代電子産業株式会社 半導体素子の電荷貯蔵電極形成方法
KR0124629B1 (ko) * 1994-02-23 1997-12-11 문정환 불휘발성 반도체 메모리장치의 제조방법
JP3599290B2 (ja) * 1994-09-19 2004-12-08 株式会社ルネサステクノロジ 半導体装置
US5523259A (en) * 1994-12-05 1996-06-04 At&T Corp. Method of forming metal layers formed as a composite of sub-layers using Ti texture control layer
KR0165423B1 (ko) * 1995-07-24 1998-12-15 김광호 반도체 장치의 접속구조 및 그 제조방법
US6703672B1 (en) * 1995-09-29 2004-03-09 Intel Corporation Polysilicon/amorphous silicon composite gate electrode
US5994217A (en) * 1996-12-16 1999-11-30 Chartered Semiconductor Manufacturing Ltd. Post metallization stress relief annealing heat treatment for ARC TiN over aluminum layers
DE19706783A1 (de) * 1997-02-20 1998-08-27 Siemens Ag Verfahren zur Herstellung dotierter Polysiliciumschichten und -schichtstrukturen und Verfahren zum Strukturieren von Schichten und Schichtstrukturen, welche Polysiliciumschichten umfassen
JP3090201B2 (ja) * 1997-06-04 2000-09-18 日本電気株式会社 多結晶シリコン膜及び半導体装置
US5874333A (en) * 1998-03-27 1999-02-23 Taiwan Semiconductor Manufacturing Company, Ltd. Process for forming a polysilicon layer having improved roughness after POCL3 doping
US7192829B2 (en) 1998-07-17 2007-03-20 Micron Technology, Inc. Methods of forming floating gate transistors
US6268068B1 (en) * 1998-10-06 2001-07-31 Case Western Reserve University Low stress polysilicon film and method for producing same
US6479166B1 (en) 1998-10-06 2002-11-12 Case Western Reserve University Large area polysilicon films with predetermined stress characteristics and method for producing same
US6140187A (en) * 1998-12-02 2000-10-31 Lucent Technologies Inc. Process for forming metal oxide semiconductors including an in situ furnace gate stack with varying silicon nitride deposition rate
US6440829B1 (en) 1998-12-30 2002-08-27 Agere Systems Guardian Corp. N-profile engineering at the poly/gate oxide and gate oxide/SI interfaces through NH3 annealing of a layered poly/amorphous-silicon structure
US6162711A (en) * 1999-01-15 2000-12-19 Lucent Technologies, Inc. In-situ boron doped polysilicon with dual layer and dual grain structure for use in integrated circuits manufacturing
US6313021B1 (en) 1999-01-15 2001-11-06 Agere Systems Guardian Corp. PMOS device having a layered silicon gate for improved silicide integrity and enhanced boron penetration resistance
KR100376268B1 (ko) 1999-09-10 2003-03-17 주식회사 하이닉스반도체 반도체 소자의 캐패시터 제조방법
KR100351238B1 (ko) 1999-09-14 2002-09-09 주식회사 하이닉스반도체 반도체 소자의 캐패시터 제조 방법
KR100482753B1 (ko) 1999-11-09 2005-04-14 주식회사 하이닉스반도체 반도체 소자의 캐패시터 제조방법
JP2001147446A (ja) * 1999-11-19 2001-05-29 Hitachi Ltd 液晶表示装置とその製造方法
KR100351254B1 (ko) 1999-12-22 2002-09-09 주식회사 하이닉스반도체 반도체 소자의 게이트 전극 형성 방법
KR100376264B1 (ko) 1999-12-24 2003-03-17 주식회사 하이닉스반도체 게이트 유전체막이 적용되는 반도체 소자의 제조 방법
KR100358069B1 (ko) 1999-12-27 2002-10-25 주식회사 하이닉스반도체 반도체 소자의 캐패시터 제조방법
US7371600B2 (en) * 2001-06-13 2008-05-13 Mitsubishi Denki Kabushiki Kaisha Thin-film structure and method for manufacturing the same, and acceleration sensor and method for manufacturing the same
DE10148491B4 (de) * 2001-10-01 2006-09-07 Infineon Technologies Ag Verfahren zum Herstellen einer integrierten Halbleiteranordnung mit Hilfe einer thermischen Oxidation und Halbleiteranordnung
US6649514B1 (en) * 2002-09-06 2003-11-18 Lattice Semiconductor Corporation EEPROM device having improved data retention and process for fabricating the device
US20040209467A1 (en) * 2003-04-21 2004-10-21 Sinclair Wang Method for reducing plasma related damages
US7425736B2 (en) * 2005-06-07 2008-09-16 United Microelectronics Corp. Silicon layer with high resistance and fabricating method thereof
US7737031B2 (en) * 2007-08-02 2010-06-15 Intel Corporation Insitu formation of inverse floating gate poly structures

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4087571A (en) * 1971-05-28 1978-05-02 Fairchild Camera And Instrument Corporation Controlled temperature polycrystalline silicon nucleation
US4460416A (en) * 1982-12-15 1984-07-17 Burroughs Corporation Method for fabricating in-situ doped polysilicon employing overdamped gradually increasing gas flow rates with constant flow rate ratio
US4631804A (en) * 1984-12-10 1986-12-30 At&T Bell Laboratories Technique for reducing substrate warpage springback using a polysilicon subsurface strained layer
US4742020A (en) * 1985-02-01 1988-05-03 American Telephone And Telegraph Company, At&T Bell Laboratories Multilayering process for stress accommodation in deposited polysilicon
US4814291A (en) * 1986-02-25 1989-03-21 American Telephone And Telegraph Company, At&T Bell Laboratories Method of making devices having thin dielectric layers
JPS63255972A (ja) * 1987-04-14 1988-10-24 Toshiba Corp 半導体装置の製造方法
JPH01161826A (ja) * 1987-12-18 1989-06-26 Toshiba Corp 気相エピタキシャル成長法
US4992391A (en) * 1989-11-29 1991-02-12 Advanced Micro Devices, Inc. Process for fabricating a control gate for a floating gate FET

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100444303B1 (ko) * 2001-12-31 2004-08-16 주식회사 하이닉스반도체 반도체소자의 캐패시터 형성방법

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JPH05206473A (ja) 1993-08-13
US5298436A (en) 1994-03-29
EP0529951A2 (en) 1993-03-03
SG49595A1 (en) 1998-06-15
EP0529951A3 (en) 1993-10-13
KR970009976B1 (ko) 1997-06-19

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