KR950001984A - 반도체장치의 소자분리방법 - Google Patents

반도체장치의 소자분리방법 Download PDF

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Publication number
KR950001984A
KR950001984A KR1019930010568A KR930010568A KR950001984A KR 950001984 A KR950001984 A KR 950001984A KR 1019930010568 A KR1019930010568 A KR 1019930010568A KR 930010568 A KR930010568 A KR 930010568A KR 950001984 A KR950001984 A KR 950001984A
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South Korea
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buffer layer
polysilicon
opening
film
etched
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KR1019930010568A
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KR960011861B1 (ko
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양원석
황민욱
황창규
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김광호
삼성전자 주식회사
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Priority to KR1019930010568A priority Critical patent/KR960011861B1/ko
Priority to US08/118,818 priority patent/US5358893A/en
Publication of KR950001984A publication Critical patent/KR950001984A/ko
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Publication of KR960011861B1 publication Critical patent/KR960011861B1/ko

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H01L21/76213—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose
    • H01L21/76216—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose introducing electrical active impurities in the local oxidation region for the sole purpose of creating channel stoppers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/32—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/117—Oxidation, selective

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Element Separation (AREA)
  • Local Oxidation Of Silicon (AREA)

Abstract

광해상도 이하의 크기를 갖고, 분리 특성이 양호한 반도체 장치의 소자 분리 방버이 개시되어 있다, 반도체 기판상에 버퍼층을 형성한 후, 상기 버퍼층상에 소자 분리 영역을 한정하고 상기 버퍼층 일부를 노출시키는 개구부를 갖는 산화 방지 패턴을 형성한다. 다음에, 상기 노출된 버퍼층의 일부를 등방성 식각하여 상기 개구부의 주변 하부에 언더커팅부위를 형성하고, 상기 개구부의 측벽에 언더커팅부를 매립하는 산화방지 스페이서를 형성한 후, 상기 개구부에 의해 노출된 버퍼층의 일부 및 상기 개구부 부위의 반도체 기판의 표면부위를 부분적으로 산화하여 필드 산화막을 형성한다. 버즈 비크의 크기가 감소되어, 양호한 분리 특성을 미세한 크기의 필드 산화막을 형성할 수 있다.

Description

반도체장치의 소자분리방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제7도 내지 제12도는 본 발명의 제1실시예에 따른 소자 분리 방법을 나타내기 위한 단면도들이다.

Claims (3)

  1. 고집적 반도체 장치의 소자분리 영역 형성 방법에 있어서, 반도체 기판상에 제1산화막과 제1폴리실리콘막과 제1산화방지막을 순차적으로 형성한 다음, 활성 영역과 비활성 영역을 정의하고, 상기 비활성 영역의 제1산화방지막을 식각한 다음, 상기 제1폴리실리콘막의 일부를 등방성식각하고 상기 식각된 제1산화방지막 측면과 제1폴리실리콘 식각 경사측면에 측벽을 형성한 후, 상기 측벽을 마스크로 제1폴리실리콘잔여층을 식각한 후, 열산화하여 비활성 영역을 형성하여 소자를 분리하는 반도체 제조 방법.
  2. 제1항에 있어서, 상기 제1폴리실리콘막을 습식식각으로 경사각을 갖도록 하는 것을 특징으로 하는 반도체 제조 방법.
  3. 제1항에 있어서, 제1폴리실리콘 잔여층과 기판을 식각하는 것을 특징으로 하느 반도체 제조 방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019930010568A 1993-06-10 1993-06-10 반도체장치의 소자 분리 방법 KR960011861B1 (ko)

Priority Applications (2)

Application Number Priority Date Filing Date Title
KR1019930010568A KR960011861B1 (ko) 1993-06-10 1993-06-10 반도체장치의 소자 분리 방법
US08/118,818 US5358893A (en) 1993-06-10 1993-09-10 Isolation method for semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019930010568A KR960011861B1 (ko) 1993-06-10 1993-06-10 반도체장치의 소자 분리 방법

Publications (2)

Publication Number Publication Date
KR950001984A true KR950001984A (ko) 1995-01-04
KR960011861B1 KR960011861B1 (ko) 1996-09-03

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US (1) US5358893A (ko)
KR (1) KR960011861B1 (ko)

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Publication number Priority date Publication date Assignee Title
KR100448232B1 (ko) * 1997-12-27 2004-11-16 주식회사 하이닉스반도체 반도체 장치의 소자 분리막 형성방법

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WO2011111498A1 (ja) * 2010-03-08 2011-09-15 株式会社日立国際電気 半導体装置の製造方法及び基板処理装置
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100448232B1 (ko) * 1997-12-27 2004-11-16 주식회사 하이닉스반도체 반도체 장치의 소자 분리막 형성방법

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US5358893A (en) 1994-10-25
KR960011861B1 (ko) 1996-09-03

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