KR940007977A - 에피택셜 웨이퍼 및 그 제조방법 - Google Patents

에피택셜 웨이퍼 및 그 제조방법 Download PDF

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KR940007977A
KR940007977A KR1019930018987A KR930018987A KR940007977A KR 940007977 A KR940007977 A KR 940007977A KR 1019930018987 A KR1019930018987 A KR 1019930018987A KR 930018987 A KR930018987 A KR 930018987A KR 940007977 A KR940007977 A KR 940007977A
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wafer
epitaxial layer
epitaxial
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forming
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다까히사 구사까
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오가 노리오
소니 가부시끼가이샤
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/36—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the concentration or distribution of impurities in the bulk material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02381—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
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    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02441—Group 14 semiconducting materials
    • H01L21/0245—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/0257—Doping during depositing
    • H01L21/02573—Conductivity type
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
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    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
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    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/322—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections
    • H01L21/3221—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections of silicon bodies, e.g. for gettering
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Abstract

불순물 농도가 안정된 에피택셜층을 형성하고, 또한 중금속계의 오염을 적게 하여, 특성이 균일하고 또한 우수한 반도체장치를 형성할 수 있는 에피택셜 웨이퍼를 제공한다.
Si 웨이퍼(11)에 As(12) 및 C(13)를 이온주입한 후, Si웨이퍼(11)상에 에피택셜층(14)을 형성한다. As는 확산계수가 작으므로, Si 웨이퍼(11)로부터 에피택셜층(14)에의 As(12)의 확산이 적고, 또한 As(12)의 이온주입에 의해 Si웨이퍼(11)의 불순물 농도가 균일에 근접하고 있다. 또한, C(13)는 Si웨이퍼(11)에 게터링사이트를 형성한다.

Description

에피택셜 웨이퍼 및 그 제조방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본 발명의 제1실시예에서 제조한 에피택셜 웨이퍼의 측단면도,
제3도는 에피택셜층의 막두께와 CCD의 셔터전압과의 관계를 나타낸 그래프,
제4도는 액피택셜층의 불순물 농도와 CCD의 셔터전압과의 관계를 나타낸 그래프.

Claims (3)

  1. 기판웨이퍼상에 에피택셜층이 형성되어 있는 에피택셜웨이퍼의 제조방법에 있어서, 상기 기판웨이퍼에 As 및 C를 도입하는 공정과, 상기 도입의 후에, 상기 기판웨이퍼상에 상기 에피택셜층을 형성하는 공정을 가지는 것을 특징으로 하는 에피택셜 웨이퍼의 제조방법.
  2. 기판웨이퍼상에 하층측의 제1의 에피택셜층과 상층측의 제2의 에피택셜층이 순차 적층되어 있는 에피택셜웨이퍼에 있어서, 상기 제1의 에피택셜층의 불순물 농도가 상기 제2의 에피택셜층의 불순물 농도의 10배이상이며, 상기 제1의 에피택셜층 중의 상기 불순물로서 As 또는 Sb가 사용되고 있으며, 상기 제2의 에피택셜층의 막두께가 4~10㎛인 것을 특징으로 하는 에피택셜 웨이퍼.
  3. 기판웨이퍼상에 하층측의 제1의 에피택셜층과 상층측의 제2의 에피택셜층이 순차 적층되어 있는 에피택셜웨이퍼의 제조방법에 있어서, 불순물로서의 As 또는 Sb의 농도가 상기 제2의 에피택셜층의 불순물 농도의 10배 이상인 상기 제1의 에피택셜층을 상기 기판웨이퍼상에 형성하는 공정과, 막두께가 4~10㎛인 상기 제2의 에피택셜층을 상기 제1의 에피택셜층상에 형성하는 공정을 가지는 것을 특징으로 하는 에피택셜 웨이퍼의 제조방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019930018987A 1992-09-25 1993-09-20 에피택셜 웨이퍼 및 그 제조방법 KR100250183B1 (ko)

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Application Number Priority Date Filing Date Title
JP28081892 1992-09-25
JP92-280,818 1992-09-25
JP92-355,507 1992-12-18
JP35550792A JP3353277B2 (ja) 1992-09-25 1992-12-18 エピタキシャルウェハの製造方法

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KR940007977A true KR940007977A (ko) 1994-04-28
KR100250183B1 KR100250183B1 (ko) 2000-05-01

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR19980071448A (ko) * 1997-02-26 1998-10-26 가나이 츠토무 반도체웨이퍼, 반도체웨이퍼의 제조방법, 반도체장치 및 반도체 장치의 제조방법
KR20030040951A (ko) * 2001-11-17 2003-05-23 주식회사 실트론 고품질 에피택셜 웨이퍼 및 그의 제조방법
KR100739099B1 (ko) * 2005-12-21 2007-07-12 주식회사 실트론 에피택셜 웨이퍼 및 그 제조방법
KR101288263B1 (ko) * 2009-05-28 2013-07-26 도요타 지도샤（주） 다이오드의 제조 방법 및 다이오드

Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3384506B2 (ja) * 1993-03-30 2003-03-10 ソニー株式会社 半導体基板の製造方法
US6181721B1 (en) * 1996-05-20 2001-01-30 Sdl, Inc. Visible wavelength, semiconductor optoelectronic device with a high power broad, significantly laterally uniform, diffraction limited output beam
JPH09321266A (ja) * 1996-05-27 1997-12-12 Sony Corp 半導体基板の製造方法及び固体撮像装置の製造方法
JPH11204771A (ja) * 1998-01-07 1999-07-30 Sony Corp 半導体基板の製造方法及び固体撮像装置の製造方法
JPH11297976A (ja) * 1998-04-07 1999-10-29 Sony Corp エピタキシャル半導体基板およびその製造方法ならびに半導体装置の製造方法ならびに固体撮像装置の製造方法
KR100588217B1 (ko) * 2004-12-31 2006-06-08 동부일렉트로닉스 주식회사 반도체 소자의 게이트 산화막 형성 방법
KR100654354B1 (ko) * 2005-07-25 2006-12-08 삼성전자주식회사 게더링 기능을 가지는 저결함 에피택셜 반도체 기판, 이를이용한 이미지 센서 및 이의 제조 방법
EP1833100A2 (en) * 2006-03-06 2007-09-12 Matsushita Electric Industrial Co., Ltd. Light-detecting device and manufacturing method thereof
JP2007273959A (ja) * 2006-03-06 2007-10-18 Matsushita Electric Ind Co Ltd 光検出素子及びその製造方法
KR100793607B1 (ko) * 2006-06-27 2008-01-10 매그나칩 반도체 유한회사 에피텍셜 실리콘 웨이퍼 및 그 제조방법
JP2009038124A (ja) * 2007-07-31 2009-02-19 Shin Etsu Handotai Co Ltd エピタキシャルウェーハの製造方法およびエピタキシャルウェーハ
JP5401808B2 (ja) * 2008-03-05 2014-01-29 株式会社Ｓｕｍｃｏ シリコン基板とその製造方法
JP5401809B2 (ja) * 2008-03-05 2014-01-29 株式会社Ｓｕｍｃｏ シリコン基板とその製造方法
JP5391651B2 (ja) * 2008-10-30 2014-01-15 信越半導体株式会社 半導体基板の製造方法
JP2010283193A (ja) * 2009-06-05 2010-12-16 Sumco Corp 半導体デバイス向け半導体基板の製造方法、半導体デバイス向け半導体基板の製造装置
JP2010283220A (ja) * 2009-06-05 2010-12-16 Sumco Corp 固体撮像素子用エピタキシャル基板の製造方法、固体撮像素子の製造方法
JP5546222B2 (ja) * 2009-12-04 2014-07-09 キヤノン株式会社 固体撮像装置及び製造方法
JP5772491B2 (ja) 2011-10-20 2015-09-02 信越半導体株式会社 エピタキシャルウエーハ及びその製造方法
CN104217929A (zh) * 2014-10-11 2014-12-17 王金 一种外延片及其加工方法

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4247859A (en) * 1974-11-29 1981-01-27 Westinghouse Electric Corp. Epitaxially grown silicon layers with relatively long minority carrier lifetimes
US4170501A (en) * 1978-02-15 1979-10-09 Rca Corporation Method of making a semiconductor integrated circuit device utilizing simultaneous outdiffusion and autodoping during epitaxial deposition
JPS55153365A (en) * 1979-05-17 1980-11-29 Toshiba Corp Manufacturing method of semiconductor device
JPS6084813A (ja) * 1983-10-17 1985-05-14 Toshiba Corp 半導体装置の製造方法
JP2555702B2 (ja) * 1988-07-25 1996-11-20 日本電装株式会社 空調装置の騒音低減装置

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR19980071448A (ko) * 1997-02-26 1998-10-26 가나이 츠토무 반도체웨이퍼, 반도체웨이퍼의 제조방법, 반도체장치 및 반도체 장치의 제조방법
KR20030040951A (ko) * 2001-11-17 2003-05-23 주식회사 실트론 고품질 에피택셜 웨이퍼 및 그의 제조방법
KR100739099B1 (ko) * 2005-12-21 2007-07-12 주식회사 실트론 에피택셜 웨이퍼 및 그 제조방법
KR101288263B1 (ko) * 2009-05-28 2013-07-26 도요타 지도샤（주） 다이오드의 제조 방법 및 다이오드

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KR100250183B1 (ko) 2000-05-01
JPH06163410A (ja) 1994-06-10
JP3353277B2 (ja) 2002-12-03

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