KR100588217B1 - 반도체 소자의 게이트 산화막 형성 방법 - Google Patents
반도체 소자의 게이트 산화막 형성 방법 Download PDFInfo
- Publication number
- KR100588217B1 KR100588217B1 KR1020040117846A KR20040117846A KR100588217B1 KR 100588217 B1 KR100588217 B1 KR 100588217B1 KR 1020040117846 A KR1020040117846 A KR 1020040117846A KR 20040117846 A KR20040117846 A KR 20040117846A KR 100588217 B1 KR100588217 B1 KR 100588217B1
- Authority
- KR
- South Korea
- Prior art keywords
- oxide film
- implant
- gate oxide
- substrate
- sacrificial oxide
- Prior art date
Links
- 238000000034 method Methods 0.000 title claims abstract description 40
- 239000004065 semiconductor Substances 0.000 title claims abstract description 13
- 239000007943 implant Substances 0.000 claims abstract description 31
- 239000000758 substrate Substances 0.000 claims abstract description 21
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims abstract description 13
- 239000001257 hydrogen Substances 0.000 claims abstract description 8
- 229910052739 hydrogen Inorganic materials 0.000 claims abstract description 8
- 238000004140 cleaning Methods 0.000 claims abstract description 7
- 238000005468 ion implantation Methods 0.000 claims abstract description 7
- 238000001039 wet etching Methods 0.000 claims abstract description 7
- 230000003647 oxidation Effects 0.000 claims abstract description 5
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 5
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 5
- 239000001301 oxygen Substances 0.000 claims description 5
- 229910052760 oxygen Inorganic materials 0.000 claims description 5
- 238000010438 heat treatment Methods 0.000 claims description 4
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 3
- 229910001873 dinitrogen Inorganic materials 0.000 claims description 3
- 238000010926 purge Methods 0.000 claims description 2
- 230000015572 biosynthetic process Effects 0.000 claims 1
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 4
- 239000000126 substance Substances 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 2
- 235000013399 edible fruits Nutrition 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 2
- MYMOFIZGZYHOMD-UHFFFAOYSA-N Dioxygen Chemical compound O=O MYMOFIZGZYHOMD-UHFFFAOYSA-N 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 229910001882 dioxygen Inorganic materials 0.000 description 1
- 238000007599 discharging Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823462—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28158—Making the insulator
- H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
- H01L21/28211—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation in a gaseous ambient using an oxygen or a water vapour, e.g. RTO, possibly through a layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02041—Cleaning
- H01L21/02043—Cleaning before device manufacture, i.e. Begin-Of-Line process
- H01L21/02046—Dry cleaning only
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
- H01L21/0223—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
- H01L21/02233—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer
- H01L21/02236—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor
- H01L21/02238—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor silicon in uncombined form, i.e. pure silicon
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
- H01L21/02255—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by thermal treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
- H01L21/02299—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment
- H01L21/02307—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment treatment by exposure to a liquid
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
- H01L21/02299—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment
- H01L21/02312—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment treatment by exposure to a gas or vapour
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/30604—Chemical etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/314—Inorganic layers
- H01L21/316—Inorganic layers composed of oxides or glassy oxides or oxide based glass
- H01L21/3165—Inorganic layers composed of oxides or glassy oxides or oxide based glass formed by oxidation
- H01L21/31654—Inorganic layers composed of oxides or glassy oxides or oxide based glass formed by oxidation of semiconductor materials, e.g. the body itself
- H01L21/31658—Inorganic layers composed of oxides or glassy oxides or oxide based glass formed by oxidation of semiconductor materials, e.g. the body itself by thermal oxidation, e.g. of SiGe
- H01L21/31662—Inorganic layers composed of oxides or glassy oxides or oxide based glass formed by oxidation of semiconductor materials, e.g. the body itself by thermal oxidation, e.g. of SiGe of silicon in uncombined form
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823493—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- High Energy & Nuclear Physics (AREA)
- Crystallography & Structural Chemistry (AREA)
- Health & Medical Sciences (AREA)
- Toxicology (AREA)
- Formation Of Insulating Films (AREA)
- Cleaning Or Drying Semiconductors (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
반도체 소자의 게이트 산화막 형성 방법을 개시한다. 본 방법은, (a) 반도체 기판에 웰 형성을 위한 이온 주입 공정을 거친 임플란트 희생 산화막을 습식 식각 공정 및 세정 공정을 통해 소정의 두께를 남기고 제거하는 단계, (b) 상기 기판을 수소 분위기에서 베이킹하여 남아 있는 상기 임플란트 희생 산화막을 제거하는 단계, 및 (c) 상기 기판 위에 게이트 산화막을 열산화 공정에 의해 성장시키는 단계;를 포함한다. 따라서, 기판 위에 잔존하는 임플란트 희생 산화막을 완전히 제거할 수 있으므로 막질이 우수하고 두께가 균일한 게이트 산화막을 용이하게 형성할 수 있다.
Description
도 1은 본 발명에 따른 게이트 산화막 형성 방법을 설명하기 위한 공정 흐름도이다.
본 발명은 반도체 소자의 제조 기술에 관한 것으로서, 보다 자세하게는, 반도체 소자의 웰 형성 공정에서 사용한 임플란트 희생 산화막을 제거하고 반도체 기판 위에 새로운 게이트 산화막을 형성하는 방법에 관한 것이다.
종래의 반도체 트랜지스터 소자의 제조 과정 중에서, 게이트 산화막을 형성하기 전에 웰(Well) 형성을 위한 이온 주입 공정을 실시하게 된다. 이 때, 이온 주입에 의해 기판 표면 근처의 결정이 상당히 손상될 수 있다. 이러한 손상을 방지하기 위하여 임플란트 희생 산화막을 형성하게 된다. 이와 같은, 임플란트 희생 산화막은 이온 주입에 대한 장벽으로도 기능하여 불순물이 주입되는 깊이를 제어하는 데에 이용된다.
한편, 임플란트 희생 산화막은 열산화 공정에 의해 형성되는데, 통상 급속 열처리 장치를 이용하여 산화막을 형성하고, 그 후 형성된 산화막을 보다 조밀하게 하기 위하여 어닐링(Annealing)을 행하게 된다.
이와 같이, 임플란트 희생 산화막을 형성한 후에는, 게이트 산화막 및 다결정 실리콘층을 형성하고 이들을 패터닝하여 게이트 전극을 형성하게 된다. 여기서, 게이트 산화막을 형성하기 위해서는, 먼저 이온 주입 공정 등에 의해 오염된 임플란트 희생 산화막을 제거해야 한다. 임플란트 희생 산화막을 제거하기 위하여, 종래에는 불산을 함유한 화학 용액을 이용한 습식 식각 공정을 통해 상당 두께의 임플란트 희생 산화막을 제거하였다. 그 후, 기판을 과수(H2O2)를 함유한 화학 용액으로 세정하게 된다.
한편, 막질이 우수하고 두께가 균일한 게이트 산화막을 성장시키기 위하여는 임플란트 희생 산화막을 완전히 제거하고 편평한 기판의 표면을 노출시켜야 한다. 그러나, 종래의 습식 식각 공정을 이용하는 경우에, 임플란트 희생 산화막을 완전히 제거하기 위하여 지나치게 식각 공정을 진행하게 되면 기판(10)을 손상시키거나 오염시킬 수 있다. 따라서, 약 3 ~ 10Å 정도의 임플란트 희생 산화막을 남긴 상태에서 식각 작업을 종료할 수 있도록 조절해야 한다. 또한 세정 공정을 거친 후 남아 있는 임플란트 희생 산화막의 편평도는 그리 만족할 만한 수준이 되지 못한다. 즉, 습식 식각 공정 및 세정 공정을 통한 종래의 임플란트 희생 산화막의 제거 방법은 균일한 두께의 게이트 산화막을 얻는데 한계가 있다.
본 발명의 목적은 임플란트 희생 산화막을 안전하고 또한 효과적으로 제거함으로써 막질이 우수하고 두께 균일도가 우수한 게이트 산화막을 형성하는 방법을 제공하는 것이다.
본 발명에 따른 반도체 소자의 게이트 산화막 형성 방법은, (a) 반도체 기판에 웰 형성을 위한 이온 주입 공정을 거친 임플란트 희생 산화막을 습식 식각 공정 및 세정 공정을 통해 소정의 두께를 남기고 제거하는 단계, (b) 상기 기판을 수소 분위기에서 베이킹하여 남아 있는 상기 임플란트 희생 산화막을 제거하는 단계, 및 (c) 상기 기판 위에 게이트 산화막을 열산화 공정에 의해 성장시키는 단계;를 포함한다. 따라서, 기판 위에 잔존하는 임플란트 희생 산화막을 완전히 제거할 수 있으므로 막질이 우수하고 두께가 균일한 게이트 산화막을 용이하게 형성할 수 있다.
여기서, (b) 단계는, 열처리 장치의 노(furnace) 내부를 질소 가스를 이용하여 퍼징하여 산소를 제거하는 (b1) 단계와, 상기 노 내부에 수소 가스를 인입하고 소정의 온도에서 베이킹하는 (b2) 단계로 진행된다. 또한 베이킹 온도는 수소 가스가 임플란트 희생 산화막에 포함된 산소와 반응하여 H2O를 형성하는 온도이고, 바람직하게는 약 900℃다.
이하 첨부한 도면을 참조하여 본 발명의 바람직한 실시예를 설명한다.
도 1에서 보듯이, 먼저 종래의 방법과 같이 임플란트 희생 산화막을 불산을 포함하는 화학 용액을 이용하여 상당 두께를 습식 식각한다. 그 후, 기판을 과수(H2O2)를 포함하는 세정액으로 세정한다.(S10) 이와 같이 종래의 습식 방법을 통해 제거되고 남은 임플란트 희생 산화막은 약 3 ~ 10Å 정도의 두께가 된다. 그러나, 앞에서 설명한 바와 같이 남아 있는 임플란트 희생 산화막은 편평도가 좋지 않게 된다.
따라서, 잔존하는 임플란트 희생 산화막을 완전히 제거하기 위한 수소 베이킹 공정을 실시한다. 여기의 수소 베이킹 공정은 다음과 같은 방식으로 진행된다.
즉, 임플란트 희생 산화막의 습식 식각 및 세정 공정을 거친 후, 웨이퍼를 게이트 산화막을 형성하기 위한 열처리 장치의 노(Furnace) 내에 장입한다. 그 후, 노 내부의 산소 기체를 제거하기 위하여 질소 가스를 이용하여 노 내부를 퍼징(purging)한다.(S20) 그리고 나서, 노 온도를 약 900℃까지 승온시키고, 상기 노(furnace)에 연결된 인입관 및 배출관을 통해 수소 가스를 노 내부에 인입 및 방출시킴으로써, 수소 분위기에서 웨이퍼를 베이킹한다.(S30) 이 때, 약 3 ~ 10Å 정도의 두께로 남아 있는 임플란트 희생 산화막에서 산소가 수소와 반응하여 환원된다. 즉, H2O가 생성되어 배출관을 통해 방출된다. 이 때, 베이킹 시간은 잔존하는 산화막의 두께에 따라 적절히 선택될 수 있다. 또한 온도 조건은 산소 및 수소의 반응이 보다 잘 일어날 수 있는 온도로 선택될 수 있다.
이렇게 소정의 시간동안 수소 베이킹 공정을 실시하여 잔존하는 임플란트 희생 산화막을 제거한 다음, 열산화 공정을 진행하여 기판 위에 게이트 산화막을 성장시킨다.(S40) 여기의 열산화 공정은 일반적으로 사용되는 방법에 의하므로 자세한 설명은 생략한다.
본 발명에 따르면, 반도체 기판에 웰을 형성하기 위하여 사용하였던 임플란트 희생 산화막을 기판의 오염 및 손상을 야기하지 않고도 완전히 제거할 수 있다. 또한, 게이트 산화막을 형성하기 전에 기판의 편평도를 균일하게 할 수 있다. 따라서, 막질이 우수하고 두께가 균일한 게이트 산화막을 용이하게 형성할 수 있다.
지금까지 본 발명의 바람직한 실시예에 대해 설명하였으나, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자는 본 발명의 본질적인 특성을 벗어나지 않는 범위 내에서 변형된 형태로 구현할 수 있을 것이다. 그러므로 여기서 설명한 본 발명의 실시예는 한정적인 관점이 아니라 설명적인 관점에서 고려되어야 하고, 본 발명의 범위는 상술한 설명이 아니라 특허청구범위에 나타나 있으며, 그와 동등한 범위 내에 있는 모든 차이점은 본 발명에 포함되는 것으로 해석되어야 한다.
Claims (5)
- (a) 반도체 기판에 웰 형성을 위한 이온 주입 공정을 거친 임플란트 희생 산화막을 습식 식각 공정 및 세정 공정을 통해 소정의 두께를 남기고 제거하는 단계;(b) 상기 기판을 수소 분위기에서 베이킹하여 남아 있는 상기 임플란트 희생 산화막을 제거하는 단계; 및(c) 상기 기판 위에 게이트 산화막을 열산화 공정에 의해 성장시키는 단계;를 포함하는 것을 특징으로 하는 반도체 소자의 게이트 산화막 형성 방법.
- 제1항에 있어서, 상기 (b) 단계는, 열처리 장치의 노(furnace) 내부를 질소 가스를 이용하여 퍼징하여 산소를 제거하는 (b1) 단계와, 상기 노 내부에 수소 가스를 인입하고 소정의 온도에서 베이킹하는 (b2) 단계를 포함하는 것을 특징으로 하는 반도체 소자의 게이트 산화막 형성 방법.
- 제2항에 있어서, 상기 소정의 온도는 수소 가스가 임플란트 희생 산화막에 포함된 산소와 반응하여 H2O를 형성하는 온도인 것을 특징으로 하는 반도체 소자의 게이트 산화막 형성 방법.
- 제3항에 있어서, 상기 H2O의 형성 온도는 약 900℃인 것을 특징으로 하는 반도체 소자의 게이트 산화막 형성 방법.
- 제1항 내지 제4항 중 어느 한 항에 따른 방법에 의해 형성된 게이트 산화막을 포함하는 것을 특징으로 하는 반도체 소자.
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020040117846A KR100588217B1 (ko) | 2004-12-31 | 2004-12-31 | 반도체 소자의 게이트 산화막 형성 방법 |
US11/320,614 US20060148223A1 (en) | 2004-12-31 | 2005-12-30 | Wafer surface pre-treatment with hydrogen for gate oxide formation |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020040117846A KR100588217B1 (ko) | 2004-12-31 | 2004-12-31 | 반도체 소자의 게이트 산화막 형성 방법 |
Publications (1)
Publication Number | Publication Date |
---|---|
KR100588217B1 true KR100588217B1 (ko) | 2006-06-08 |
Family
ID=36641092
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1020040117846A KR100588217B1 (ko) | 2004-12-31 | 2004-12-31 | 반도체 소자의 게이트 산화막 형성 방법 |
Country Status (2)
Country | Link |
---|---|
US (1) | US20060148223A1 (ko) |
KR (1) | KR100588217B1 (ko) |
Family Cites Families (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4863561A (en) * | 1986-12-09 | 1989-09-05 | Texas Instruments Incorporated | Method and apparatus for cleaning integrated circuit wafers |
EP0496605B1 (en) * | 1991-01-24 | 2001-08-01 | Wako Pure Chemical Industries Ltd | Surface treating solutions for semiconductors |
US5352636A (en) * | 1992-01-16 | 1994-10-04 | Applied Materials, Inc. | In situ method for cleaning silicon surface and forming layer thereon in same chamber |
JP2560178B2 (ja) * | 1992-06-29 | 1996-12-04 | 九州電子金属株式会社 | 半導体ウェーハの製造方法 |
JP3353277B2 (ja) * | 1992-09-25 | 2002-12-03 | ソニー株式会社 | エピタキシャルウェハの製造方法 |
JPH07216392A (ja) * | 1994-01-26 | 1995-08-15 | Daikin Ind Ltd | 洗浄剤及び洗浄方法 |
US5783495A (en) * | 1995-11-13 | 1998-07-21 | Micron Technology, Inc. | Method of wafer cleaning, and system and cleaning solution regarding same |
EP0871209A4 (en) * | 1995-11-15 | 2006-02-08 | Daikin Ind Ltd | PLATELET CLEANING SOLUTION AND METHOD FOR PRODUCING THE SAME |
US6271151B1 (en) * | 1997-06-30 | 2001-08-07 | Advanced Micro Devices, Inc. | Method and apparatus for controlling the thickness of a gate oxide in a semiconductor manufacturing process |
US6749687B1 (en) * | 1998-01-09 | 2004-06-15 | Asm America, Inc. | In situ growth of oxide and silicon layers |
US6171911B1 (en) * | 1999-09-13 | 2001-01-09 | Taiwan Semiconductor Manufacturing Company | Method for forming dual gate oxides on integrated circuits with advanced logic devices |
US6927176B2 (en) * | 2000-06-26 | 2005-08-09 | Applied Materials, Inc. | Cleaning method and solution for cleaning a wafer in a single wafer process |
KR100499211B1 (ko) * | 2001-11-13 | 2005-07-07 | 가부시키가이샤 히다치 고쿠사이 덴키 | 반도체 장치의 제조 방법 및 기판 처리 장치 |
JPWO2004003995A1 (ja) * | 2002-06-27 | 2005-11-04 | 株式会社日立国際電気 | 基板処理装置および半導体装置の製造方法 |
-
2004
- 2004-12-31 KR KR1020040117846A patent/KR100588217B1/ko not_active IP Right Cessation
-
2005
- 2005-12-30 US US11/320,614 patent/US20060148223A1/en not_active Abandoned
Also Published As
Publication number | Publication date |
---|---|
US20060148223A1 (en) | 2006-07-06 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US7977246B2 (en) | Thermal annealing method for preventing defects in doped silicon oxide surfaces during exposure to atmosphere | |
TWI458010B (zh) | Etching method, etching system and recording medium | |
JP3815937B2 (ja) | 半導体装置のコンタクトホール埋め込み方法 | |
JP2001319918A (ja) | 基板表面の処理方法、半導体素子向け基板表面の処理方法 | |
US20140083979A1 (en) | Deposit removal method | |
TW201608605A (zh) | 改質處理方法及半導體裝置之製造方法 | |
JPH04226017A (ja) | 低欠陥ポリシリコン集積回路の製造方法 | |
US20150064925A1 (en) | Deposit removing method and gas processing apparatus | |
KR100588217B1 (ko) | 반도체 소자의 게이트 산화막 형성 방법 | |
JP5508701B2 (ja) | 半導体処理装置及び処理方法 | |
CN105185700B (zh) | 超薄栅氧的制备方法 | |
JP4797358B2 (ja) | 半導体装置の製造方法 | |
US20070082494A1 (en) | Method for forming silicide layer | |
JPH11186257A (ja) | 半導体装置の製造方法 | |
JP2003282869A (ja) | 半導体装置の製造方法 | |
JP2001217198A (ja) | 半導体装置の製造方法 | |
KR100687410B1 (ko) | 반도체 소자의 게이트 산화막 형성방법 | |
KR100358572B1 (ko) | 반도체소자의 산화막 형성방법 | |
JP2006108607A (ja) | 半導体素子の絶縁膜形成方法 | |
JPS6074441A (ja) | 半導体層の表面処理方法 | |
KR100657153B1 (ko) | 임플란트 희생 산화막의 형성 방법 | |
KR20060076087A (ko) | 웨이퍼 세정 방법 | |
KR100444166B1 (ko) | 급속 열처리 장치에서의 어닐링 방법 | |
JPH06326058A (ja) | 半導体基板の処理方法 | |
KR20130069935A (ko) | 웨이퍼 제조 방법 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A201 | Request for examination | ||
E701 | Decision to grant or registration of patent right | ||
GRNT | Written decision to grant | ||
FPAY | Annual fee payment |
Payment date: 20110520 Year of fee payment: 6 |
|
LAPS | Lapse due to unpaid annual fee |