US20070082494A1 - Method for forming silicide layer - Google Patents

Method for forming silicide layer Download PDF

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Publication number
US20070082494A1
US20070082494A1 US11/538,061 US53806106A US2007082494A1 US 20070082494 A1 US20070082494 A1 US 20070082494A1 US 53806106 A US53806106 A US 53806106A US 2007082494 A1 US2007082494 A1 US 2007082494A1
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Prior art keywords
substrate
tool system
plasma
fluorine
clean process
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Abandoned
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US11/538,061
Inventor
Yi-Wei Chen
Yi-Yiing Chiang
Yu-Lan Chang
Tzung-Yu Hung
Chao-Ching Hsieh
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United Microelectronics Corp
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United Microelectronics Corp
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Priority to US11/538,061 priority Critical patent/US20070082494A1/en
Assigned to UNITED MICROELECTRONICS CORP. reassignment UNITED MICROELECTRONICS CORP. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: CHANG, YU-LAN, CHEN, YI-WEI, CHIANG, YI-YIING, HSIEH, CHAO-CHING, HUNG, TZUNG-YU
Publication of US20070082494A1 publication Critical patent/US20070082494A1/en
Abandoned legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041—Cleaning
    • H01L21/02057—Cleaning during device manufacture
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
    • H01L21/28044—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
    • H01L21/28052—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer the conductor comprising a silicide layer formed by the silicidation reaction of silicon with a metal layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System
    • H01L21/28518—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System the conductive layers comprising silicides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide

Abstract

A method for forming a metal silicide over a substrate is provided. The method comprises steps of performing a fluorine-containing plasma treatment on the substrate to remove a plurality of residual over the substrate, wherein the fluorine-containing plasma treatment is performed in a first tool system. Then, a vacuum system of the first tool system is broken. The substrate is transferred from the first tool system into a second tool system. A metal silicide layer is formed over the substrate in the second tool system.

Description

    CROSS-REFERENCE TO RELATED APPLICATION
  • This application claims the priority benefits of U.S. provisional application Ser. No. 60/723,503, filed on Oct. 3, 2005. All disclosure of this application is incorporated herein by reference.
    • BACKGROUND OF THE INVENTION
  • 1. Field of Invention
  • The present invention relates to a method for forming a semiconductor. More particularly, the present invention relates to a method for forming a silicide layer.
  • 2. Description of Related Art
  • Usually, silicide is formed on the gates, the source/drain region or the interconnects to lower the contact resistance between the semiconductor devices on a substrate. Since lattice of the silicide is rearranged when it is treated by high-temperature annealing, the defects in the silicide are eliminated, wherein the defects are eliminated, and perfect grains are grown instead of defective grains. A crystalline structure is formed in the silicide after a high-temperature annealing is performed so that the resistance of the silicide is lowered. Hence, the contact resistance can be reduced by forming a silicide layer on the gates, the source/drain region or the interconnects.
  • Typically, before the deposition process for forming the metal silicide layer, a surface clean process is performed over the substrate to remove the impurity residual generated in the previous processes. The conventional method for cleaning the surface of the substrate is wet etching. However, the experimental data shows that the impurity residual cannot be completely removed by the wet etching process. Also, the impurity residual is the cause for generating pits between the metal silicide and the substrate. Furthermore, the pits are the leakage paths in the devices so that the yield of the devices is decreased.
    • SUMMARY OF THE INVENTION
  • Accordingly, at least one objective of the present invention is to provide a method for forming a metal silicide over a substrate capable of preventing the metal silicide from generating pits therein.
  • At least another objective of the present invention is to provide a method for cleaning a surface of a substrate for a later formed metal silicide. By using the method according to the present invention, the impurity residual over the substrate can be completely removed.
  • To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a method for forming a metal silicide over a substrate. The method comprises steps of performing a fluorine-containing plasma treatment on the substrate to remove a plurality of residual over the substrate, wherein the fluorine-containing plasma treatment is performed in a first tool system. Then, a vacuum system of the first tool system is broken. The substrate is transferred from the first tool system into a second tool system. A metal silicide layer is formed over the substrate in the second tool system.
  • According to one embodiment of the present invention, before the metal silicide layer is formed, a soft clean process is performed on the substrate.
  • According to one embodiment of the present invention, the soft clean process is performed by using an inert-gas plasma.
  • According to one embodiment of the present invention, the inert-gas plasma includes an argon-gas plasma.
  • According to one embodiment of the present invention, the soft clean process is performed in the second tool system.
  • According to one embodiment of the present invention, the fluorine-containing plasma treatment is selected from a group consisting of NF3 plasma, NF3/NH3 plasma, NF3/H2 plasma and SF6/H2O plasma.
  • According to one embodiment of the present invention, the fluorine-containing plasma treatment is performed at a pressure of about 30 mTorr with a power of about 20˜300 Watt.
  • According to one embodiment of the present invention, the flow rate of a fluorine-containing gas of the fluorine-containing plasma treatment is about 5˜25 sccm.
  • According to one embodiment of the present invention, the metal silicide is made of cobalt silicide.
  • The present invention further provides a method for cleaning a surface of a substrate before a silicidation process is performed over the substrate. The method comprises steps of performing a dry clean process in an etching tool system and then performing a soft clean process in a deposition tool system. The silicidation process is going to be performed on the substrate in the deposition tool system.
  • According to one embodiment of the present invention, the dry clean process is performed by a fluorine-containing plasma.
  • According to one embodiment of the present invention, the fluorine-containing plasma is selected from a group consisting of NF3 plasma, NF3/NH3 plasma, NF3/H2 plasma and SF6/H2O plasma.
  • According to one embodiment of the present invention, the fluorine-containing plasma is performed at a pressure of about 30 mTorr with a power of about 20˜300 Watt.
  • According to one embodiment of the present invention, the flow rate of a fluorine-containing gas of the fluorine-containing plasma is about 5˜25 sccm.
  • According to one embodiment of the present invention, before the soft clean process and after the dry clean process, the method further comprise steps of breaking a vacuum system of the etching tool system and then transferring the substrate from the etching tool system into the deposition tool system.
  • In the present invention, the dry clean process with the use of the fluorine-containing plasma removes not only the polymer and oxide on the substrate but also remove a portion of the silicon of the substrate so that the surface of the substrate is clean for later formed metal layer. Furthermore, the fluorine-containing plasma can repair silicon dangling bonds, which is one of the reasons to generate the pits in the metal silicide layer, on the surface of the substrate. In addition, since the dry clean process is performed in a tool system different from that for performing the deposition process of the metal layer, the impurity residual etched away from the substrate does not contaminate the wall of the tool system for performing the deposition process. Also, before the deposition process is performed, a soft clean with the operation power smaller than that of the dry clean process is performed to remove the possible oxide generated during the transferring procedure so that the surface of the substrate can be completely cleaned.
  • In order to make the aforementioned and other objects, features and advantages of the present invention comprehensible, a preferred embodiment accompanied with figures is described in detail below.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.
  • FIG. 1 is a process flow diagram, schematically illustrating a method for forming a metal silicide over a substrate according to one embodiment of the present invention.
  • FIG. 2 is a process flow showing a method for forming the metal silicide layer.
    • DESCRIPTION OF EMBODIMENTS
  • FIG. 1 is a process flow diagram, schematically illustrating a method for forming a metal silicide over a substrate according to one embodiment of the present invention. As shown in FIG. 1, a substrate 100 having devices formed thereon is provided. The devices can be a metal-oxide semiconductor composed of a gate and a source/drain region adjacent to the gate, for example. Thereafter, in the step S201, a dry clean process is performed on the substrate 100. It should be noticed that the dry clean process is performed in a first tool system 102. The first tool system 102 can be, for example, an etching tool system. The purpose for performing the dry clean process is to remove the residual over the substrate 100 after the devices are formed. The residual can be the manufacturing by-product such as polymer, oxide or implant species residual. Furthermore, the dry clean process can be a fluorine-containing plasma treatment. That is, the dry clean process is performed by using a fluorine-containing plasma. Moreover, the fluorine-containing plasma can be selected from a group consisting of NF3 plasma, NF3/NH3 plasma, NF3/H2 plasma and SF6/H2O plasma. Also, the fluorine-containing plasma is performed at a pressure of about 30 mTorr with an operation power of about 20˜300 Watt. Further, the flow rate of the fluorine-containing gas for generating the fluorine-containing plasma is about 5˜25 sccm.
  • Then, in the step S203, the substrate 100 is transferred from the first tool system 102 in to a second tool system 104. During the step S203, the vacuum system of the first tool system 102 is broken and then the substrate 100 is transferred into the second tool system 104 in which a metal silicide layer are going to be formed over the substrate 100. Furthermore, the second tool system 104 can be, for example, a deposition tool system.
  • Before the metal silicide layer is formed over the substrate 100, a soft clean process (step S205) is performed on the substrate 100 for further removing the oxide impurity generated during the transferring procedure. The soft clean process can be performed in the deposition tool system 104 as shown in FIG. 1. Furthermore, the soft clean process can be performed by using an inert-gas plasma such as an argon-gas plasma. In addition, the operation power for performing the soft clean process is smaller than that of the dry clean process. Also, the flow rate of the argon gas of the soft clean process is about 0˜10 sccm and the soft clean process is performed for about 5˜20 seconds.
  • Thereafter, in the step S207, a metal silicide layer is formed over the substrate 100 in the second tool system. The metal silicide layer can be, for example, made of cobalt silicide.
  • FIG. 2 is a process flow showing a method for forming the metal silicide layer. Taking metal cobalt as an example, the method for forming the metal silicide layer (step S207 in FIG. 1) is detail described herein. As shown in FIG. 2, in the step S301, a metal layer, such as a cobalt layer, is formed over the substrate 100. The method of forming the metal layer can be performed by a conventional method known to the skilled in the art. In this example, the metal layer is formed by sputtering.
  • Then, in the step S303, a first thermal process is used to convert portions of the metal layer above the gate electrodes and the source/drain regions of the devices into a metal silicide layer. In this embodiment, the metal silicide layer can be, for example, made of cobalt silicide. The remaining metal layer, which is not converted into the metal silicide layer, is removed to expose the metal silicide layer (step S305). The method of removing the metal layer can be performed by a conventional method known to the skilled in the art. In this example, the removal of the metal layer is by wet etching.
  • Thereafter, in the step S307, a second thermal process is performed to convert the metal silicide layer, such as the cobalt silicide layer, into a CoSi2 layer. In the conventional process for forming the metal silicide over a substrate, the substrate is pre-cleaned by using the wet etching process. However, the impurity residual, such as the polymer by-product or oxide cannot be completely removed. Hence, after the second thermal process is performed on the substrate to convert the cobalt silicide into CoSi2, the impurity residual would lead to pits at the boundary between CoSi2 and the substrate. Therefore, the pits become the cause of the leakage path and the device yield is decreased. In the present invention, the dry clean process with the use of the fluorine-containing plasma removes not only the polymer and oxide on the substrate but also remove a portion of the silicon of the substrate so that the surface of the substrate is clean for later formed metal layer. Furthermore, the fluorine-containing plasma can repair silicon dangling bonds, which is one of the reasons to generate the pits in CoSi2, on the surface of the substrate. In addition, since the dry clean process is performed in a tool system different from that for performing the deposition process of the metal layer, the impurity residual etched away from the substrate does not contaminate the wall of the tool system for performing the deposition process. Also, before the deposition process is performed a soft clean with the operation power smaller than that of the dry clean process is performed to remove the possible oxide generated during the transferring procedure so that the surface of the substrate can be completely cleaned.
  • The present invention has been disclosed above in the preferred embodiments, but is not limited to those. It is known to persons skilled in the art that some modifications and innovations may be made without departing from the spirit and scope of the present invention. Therefore, the scope of the present invention should be defined by the following claims.

Claims (15)

1. A method for forming a metal silicide over a substrate, comprising:
performing a fluorine-containing plasma treatment on the substrate to remove a plurality of residual over the substrate, wherein the fluorine-containing plasma treatment is performed in a first tool system;
breaking a vacuum system of the first tool system;
transferring the substrate from the first tool system into a second tool system; and
forming a metal silicide layer over the substrate in the second tool system.
2. The method of claim 1, wherein, before the metal silicide layer is formed, a soft clean process is performed on the substrate.
3. The method of claim 2, wherein the soft clean process is performed by using an inert-gas plasma.
4. The method of claim 3, wherein the inert-gas plasma includes an argon-gas plasma.
5. The method of claim 2, wherein the soft clean process is performed in the second tool system.
6. The method of claim 1, wherein the fluorine-containing plasma treatment is selected from a group consisting of NF3 plasma, NF3/NH3 plasma, NF3/H2 plasma and SF6/H2O plasma.
7. The method of claim 1, wherein the fluorine-containing plasma treatment is performed at a pressure of about 30 mTorr with a power of about 20˜300 Watt.
8. The method of claim 1, wherein the flow rate of a fluorine-containing gas of the fluorine-containing plasma treatment is about 5˜25 sccm.
9. The method of claim 1, wherein the metal silicide is made of cobalt silicide.
10. A method for cleaning a surface of a substrate before a silicidation process is performed over the substrate, comprising:
performing a dry clean process in an etching tool system; and
performing a soft clean process in a deposition tool system, wherein the silicidation process is going to be performed on the substrate in the deposition tool system.
11. The method of claim 10, wherein the dry clean process is performed by a fluorine-containing plasma.
12. The method of claim 11, wherein the fluorine-containing plasma is selected from a group consisting of NF3 plasma, NF3/NH3 plasma, NF3/H2 plasma and SF6/H2O plasma.
13. The method of claim 11, wherein the fluorine-containing plasma is performed at a pressure of about 30 mTorr with a power of about 20˜300 Watt.
14. The method of claim 11, wherein the flow rate of a fluorine-containing gas of the fluorine-containing plasma is about 5˜25 sccm.
15. The method of claim 10, before the soft clean process and after the dry clean process, further comprising:
breaking a vacuum system of the etching tool system; and
transferring the substrate from the etching tool system into the deposition tool system.
US11/538,061 2005-10-03 2006-10-03 Method for forming silicide layer Abandoned US20070082494A1 (en)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102122613A (en) * 2010-01-08 2011-07-13 中芯国际集成电路制造(上海)有限公司 Method for forming self-aligning metal silicide
CN104347393A (en) * 2013-07-30 2015-02-11 中芯国际集成电路制造(上海)有限公司 Method for removing natural oxidation layer at bottom of contact window
US11450571B2 (en) * 2018-09-27 2022-09-20 Taiwan Semiconductor Manufacturing Company Ltd. Method for manufacturing semiconductor structure

Citations (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5256245A (en) * 1992-08-11 1993-10-26 Micron Semiconductor, Inc. Use of a clean up step to form more vertical profiles of polycrystalline silicon sidewalls during the manufacture of a semiconductor device
US5656861A (en) * 1990-01-12 1997-08-12 Paradigm Technology, Inc. Self-aligning contact and interconnect structure
US5670421A (en) * 1988-07-27 1997-09-23 Hitachi, Ltd. Process for forming multilayer wiring
US6090707A (en) * 1999-09-02 2000-07-18 Micron Technology, Inc. Method of forming a conductive silicide layer on a silicon comprising substrate and method of forming a conductive silicide contact
US6313042B1 (en) * 1999-09-03 2001-11-06 Applied Materials, Inc. Cleaning contact with successive fluorine and hydrogen plasmas
US20030203606A1 (en) * 2002-04-26 2003-10-30 Kazuyoshi Maekawa Method for manufacturing a semiconductor device
US6930028B1 (en) * 1997-06-09 2005-08-16 Texas Instruments Incorporated Antireflective structure and method
US7229920B2 (en) * 2005-01-11 2007-06-12 United Microelectronics Corp. Method of fabricating metal silicide layer
US20080233747A1 (en) * 2007-03-23 2008-09-25 Texas Instruments Incorporated Semiconductor Device Manufactured Using an Improved Plasma Etch Process for a Fully Silicided Gate Flow Process
US20090061623A1 (en) * 2007-09-05 2009-03-05 United Microelectronics Corp. Method of forming electrical connection structure
US7566662B2 (en) * 2006-04-10 2009-07-28 Renesas Technology Corp. Method of dry cleaning silicon surface prior to forming self-aligned nickel silicide layer

Patent Citations (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5670421A (en) * 1988-07-27 1997-09-23 Hitachi, Ltd. Process for forming multilayer wiring
US5656861A (en) * 1990-01-12 1997-08-12 Paradigm Technology, Inc. Self-aligning contact and interconnect structure
US5256245A (en) * 1992-08-11 1993-10-26 Micron Semiconductor, Inc. Use of a clean up step to form more vertical profiles of polycrystalline silicon sidewalls during the manufacture of a semiconductor device
US6930028B1 (en) * 1997-06-09 2005-08-16 Texas Instruments Incorporated Antireflective structure and method
US6090707A (en) * 1999-09-02 2000-07-18 Micron Technology, Inc. Method of forming a conductive silicide layer on a silicon comprising substrate and method of forming a conductive silicide contact
US6313042B1 (en) * 1999-09-03 2001-11-06 Applied Materials, Inc. Cleaning contact with successive fluorine and hydrogen plasmas
US20030203606A1 (en) * 2002-04-26 2003-10-30 Kazuyoshi Maekawa Method for manufacturing a semiconductor device
US7229920B2 (en) * 2005-01-11 2007-06-12 United Microelectronics Corp. Method of fabricating metal silicide layer
US7566662B2 (en) * 2006-04-10 2009-07-28 Renesas Technology Corp. Method of dry cleaning silicon surface prior to forming self-aligned nickel silicide layer
US20080233747A1 (en) * 2007-03-23 2008-09-25 Texas Instruments Incorporated Semiconductor Device Manufactured Using an Improved Plasma Etch Process for a Fully Silicided Gate Flow Process
US20090061623A1 (en) * 2007-09-05 2009-03-05 United Microelectronics Corp. Method of forming electrical connection structure

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102122613A (en) * 2010-01-08 2011-07-13 中芯国际集成电路制造(上海)有限公司 Method for forming self-aligning metal silicide
CN104347393A (en) * 2013-07-30 2015-02-11 中芯国际集成电路制造(上海)有限公司 Method for removing natural oxidation layer at bottom of contact window
US11450571B2 (en) * 2018-09-27 2022-09-20 Taiwan Semiconductor Manufacturing Company Ltd. Method for manufacturing semiconductor structure

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