CN116313761A - Method for monitoring and preventing oxide residue generated in double grid electrode - Google Patents
Method for monitoring and preventing oxide residue generated in double grid electrode Download PDFInfo
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- CN116313761A CN116313761A CN202310251328.XA CN202310251328A CN116313761A CN 116313761 A CN116313761 A CN 116313761A CN 202310251328 A CN202310251328 A CN 202310251328A CN 116313761 A CN116313761 A CN 116313761A
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- gate oxide
- oxide layer
- wafer
- leaked
- deionized water
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- 238000000034 method Methods 0.000 title claims abstract description 29
- 238000012544 monitoring process Methods 0.000 title claims abstract description 13
- 239000008367 deionised water Substances 0.000 claims abstract description 25
- 229910021641 deionized water Inorganic materials 0.000 claims abstract description 25
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 claims abstract description 25
- 238000004140 cleaning Methods 0.000 claims abstract description 17
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 17
- 239000004065 semiconductor Substances 0.000 claims abstract description 11
- -1 water vapor compound Chemical class 0.000 claims abstract description 10
- 239000000758 substrate Substances 0.000 claims abstract description 9
- 238000000059 patterning Methods 0.000 claims abstract description 7
- 238000005530 etching Methods 0.000 claims description 10
- CURLTUGMZLYLDI-UHFFFAOYSA-N Carbon dioxide Chemical compound O=C=O CURLTUGMZLYLDI-UHFFFAOYSA-N 0.000 claims description 8
- 238000001035 drying Methods 0.000 claims description 7
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 6
- 230000009977 dual effect Effects 0.000 claims description 6
- 229910002092 carbon dioxide Inorganic materials 0.000 claims description 4
- 239000001569 carbon dioxide Substances 0.000 claims description 4
- 239000011261 inert gas Substances 0.000 claims description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 3
- 229910052757 nitrogen Inorganic materials 0.000 claims description 3
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 3
- 230000007547 defect Effects 0.000 description 8
- 150000001875 compounds Chemical class 0.000 description 7
- 238000004519 manufacturing process Methods 0.000 description 4
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 229910052786 argon Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000001307 helium Substances 0.000 description 1
- 229910052734 helium Inorganic materials 0.000 description 1
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28158—Making the insulator
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02041—Cleaning
- H01L21/02057—Cleaning during device manufacture
- H01L21/0206—Cleaning during device manufacture during, before or after processing of insulating layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
- H01L22/12—Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
Abstract
The present invention provides a method for monitoring and preventing oxide residues generated at double gates, the method comprising: providing a wafer, wherein the wafer comprises a semiconductor substrate and a gate oxide layer formed on the surface of the semiconductor substrate; forming a photoresist layer on the surface of the gate oxide layer, and performing patterning treatment on the photoresist layer to leak the gate oxide layer to be etched; and judging whether the surface of the leaked gate oxide layer has a water vapor compound or not through scanning, and if so, cleaning the leaked gate oxide layer by using deionized water. The invention solves the problem that the existing double grid electrode is easy to generate oxide residues.
Description
Technical Field
The present invention relates to the field of semiconductor manufacturing, and more particularly, to a method for monitoring and preventing the generation of oxide residues in dual gates.
Background
With the development of semiconductor integrated circuit manufacturing technology, the critical defect size in the wafer production process is also becoming smaller, and many defects are difficult to capture by a scanner during the production process. In the formation of dual gate, the thickness of the gate oxide layer is 10 at most -1 ～10 0 nm, the conventional scanner is difficult to capture and form at 10 0 Defects (defects) in the gate oxide layer below nm,therefore, it is difficult to monitor the oxide residue during the gate oxide growth stage, and defects are monitored only when the subsequent polysilicon deposition is performed to amplify the defects, but the defects cannot be removed later.
In the wafer double-gate process flow, when the photoresist on the surface of the gate oxide layer is trimmed, the photoresist is cooled from high temperature to low temperature, in this case, a water vapor compound is formed on the surface of the wafer, and the etching of the gate oxide layer is affected by the water vapor compound, so that oxide residues are formed. Therefore, it is important to effectively monitor and prevent the reduction of the residual oxide in time for the vapor compound.
Disclosure of Invention
In view of the above-mentioned drawbacks of the prior art, an object of the present invention is to provide a method for monitoring and preventing the generation of oxide residues on double gates, which is used for solving the problem that the existing double gates are prone to generate oxide residues.
To achieve the above and other related objects, the present invention provides a method of monitoring and preventing the generation of oxide residues at a double gate, the method comprising:
providing a wafer, wherein the wafer comprises a semiconductor substrate and a gate oxide layer formed on the surface of the semiconductor substrate;
forming a photoresist layer on the surface of the gate oxide layer, and performing patterning treatment on the photoresist layer to leak the gate oxide layer to be etched;
and judging whether the surface of the leaked gate oxide layer has a water vapor compound or not through scanning, and if so, cleaning the leaked gate oxide layer by using deionized water.
Optionally, the rotation speed of the gate oxide layer when the deionized water is used for cleaning comprises 1800r/min to 2200r/min.
Optionally, the deionized water comprises carbon dioxide.
Optionally, the time for cleaning with the deionized water comprises 55s to 65s.
Optionally, after the step of cleaning the leaked gate oxide layer with the deionized water, the method further includes a step of etching the leaked gate oxide layer.
Optionally, after cleaning the leaked gate oxide layer and before etching, the method further comprises a step of drying the wafer with the photoresist layer formed thereon.
Optionally, the wafer is dried by using nitrogen or inert gas.
Optionally, drying the wafer by spin-drying.
Optionally, the gate oxide layer is made of silicon oxide.
As described above, the method for monitoring and preventing oxide residues generated on the double gate electrode of the present invention can effectively monitor the moisture compounds by setting up a scanning station after patterning the photoresist and scanning the wafer; the wafer with the water vapor compound is washed by deionized water, so that the generation of oxide residues can be effectively avoided. And since deionized water is inexpensive, it does not affect the wafer, so that the removal of the moisture compound by using deionized water has high economical efficiency.
Drawings
FIG. 1 is a flow chart of a method of monitoring and preventing oxide residue generation at dual gates according to the present invention.
Detailed Description
Other advantages and effects of the present invention will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present invention with reference to specific examples. The invention may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present invention.
Please refer to fig. 1. It should be noted that, the illustrations provided in the present embodiment are merely schematic illustrations of the basic concepts of the present invention, and only the components related to the present invention are shown in the illustrations, rather than being drawn according to the number, shape and size of the components in actual implementation, and the form, number and proportion of each component in actual implementation may be arbitrarily changed, and the layout of the components may be more complex.
As shown in fig. 1, the present embodiment provides a method for monitoring and preventing oxide residues generated at a dual gate, the method comprising:
providing a wafer, wherein the wafer comprises a semiconductor substrate and a gate oxide layer formed on the surface of the semiconductor substrate;
forming a photoresist layer on the surface of the gate oxide layer, and performing patterning treatment on the photoresist layer to leak the gate oxide layer to be etched;
and judging whether the surface of the leaked gate oxide layer has a water vapor compound or not through scanning, and if so, cleaning the leaked gate oxide layer by using deionized water.
In this embodiment, the material of the semiconductor substrate includes silicon or silicon on insulator. In this embodiment, after the patterning process is performed on the photoresist layer, the temperature is reduced from high temperature to low temperature, so that a vapor compound (condensed) is formed on the surface of the leaked gate oxide layer, and the etching of the gate oxide layer is affected by the presence of the vapor compound, so that the etching of the gate oxide layer cannot be performed to generate oxide residues. And a scanning station is set up before etching the gate oxide layer, and the wafer with the photoresist layer is scanned to monitor whether the water vapor compound exists, so that the purpose of effective monitoring is achieved, and the wafer with the water vapor compound is cleaned by using deionized water, so that the purpose of effectively avoiding oxide residues is achieved.
Specifically, the gate oxide layer is made of silicon oxide.
Specifically, the rotation speed of the gate oxide layer when the deionized water is used for cleaning comprises 1800r/min to 2200r/min.
In this embodiment, the rotation speed is 2000r/min when the deionized water is used to clean the gate oxide layer.
Specifically, the deionized water comprises carbon dioxide. In this example, the carbon dioxide concentration is 5 siemens per square centimeter.
Specifically, the time for cleaning by using the deionized water comprises 55-65 s.
In this embodiment, the time for cleaning with the deionized water may be selected according to the need, and optionally, in this embodiment, the cleaning time is 50s.
Specifically, after the leaked gate oxide layer is cleaned by the deionized water, the method further comprises the step of etching the leaked gate oxide layer.
Specifically, after cleaning the leaked gate oxide layer and before etching, the method further comprises a step of drying the wafer with the photoresist layer formed thereon.
In one example, the wafer is dried by using nitrogen or an inert gas. In this embodiment, the inert gas includes argon or helium.
In another example, the wafer is dried by spin-drying.
In summary, in the method for monitoring and preventing the generation of oxide residues on the dual gate electrode, the scanning station is set up after the patterning treatment of the photoresist, and the wafer is scanned to realize the effective monitoring of the vapor compound; the wafer with the water vapor compound is washed by deionized water, so that the generation of oxide residues can be effectively avoided. And since deionized water is inexpensive, it does not affect the wafer, so that the removal of the moisture compound by using deionized water has high economical efficiency. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The above embodiments are merely illustrative of the principles of the present invention and its effectiveness, and are not intended to limit the invention. Modifications and variations may be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the invention. Accordingly, it is intended that all equivalent modifications and variations of the invention be covered by the claims, which are within the ordinary skill of the art, be within the spirit and scope of the present disclosure.
Claims (9)
1. A method of monitoring and preventing oxide residue generation at a dual gate, the method comprising:
providing a wafer, wherein the wafer comprises a semiconductor substrate and a gate oxide layer formed on the surface of the semiconductor substrate;
forming a photoresist layer on the surface of the gate oxide layer, and performing patterning treatment on the photoresist layer to leak the gate oxide layer to be etched;
and judging whether the surface of the leaked gate oxide layer has a water vapor compound or not through scanning, and if so, cleaning the leaked gate oxide layer by using deionized water.
2. The method of claim 1, wherein the speed of rotation of the gate oxide layer when the deionized water is used for cleaning comprises 1800r/min to 2200r/min.
3. The method of claim 1, wherein the deionized water comprises carbon dioxide.
4. The method of claim 1, wherein the time for cleaning with deionized water comprises 55s to 65s.
5. The method of any one of claims 1 to 4, further comprising the step of etching the leaked gate oxide layer after cleaning the leaked gate oxide layer with the deionized water.
6. The method of claim 5, further comprising the step of drying the wafer having the photoresist layer formed thereon after cleaning and before etching the leaked gate oxide layer.
7. The method of claim 6, wherein the wafer is dried by using nitrogen or inert gas.
8. The method of claim 6, wherein the wafer is dried by spin-drying.
9. The method of claim 1, wherein the gate oxide layer comprises silicon oxide.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310251328.XA CN116313761A (en) | 2023-03-14 | 2023-03-14 | Method for monitoring and preventing oxide residue generated in double grid electrode |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310251328.XA CN116313761A (en) | 2023-03-14 | 2023-03-14 | Method for monitoring and preventing oxide residue generated in double grid electrode |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN116313761A true CN116313761A (en) | 2023-06-23 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202310251328.XA Pending CN116313761A (en) | 2023-03-14 | 2023-03-14 | Method for monitoring and preventing oxide residue generated in double grid electrode |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN116313761A (en) |
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2023
- 2023-03-14 CN CN202310251328.XA patent/CN116313761A/en active Pending
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