KR920003414A - 고융점금속 성장방법 - Google Patents

고융점금속 성장방법 Download PDF

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Publication number
KR920003414A
KR920003414A KR1019900010173A KR900010173A KR920003414A KR 920003414 A KR920003414 A KR 920003414A KR 1019900010173 A KR1019900010173 A KR 1019900010173A KR 900010173 A KR900010173 A KR 900010173A KR 920003414 A KR920003414 A KR 920003414A
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South Korea
Prior art keywords
melting point
ion implantation
high melting
point metal
implantation layer
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KR1019900010173A
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English (en)
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KR930002673B1 (ko
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고광옥
박종호
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김광호
삼성전자 주식회사
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Priority to KR1019900010173A priority Critical patent/KR930002673B1/ko
Priority to JP2226834A priority patent/JPH073819B2/ja
Priority to US07/575,627 priority patent/US5180468A/en
Publication of KR920003414A publication Critical patent/KR920003414A/ko
Priority to US08/005,068 priority patent/US5360766A/en
Application granted granted Critical
Publication of KR930002673B1 publication Critical patent/KR930002673B1/ko

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    • H01L21/205—
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H01L21/76879—Filling of holes, grooves or trenches, e.g. vias, with conductive material by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
    • C23C14/22—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the process of coating
    • C23C14/48—Ion implantation
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/04—Coating on selected surface areas, e.g. using masks
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/06—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of metallic material
    • C23C16/16—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of metallic material from metal carbonyl compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268

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  • Chemical & Material Sciences (AREA)
  • Engineering & Computer Science (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Materials Engineering (AREA)
  • Mechanical Engineering (AREA)
  • Metallurgy (AREA)
  • Organic Chemistry (AREA)
  • General Chemical & Material Sciences (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

내용 없음

Description

고융점금속 성장방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제2도는 본 발명에 따른 단면구조도.
제3도는 본 발명에 따른 방법을 보여주는 공정.

Claims (8)

  1. 고융점금속을 성장하는 방법에 있어서, 실리콘기판의 소정영역에 제1이온주입층을 형성하고 상기 제1이온주입층내에 제2이온주입층을 형성하는 제1공정과, 상기 제이온주입층의 표면에 고융점금속 플로라이드 개스를 접촉시켜 고융점금속을 상기 실리콘기판과 접착시키는 제2공정과, 상기 고융점금속 플로라이드와 실란개스의 혼합개스를 화학반응시켜 소정두께의 고융점금속막을 성장시키는 제3공정과, 상기 실리콘기판을 소정온도에서 열처리하는 제4공정이 연속적으로 구비되어 상기 제3공정 및 제4공정이 반복적으로 이루어짐을 특징으로 하는 고융점금속 성장방법.
  2. 제1항에 있어서, 상기 제1공정에서 제1 및 제2이온주입층을 이루는 이온주입불순물이 Si, As, B, P등임을 특징으로 하는 고융점금속 성장방법.
  3. 제1항에 있어서, 상기 제2이온주입층의 실리콘표면 하단에 200 - 500Å 정도의 이온주입에 의한 결합층이 형성됨을 특징으로 하는 고융점금속 성장방법.
  4. 제1항에 있어서, 상기 제3공정에서 고융점금속폴로라이드 개스와 실란개스의 혼합비율을 3:2 정도로 하여 260 - 320℃에서 45초 내지 90초동안 상기 제2이온주입층의 상부에서 1500 - 3000Å 정도의 두께로 고융점금속을 성장시킴을 특징으로 하는 고융점금속 성장방법.
  5. 제1항에 있어서, 상기 제4공정 450℃정도의 온도에서 약2분동안 진행됨을 특징으로 하는 고융점금속 성장방법.
  6. 실리콘기판의 소정영역에 화학기상증착법에 의해 고융점금속을 성장하는 방법에 있어서, 상기 실리콘기판의 소정영역에 불순물을 이온주입하여 제1이온주입층을 형성한후 기판상에 절연막을 도포하는 제1공정과, 상기 절연막을 선택적으로 식각하여 상기 제1이온주입층의 일부표면을 노출시키는 접촉개구를 형성하는 제2공정과, 상기 접촉개구를 통하여 소정의 불순물을 이온주입하여 상기 제1이온주입층내에서 표면에 결함이 있는 제2이온주입층을 형성하는 제3공정과, 상기 접촉개구를 통하여 텅스텐플로라이드 개스를 접촉시켜 상기 제2이온주입층의 표면에서 실리콘을 환원시키는 제4공정과, 상기 접촉개구를 통하여 텅스텐 플로라이드개스와 실란개스를 약 3:2정도의 비율로 280 - 300℃에서 45초 내지 90초 동안 화학반응 분해시켜 1500 - 3000Å 두께의 텅스텐 실리사이드막을 성장시키는 제5고정과, 상기 실리콘기판을 450℃ 정도의 온도에서 약2분동안 열처리하는 제6공정을 구비하여 상기 제5공정 및 제6공정이 반복시행됨을 특징으로 하는 고융점금속 성장방법.
  7. 제6항에 있어서, 상기 이온주입되는 불순물이 Si, As, B, P등임을 특징으로 하는 고융점금속 성장방법.
  8. 제6항에 있어서, 상기 제3공정에서 제2이온주입층의 표면에 200 - 500Å 의 결합부분이 형성됨을 특징으로 하는 고융점금속 형성방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019900010173A 1990-06-05 1990-07-05 고융점금속 성장방법 KR930002673B1 (ko)

Priority Applications (4)

Application Number Priority Date Filing Date Title
KR1019900010173A KR930002673B1 (ko) 1990-07-05 1990-07-05 고융점금속 성장방법
JP2226834A JPH073819B2 (ja) 1990-07-05 1990-08-30 高融点金属成長方法
US07/575,627 US5180468A (en) 1990-07-05 1990-08-31 Method for growing a high-melting-point metal film
US08/005,068 US5360766A (en) 1990-06-05 1993-01-15 Method for growing a high-melting-point metal film

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Application Number Priority Date Filing Date Title
KR1019900010173A KR930002673B1 (ko) 1990-07-05 1990-07-05 고융점금속 성장방법

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KR920003414A true KR920003414A (ko) 1992-02-29
KR930002673B1 KR930002673B1 (ko) 1993-04-07

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US (2) US5180468A (ko)
JP (1) JPH073819B2 (ko)
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Cited By (1)

* Cited by examiner, † Cited by third party
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KR100464393B1 (ko) * 1997-09-02 2005-02-28 삼성전자주식회사 반도체소자의금속배선형성방법

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100464393B1 (ko) * 1997-09-02 2005-02-28 삼성전자주식회사 반도체소자의금속배선형성방법

Also Published As

Publication number Publication date
JPH0467630A (ja) 1992-03-03
KR930002673B1 (ko) 1993-04-07
JPH073819B2 (ja) 1995-01-18
US5360766A (en) 1994-11-01
US5180468A (en) 1993-01-19

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