KR940006577B1 - 반도체장치 및 그 번인방법 - Google Patents

반도체장치 및 그 번인방법 Download PDF

Info

Publication number
KR940006577B1
KR940006577B1 KR1019900009729A KR900009729A KR940006577B1 KR 940006577 B1 KR940006577 B1 KR 940006577B1 KR 1019900009729 A KR1019900009729 A KR 1019900009729A KR 900009729 A KR900009729 A KR 900009729A KR 940006577 B1 KR940006577 B1 KR 940006577B1
Authority
KR
South Korea
Prior art keywords
wiring
integrated circuit
semiconductor device
circuit chip
burn
Prior art date
Application number
KR1019900009729A
Other languages
English (en)
Korean (ko)
Other versions
KR910001975A (ko
Inventor
도루 후루야마
Original Assignee
가부시키가이샤 도시바
아오이 죠이치
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 가부시키가이샤 도시바, 아오이 죠이치 filed Critical 가부시키가이샤 도시바
Publication of KR910001975A publication Critical patent/KR910001975A/ko
Application granted granted Critical
Publication of KR940006577B1 publication Critical patent/KR940006577B1/ko

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851—Testing of integrated circuits [IC]
    • G01R31/2855—Environmental, reliability or burn-in testing
    • G01R31/2856—Internal circuit aspects, e.g. built-in test features; Test chips; Measuring material aspects, e.g. electro migration [EM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76886—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/282—Testing of electronic circuits specially adapted for particular applications not provided for elsewhere
    • G01R31/2831—Testing of materials or semi-finished products, e.g. semiconductor wafers or substrates
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851—Testing of integrated circuits [IC]
    • G01R31/2855—Environmental, reliability or burn-in testing
    • G01R31/286—External aspects, e.g. related to chambers, contacting devices or handlers
    • G01R31/2863—Contacting devices, e.g. sockets, burn-in boards or mounting fixtures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Environmental & Geological Engineering (AREA)
  • General Engineering & Computer Science (AREA)
  • Geometry (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Testing Of Individual Semiconductor Devices (AREA)
  • Tests Of Electronic Circuits (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Dram (AREA)
  • Semiconductor Memories (AREA)
KR1019900009729A 1989-06-30 1990-06-29 반도체장치 및 그 번인방법 KR940006577B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP1169659A JP2585799B2 (ja) 1989-06-30 1989-06-30 半導体メモリ装置及びそのバーンイン方法
JP1-169659 1989-06-30

Publications (2)

Publication Number Publication Date
KR910001975A KR910001975A (ko) 1991-01-31
KR940006577B1 true KR940006577B1 (ko) 1994-07-22

Family

ID=15890557

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019900009729A KR940006577B1 (ko) 1989-06-30 1990-06-29 반도체장치 및 그 번인방법

Country Status (5)

Country Link
US (2) US5138427A (de)
EP (1) EP0405586B1 (de)
JP (1) JP2585799B2 (de)
KR (1) KR940006577B1 (de)
DE (1) DE69030283T2 (de)

Families Citing this family (41)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7511520B2 (en) * 1990-08-29 2009-03-31 Micron Technology, Inc. Universal wafer carrier for wafer level die burn-in
US5663654A (en) * 1990-08-29 1997-09-02 Micron Technology, Inc. Universal wafer carrier for wafer level die burn-in
KR960007478B1 (ko) * 1990-12-27 1996-06-03 가부시키가이샤 도시바 반도체장치 및 반도체장치의 제조방법
JP2925337B2 (ja) * 1990-12-27 1999-07-28 株式会社東芝 半導体装置
EP0494782B1 (de) * 1991-01-11 1997-04-23 Texas Instruments Incorporated Prüf- und Einbrennsystem für einen Wafer und Methode für deren Herstellung
JPH04330755A (ja) * 1991-02-27 1992-11-18 Mitsubishi Electric Corp 半導体集積回路およびそのエージング装置
US5391984A (en) * 1991-11-01 1995-02-21 Sgs-Thomson Microelectronics, Inc. Method and apparatus for testing integrated circuit devices
US5279975A (en) * 1992-02-07 1994-01-18 Micron Technology, Inc. Method of testing individual dies on semiconductor wafers prior to singulation
US5424651A (en) * 1992-03-27 1995-06-13 Green; Robert S. Fixture for burn-in testing of semiconductor wafers, and a semiconductor wafer
US5519193A (en) * 1992-10-27 1996-05-21 International Business Machines Corporation Method and apparatus for stressing, burning in and reducing leakage current of electronic devices using microwave radiation
US5399505A (en) * 1993-07-23 1995-03-21 Motorola, Inc. Method and apparatus for performing wafer level testing of integrated circuit dice
US5654588A (en) * 1993-07-23 1997-08-05 Motorola Inc. Apparatus for performing wafer-level testing of integrated circuits where the wafer uses a segmented conductive top-layer bus structure
US5594273A (en) * 1993-07-23 1997-01-14 Motorola Inc. Apparatus for performing wafer-level testing of integrated circuits where test pads lie within integrated circuit die but overly no active circuitry for improved yield
JPH07169807A (ja) * 1993-12-16 1995-07-04 Nippondenso Co Ltd 半導体ウェハ
DE4400118A1 (de) * 1994-01-04 1995-07-06 Siemens Ag Verfahren zum Durchführen von Burn-in-Prozeduren an Halbleiterchips
US6577148B1 (en) 1994-08-31 2003-06-10 Motorola, Inc. Apparatus, method, and wafer used for testing integrated circuits formed on a product wafer
US5777486A (en) * 1994-10-03 1998-07-07 United Microelectronics Corporation Electromigration test pattern simulating semiconductor components
JP3734853B2 (ja) * 1995-06-27 2006-01-11 株式会社ルネサステクノロジ 半導体記憶装置
US5852581A (en) * 1996-06-13 1998-12-22 Micron Technology, Inc. Method of stress testing memory integrated circuits
JP3592885B2 (ja) * 1997-03-31 2004-11-24 シャープ株式会社 半導体集積回路装置
US5898706A (en) * 1997-04-30 1999-04-27 International Business Machines Corporation Structure and method for reliability stressing of dielectrics
US6233185B1 (en) 1997-08-21 2001-05-15 Micron Technology, Inc. Wafer level burn-in of memory integrated circuits
US7161175B2 (en) * 1997-09-30 2007-01-09 Jeng-Jye Shau Inter-dice signal transfer methods for integrated circuits
JPH11354721A (ja) 1998-06-04 1999-12-24 Mitsubishi Electric Corp 半導体装置
KR100313185B1 (ko) * 1998-09-29 2001-11-07 포만 제프리 엘 집적 회로 소자의 전기적 액세스 및 상호 접속 방법과 그 장치
JP3708438B2 (ja) * 1998-11-02 2005-10-19 アーテーゲー テスト システムス ゲーエムベーハー アンド コ カーゲー プリント回路基板テスタ
US6233184B1 (en) 1998-11-13 2001-05-15 International Business Machines Corporation Structures for wafer level test and burn-in
JP4234244B2 (ja) 1998-12-28 2009-03-04 富士通マイクロエレクトロニクス株式会社 ウエハーレベルパッケージ及びウエハーレベルパッケージを用いた半導体装置の製造方法
KR100355225B1 (ko) * 1999-07-12 2002-10-11 삼성전자 주식회사 교류 스트레스의 번-인 테스트가 가능한 집적회로 및 이를 이용한 테스트 방법
US6337576B1 (en) 1999-07-19 2002-01-08 Alpine Microsystems, Inc. Wafer-level burn-in
DE19936321C2 (de) * 1999-08-02 2003-12-24 Infineon Technologies Ag Anordnung und Verfahren zum Testen einer Vielzahl von Halbleiterchips auf Waferebene
US6603323B1 (en) * 2000-07-10 2003-08-05 Formfactor, Inc. Closed-grid bus architecture for wafer interconnect structure
JP2002033363A (ja) * 2000-07-19 2002-01-31 Hitachi Ltd 半導体ウエハ、半導体チップ、および半導体装置の製造方法
KR100868419B1 (ko) 2001-06-07 2008-11-11 가부시끼가이샤 르네사스 테크놀로지 반도체장치 및 그 제조방법
KR100575882B1 (ko) * 2003-11-26 2006-05-03 주식회사 하이닉스반도체 번인 테스트용 내부 전압 발생 장치
JP5375834B2 (ja) 2008-12-26 2013-12-25 日本電気株式会社 半導体装置およびそのテスト方法
CN102449658A (zh) 2009-03-18 2012-05-09 踏途音乐公司 娱乐服务器及相关的社交网络系统
US8274301B2 (en) * 2009-11-02 2012-09-25 International Business Machines Corporation On-chip accelerated failure indicator
JP5571200B2 (ja) 2010-01-26 2014-08-13 タッチチューンズ ミュージック コーポレイション 改善されたユーザインターフェースを備えたデジタルジュークボックス装置および関連手法
JP6137318B2 (ja) 2013-07-22 2017-05-31 株式会社村田製作所 垂直共振面発光レーザアレイ
CN112907655B (zh) * 2021-02-08 2021-12-17 深圳信息职业技术学院 Ic烧录的定位方法、系统、终端设备及计算机存储介质

Family Cites Families (39)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3781683A (en) * 1971-03-30 1973-12-25 Ibm Test circuit configuration for integrated semiconductor circuits and a test system containing said configuration
US3890611A (en) * 1972-01-24 1975-06-17 Analog Devices Inc Constant-current digital-to-analog converter
US3849872A (en) * 1972-10-24 1974-11-26 Ibm Contacting integrated circuit chip terminal through the wafer kerf
US4038648A (en) * 1974-06-03 1977-07-26 Chesley Gilman D Self-configurable circuit structure for achieving wafer scale integration
GB1487945A (en) * 1974-11-20 1977-10-05 Ibm Semiconductor integrated circuit devices
US4281449A (en) * 1979-12-21 1981-08-04 Harris Corporation Method for qualifying biased burn-in integrated circuits on a wafer level
US4479088A (en) * 1981-01-16 1984-10-23 Burroughs Corporation Wafer including test lead connected to ground for testing networks thereon
US4467400A (en) * 1981-01-16 1984-08-21 Burroughs Corporation Wafer scale integrated circuit
US4413271A (en) * 1981-03-30 1983-11-01 Sprague Electric Company Integrated circuit including test portion and method for making
EP0072690A3 (de) * 1981-08-17 1983-11-09 Fujitsu Limited MIS Halbleiteranordnung und Verfahren zu deren Herstellung
JPS5911661A (ja) * 1982-07-13 1984-01-21 Nec Corp 集積回路
JPS59172243A (ja) * 1983-03-18 1984-09-28 Nippon Denso Co Ltd Ｉｃウエハ
EP0127100B1 (de) * 1983-05-24 1990-04-11 Kabushiki Kaisha Toshiba Integrierte Halbleiterschaltungsanordnung
DE3483137D1 (de) * 1983-11-30 1990-10-11 Fujitsu Ltd Ec-torfeld.
JPS60140842A (ja) * 1983-12-28 1985-07-25 Nec Corp 半導体装置
JPH0714002B2 (ja) * 1984-05-15 1995-02-15 セイコーエプソン株式会社 チップへの信号供給方法
DE3585756D1 (de) * 1984-07-02 1992-05-07 Fujitsu Ltd Halbleiterschaltungsanordnung in hauptscheibentechnik.
SU1250997A1 (ru) * 1984-10-01 1986-08-15 Предприятие П/Я Р-6668 Способ контрол интегральных микросхем
US4721495A (en) * 1985-09-01 1988-01-26 Nippon Seiko Kabushiki Kaisha Autotensioner
JPS6295853A (ja) * 1985-10-22 1987-05-02 Nec Corp 半導体集積回路
US4813017A (en) * 1985-10-28 1989-03-14 International Business Machines Corportion Semiconductor memory device and array
JPH0740583B2 (ja) * 1986-03-24 1995-05-01 日立コンピユ−タエンジニアリング株式会社 半導体装置の試験方法及びその実施用ウエハ
JPS6343344A (ja) * 1986-08-08 1988-02-24 Nec Corp マスタスライス方式ｌｓｉのブロツク
JPS63213965A (ja) * 1987-03-03 1988-09-06 Mitsubishi Electric Corp 半導体装置
US4910574A (en) * 1987-04-30 1990-03-20 Ibm Corporation Porous circuit macro for semiconductor integrated circuits
JPS63300530A (ja) * 1987-05-29 1988-12-07 Nec Corp 集積回路
JP2606845B2 (ja) * 1987-06-19 1997-05-07 富士通株式会社 半導体集積回路
JPS6435934A (en) * 1987-07-30 1989-02-07 Hitachi Ltd Semiconductor integrated circuit device
US4812742A (en) * 1987-12-03 1989-03-14 Unisys Corporation Integrated circuit package having a removable test region for testing for shorts and opens
JPH01239950A (ja) * 1988-03-22 1989-09-25 Mitsubishi Electric Corp 半導体ウエハ
JPH01298733A (ja) * 1988-05-27 1989-12-01 Fujitsu Ltd 自走機能内蔵集積回路
US5014110A (en) * 1988-06-03 1991-05-07 Mitsubishi Denki Kabushiki Kaisha Wiring structures for semiconductor memory device
JPH0227467A (ja) * 1988-07-16 1990-01-30 Fuji Electric Co Ltd 演算装置間の同期方法
JP2746925B2 (ja) * 1988-08-04 1998-05-06 株式会社リコー 画像形成装置
JPH039364A (ja) * 1989-06-06 1991-01-17 Toshiba Corp 電子写真感光体
JP2508288B2 (ja) * 1989-08-30 1996-06-19 三菱電機株式会社 半導体記憶装置
JPH03106029A (ja) * 1989-09-20 1991-05-02 Fujitsu Ltd ウエハ・スケール・ｉｃ
US5070296A (en) * 1990-06-22 1991-12-03 Honeywell Inc. Integrated circuit interconnections testing
US5059899A (en) * 1990-08-16 1991-10-22 Micron Technology, Inc. Semiconductor dies and wafers and methods for making

Also Published As

Publication number Publication date
US5294776A (en) 1994-03-15
EP0405586B1 (de) 1997-03-26
JP2585799B2 (ja) 1997-02-26
US5138427A (en) 1992-08-11
JPH0334555A (ja) 1991-02-14
KR910001975A (ko) 1991-01-31
EP0405586A1 (de) 1991-01-02
DE69030283D1 (de) 1997-04-30
DE69030283T2 (de) 1997-08-07

Similar Documents

Publication Publication Date Title
KR940006577B1 (ko) 반도체장치 및 그 번인방법
US6625073B1 (en) Apparatus and method for testing for defects between memory cells in packaged semiconductor memory devices
KR960007478B1 (ko) 반도체장치 및 반도체장치의 제조방법
JP2793427B2 (ja) 半導体装置
US5391892A (en) Semiconductor wafers having test circuitry for individual dies
KR100283030B1 (ko) 반도체 장치의 레이 아웃 구조
US4527254A (en) Dynamic random access memory having separated VDD pads for improved burn-in
KR910003147B1 (ko) 반도체집적회로와 그 시험방법
US7449350B2 (en) Structure and method for parallel testing of dies on a semiconductor wafer
KR960002010B1 (ko) 반도체 기억 장치
US7515502B1 (en) Memory array peripheral structures and use
JP4103010B2 (ja) 半導体ウエハ
EP0492609A2 (de) Halbleitergerät mit Spannungsbelastungskontaktfläche
JP2575990B2 (ja) 半導体装置とそのテスト方法
US5297087A (en) Methods and devices for accelerating failure of marginally defective dielectric layers
JPS6229903B2 (de)
US6950355B2 (en) System and method to screen defect related reliability failures in CMOS SRAMS
US7079433B1 (en) Wafer level burn-in of SRAM
JP2954076B2 (ja) 半導体集積回路ウェハ及びその試験方法
JPH0730068A (ja) 半導体記憶装置
JPS6158254A (ja) 半導体集積回路装置
CN118280427A (zh) 动态随机存取存储器及设计方法
JPS59500840A (ja) メモリの加速試験用のパッド
JPH05136243A (ja) エージング等テスト用パターンを付加した半導体ウエハー
JPH0555313A (ja) 半導体ウエハ

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
AMND Amendment
E601 Decision to refuse application
J2X1 Appeal (before the patent court)

Free format text: APPEAL AGAINST DECISION TO DECLINE REFUSAL

G160 Decision to publish patent application
B701 Decision to grant
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20030701

Year of fee payment: 10

LAPS Lapse due to unpaid annual fee