KR930022520A - 저감 단절 전류를 요하는 퓨즈 구조 및 그 퓨즈 구조 제조방법 - Google Patents

저감 단절 전류를 요하는 퓨즈 구조 및 그 퓨즈 구조 제조방법

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Publication number
KR930022520A
KR930022520A KR1019930005508A KR930005508A KR930022520A KR 930022520 A KR930022520 A KR 930022520A KR 1019930005508 A KR1019930005508 A KR 1019930005508A KR 930005508 A KR930005508 A KR 930005508A KR 930022520 A KR930022520 A KR 930022520A
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South Korea
Prior art keywords
fuse
current
fuse link
link
strip
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KR1019930005508A
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English (en)
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KR970007115B1 (ko
Inventor
엘머 갈비 듀안
휴레트 구쓰리 윌리암
키일 올리버
앨런 만델만 잭
사무엘 왓츠 조셉
Original Assignee
죤 디. 크레인
인터내셔널 비지네스 머신즈 코포레이션
베르너 뵈켈, 빌헬름 파우. 리레스
지멘스 악티엔게젤샤프트
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Application filed by 죤 디. 크레인, 인터내셔널 비지네스 머신즈 코포레이션, 베르너 뵈켈, 빌헬름 파우. 리레스, 지멘스 악티엔게젤샤프트 filed Critical 죤 디. 크레인
Publication of KR930022520A publication Critical patent/KR930022520A/ko
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Publication of KR970007115B1 publication Critical patent/KR970007115B1/ko

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
    • H01L23/5252—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising anti-fuses, i.e. connections having their state changed from non-conductive to conductive
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
    • H01L23/5256—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising fuses, i.e. connections having their state changed from conductive to non-conductive
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)

Abstract

저감 단절 전류의 요함으로써 전력 공급 전압 및 구동 트랜지스터에 필요한 칩면적을 최소화 하는 퓨즈는 퓨즈 링크내에 적어도 하나의 거의 직각인 굴곡부를 갖는 것을 제외하고는 상기 퓨즈링크의 주축에 걸쳐 본질적으로 균일한 폭칫수로 특징되는 형상을 갖는다. 퓨즈는 갖은 단면적의 직선퓨즈에 필요한 입력 전류 밀도의 10％정도에서 단절오픈될 수 있다. 이것은 전류 집중으로 인해 전류 밀도가 굴곡부의 내측코너에 집되기 때문이다. 퓨즈의 입력전류가 증가함에 따라 전류 밀도는 내측코너에서 퓨즈 물질이 용융기키는 전류밀도에 도달하게 된다. 노치(notch)는 내측코너에서 형성된다. 노치에 의해 변경된 퓨즈형상은 노치에 전류 집증을 더 심하게 하고, 이것은 용융을 퓨즈의 폭을 가로질러 전파하게 한다.퓨즈 단절점의 예견가능성은 더큰 회로 밀도를 가능케 함과 동시에 인접장치의 뜻밖의 손상 가능성을 최소화하게 한다.

Description

저감 단절 전류를 요하는 퓨즈 구조 및 퓨즈 구조 제조방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본 발명에 바람직한 실시예에 따른 ZAG 퓨즈의 계단 형상을 도시하는 평면도.
제2도는 제1도의 ZAG 퓨즈 형상의 내측 코너에 있는 집중된 전류 밀도를 도시하는 평면도.
제3도는 퓨즈를 가로질러 용융이 전파하는 것을 도시한는 제1도의 ZAG 퓨즈의 대한 평면도.

Claims (6)

  1. 용장성(redundancy)이나 주문형 배선(custom wiring)의 구현을 반도체 회로에 이용되는, 저감 단절전류(reduced blow current)를 요하는 퓨즈 구조의 있어서, 상기 퓨즈구조는, 퓨즈링크를 형성하는 반도체 기판상의 퓨즈물질을 전도성 전도성 스트립을 포함하되, 상기 스트립은 상기 퓨즈 링크내에 적어고 하나의 굴곡부(bend)를 갖는 것을 제외하고는 상기 퓨즈 링크의 주축(primary asix)에 걸쳐 본질적으로 균일한 폭칫수로 특징되어, 전류집중(current crowding)으로 인해 전류 밀도는 상기 퓨즈 링크의 상기 굴곡부에 집중되고, 상기 퓨즈링크에의 입력전류가 증가항에 따라 전류 밀도는 내측 코너에서 상기 퓨즈 물질이 용융하는데 까지 도달되는 퓨즈구조.
  2. 제1항에 있어서, 상기 퓨즈물질은 P+다결정 실리콘인 퓨즈구조
  3. 제2항에 있어서, 상기 스트립은 두 절연물질층 사이에서 둘러쌓이고(encapsulated), 상기 스트립의 자유단 부를 노출하는 호울(hole)내에 형성된 전기 접점을 더 포함하는 퓨즈 구조.
  4. 제1항에 있어서, 상기 스트립은 상기 퓨즈가 전류 집중으로 인해 단절되는 두용장 포인트를 제공하는 두골곡부로 형성되는 퓨즈 구조.
  5. 용장성이나 주문형 배선형 배선을 구현하기 위해 반도체 회로에 이용되는, 저감 단절 전류를 요하는 퓨즈 구조 제조방법에 있어서, 상기퓨즈 구조 제조방법은, 실리콘 기판상에 제1절연층을 형성하는 단계와; 상기 제1절연층상에 전도성 물질을 침적하는 단계와; 상기 전도성 물질내에 퓨즈 링크를 규정하되, 상기 퓨즈링크 상기 퓨즈링크 내에 적어도 하나의 벤드를 갖는 것을 제외하고는 상기 퓨즈링크의 주축에 걸쳐 본질적으로 균일한 폭칫수로 특정되어,전류집중으로 인해 전류밀도는 집중되고 , 상기 퓨즈 링크의 입력전류가 증가함에 따라 전류밀도는 상기 퓨즈 물질을 용융시키는데 까지 도달되는 퓨즈 링크를 규정하는 단계와: 상기 제1절단층과 상기 퓨즈 링크상에 제2절연층을 침적하여 상기 퓨즈 링크를 둘러쌓는 단계와: 상기 제2절연층내에 호울을 형성하여 상기 퓨즈 링크의 자유단부를 노출시키는 단계와: 성기 호울에서 상기 퓨즈 링크의 전기접점을 침적하는 포함하는 퓨즈 구조제조방법.
  6. 제5항에 있어서, 상기 전도성 물질을 P+다결성 실리콘인 퓨즈구조 제조방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019930005508A 1992-04-02 1993-04-01 리던던시 또는 커스텀 와이어링을 구현하기 위해 반도체 회로에서 사용되는 퓨즈 구조물 및 그의 제조 방법 KR970007115B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US861,772 1977-12-19
US86177292A 1992-04-02 1992-04-02

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KR930022520A true KR930022520A (ko) 1993-11-24
KR970007115B1 KR970007115B1 (ko) 1997-05-02

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Country Status (5)

Country Link
US (1) US5420456A (ko)
EP (1) EP0563852A1 (ko)
JP (1) JPH06140510A (ko)
KR (1) KR970007115B1 (ko)
TW (1) TW228036B (ko)

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TW228036B (ko) 1994-08-11
EP0563852A1 (en) 1993-10-06
JPH06140510A (ja) 1994-05-20
US5420456A (en) 1995-05-30

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