KR920018916A - 반도체 장치 - Google Patents
반도체 장치 Download PDFInfo
- Publication number
- KR920018916A KR920018916A KR1019920004046A KR920004046A KR920018916A KR 920018916 A KR920018916 A KR 920018916A KR 1019920004046 A KR1019920004046 A KR 1019920004046A KR 920004046 A KR920004046 A KR 920004046A KR 920018916 A KR920018916 A KR 920018916A
- Authority
- KR
- South Korea
- Prior art keywords
- insulating film
- bar
- lead
- semiconductor device
- chip
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims description 21
- 239000012790 adhesive layer Substances 0.000 claims 5
- 239000000463 material Substances 0.000 claims 4
- 230000002093 peripheral effect Effects 0.000 claims 3
- 239000000758 substrate Substances 0.000 claims 2
- 238000010521 absorption reaction Methods 0.000 claims 1
- 239000010410 layer Substances 0.000 claims 1
- 229920001721 polyimide Polymers 0.000 claims 1
- 239000009719 polyimide resin Substances 0.000 claims 1
- 238000007789 sealing Methods 0.000 claims 1
- 238000005728 strengthening Methods 0.000 claims 1
- 230000005945 translocation Effects 0.000 claims 1
Classifications
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Abstract
내용 없음
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제4도는 본 발명의 1실시예에 의한 DRAM을 포함하는 패케이지된 반도체장치의 부분단면사시도.
제5도는 제4도의 장치의 평면도.
제6도는 제4도의 Ⅵ-Ⅵ선으로 자른 단면도.
Claims (8)
- 주표면에 전자회로가 형성된 반도체칩, 상기 반도체칩의 주표면상에 마련된 전기적 절연막, 각각 내부리이드부와 그것에서 연장하는 외부리이드를 구비하는 여러개의 리이드 및 상기 반도체 칩, 절연막 및 내부리이드부를 봉하는 패케이지재를 포함하며, 상기 절연막은 전기적으로 절연성의 베이스막(기판)과 그 베이스막의 대향하는 제1 및 제2의 표면상에 각각 마련된 제1 및 제2의 접착제층을 구비하고, 그 제1의 접착제층은 상기 칩의 주표면과 상기 베이스막 사이에 끼어져 있고, 리이드부의 일부는 상기 절연막상에 형성되고, 상기 제2의 접착제층은 그들 내부리이드부의 일부와 절연막 사이에 끼워져 있고, 상기 절연막의 면적은 그 절연막의 상기 패케이지재 및 상기 칩에 대한 접착력을 증대하기 위해 상기 내부리이드부의 일부에 의해서 덮여지지 않은 주변부를 부여하는 면적으로 하고, 상기 절연막의 두께는 주위온도의 변동이 있었을때 패케이지된 반도체장치내에 발생할 가능성이 있는 용력을 흡수하기 위해 80~200㎛의 범위에 있는 두께로 한 패케이지된 반도체장치.
- 특히청구의 범위 제1항에 있어서, 패케이지된 반도체장치는 또 상기 절연막상에 형성된 공용내부리이드를 갖고, 상기 반도체칩의 주표면은 사각형이고, 상기 절연막은 빗살형상으로써 상기 칩의 주표면의 한쌍의 평행한 변과 평행한 방향으로 연장하는 바부와 그 바부에 수직인 제2의 방향으로 바부에서 연장하는 여러개의 평행한 바부를 구비하고, 상기 공용내부바는 상기 절연막의 비부상에 형성되고, 상기 여러개의 리이드의 내부리이드의 일부는 상기 빗살형상 절연막의 바부상에 형성되고, 상기 빗살형상의 절연막의 면적은 상기 리이드 및 상기 공용 내부바에 의해 덮여지지 않은 상기 접착증대용 주변부를 갖는 면적으로 되고, 상기 공용내부바는 상기 리이드의 적어도 1개의 내부리이드부와 일체인 패케이지된 반도체장치.
- 특허청구의 범위 제1항에 있어서, 상기 절연막의 두께는 상기 칩과 상기 리이드의 1개 사이의 용량이 1.2pF이상인 패케이지된 반도체장치.
- 특허청구의 범위 제1항에 있어서, 상기 리이드에 덮여지지 않는 상기 절연막의 주변부는 그들 리이드의 관련된 긴쪽방향의 가장자리에서 리이드의 연장방향과 수직인 방향으로 측정한 폭이 10~200㎛의 범위인 페케이지된 반도체장치.
- 특허청구의 범위 제4항에 있어서, 패케이지된 반도체장치는 또 상기 절연막상에 형성된 공용내부바를 가지고, 상기 반도체칩의 주표면은 사각형이고, 상기 절연막은 빗살형상으로써 상기 칩의 주표면의 1쌍의 평행한 변과 평행한 방향으로 연장하는 바부 및 그 바부와 수직인 제2의 방향으로 바부에서 연장하는 여러개의 평행한 바부를 구비하고, 상기 공용내부바는 상기 절연막의 바부상에 형성되고, 상기 여러개의 리이드의 내부리이드부의 일부는 상기 빗살형상의 절연막의 바부상에 형성되고, 상기 빗살형상의 절연막의 면적은 상기 리이드 및 상기 공용 내부비에 의해 덮여지지 않은 상기 접착력증대용 주변부를 갖는 면적으로 되고, 상기 공용내부바는 상기 리이드의 적어도 1개의 내부리이드부와 일체인 패케이지된 반도체장치.
- 주표면에 전좌회로가 형성되는 반도체칩, 주위온도의 변동이 있었을 때 패케이지된 반도체장치내에 발생할 가능성이 있는 응력을 흡수하기 위해 상기 칩의 주표면상에 형성된 응력흡수막, 상기 응력흡수막상에 마련된 전기적 절연막 및 상기 반도체칩, 절연막 및 내부리이드부를 봉하는 패케이지를 포함하며, 상기 절연막의 전기적으로 절연성의 베이스막(기판)과 그 베이스막의 대향하는 제1및 제2의 표면상에 각각 마련된 제1및 제2의 접착제층을 구비하고, 그 제1의 접착제층은 상기 응력흡수막과 상기 베이스막 사이에 끼워져 있고, 또 상기 응력흡수막은 상기 칩의 열팽창율이상으로 상기 절연막의 열팽창율이하의 열팽창계수를 갖고, 상기 외부리이드부는 패케이지재에서 돌출하고 있고, 상기 절연막의 면적은 그 절연막의 상기 패케이지재 및 상기 칩에 대한 접착력을 증대하기 위해 상기 내부리이드부의 일부에 의해서 덮여지지 않은 주변부를 부여하는 면적으로 하고, 상기 절연막의 두께는 주위온도의 변동이 있었을때 패케이지된 반도체장치내에 발생할 가능성이 있는 응력을 흡수하기 위해 80~200㎛의 범위인 두께로 한 페케이지된 반도체장치.
- 특허청구의 범위 제6항에 있어서, 상기 응력흡수막 및 절연막은 모두 폴리이미드수지막으로 되어 있는 패케이지된 반도체장치.
- 특히 청구의 범위 제6항에 있어서, 상기 응력흡수막은 상기 칩에 대해서 압축응력을 생성하는 작용을 하는 패케이지된 반도체장치.※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
Applications Claiming Priority (6)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3081451A JP2556628B2 (ja) | 1991-03-20 | 1991-03-20 | 半導体装置 |
JP91-057477 | 1991-03-20 | ||
JP3057476A JPH0831561B2 (ja) | 1991-03-20 | 1991-03-20 | 半導体装置 |
JP91-057476 | 1991-03-20 | ||
JP3057477A JP2567998B2 (ja) | 1991-03-20 | 1991-03-20 | 半導体装置 |
JP91-081451 | 1991-03-20 |
Publications (2)
Publication Number | Publication Date |
---|---|
KR920018916A true KR920018916A (ko) | 1992-10-22 |
KR100234824B1 KR100234824B1 (ko) | 1999-12-15 |
Family
ID=27296276
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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KR1019920004046A KR100234824B1 (ko) | 1991-03-20 | 1992-03-12 | 반도체 장치 |
Country Status (4)
Country | Link |
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US (2) | US5406028A (ko) |
EP (1) | EP0504821B1 (ko) |
KR (1) | KR100234824B1 (ko) |
DE (1) | DE69227334T2 (ko) |
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JP2708191B2 (ja) | 1988-09-20 | 1998-02-04 | 株式会社日立製作所 | 半導体装置 |
KR0158868B1 (ko) * | 1988-09-20 | 1998-12-01 | 미다 가쓰시게 | 반도체장치 |
JP3388369B2 (ja) * | 1994-01-31 | 2003-03-17 | 日本テキサス・インスツルメンツ株式会社 | 半導体パッケージ装置 |
US5572066A (en) * | 1995-01-03 | 1996-11-05 | Motorola Inc. | Lead-on-chip semiconductor device and method for its fabrication |
TW314650B (ko) * | 1995-06-21 | 1997-09-01 | Oki Electric Ind Co Ltd | |
US5657284A (en) | 1995-09-19 | 1997-08-12 | Micron Technology, Inc. | Apparatus and method for testing for defects between memory cells in packaged semiconductor memory devices |
US5965902A (en) * | 1995-09-19 | 1999-10-12 | Micron Technology | Method and apparatus for testing of dielectric defects in a packaged semiconductor memory device |
US5872398A (en) * | 1996-01-11 | 1999-02-16 | Micron Technology, Inc. | Reduced stress LOC assembly including cantilevered leads |
US6277225B1 (en) | 1996-03-13 | 2001-08-21 | Micron Technology, Inc. | Stress reduction feature for LOC lead frame |
US5781486A (en) * | 1996-04-16 | 1998-07-14 | Micron Technology Corporation | Apparatus for testing redundant elements in a packaged semiconductor memory device |
US5717246A (en) | 1996-07-29 | 1998-02-10 | Micron Technology, Inc. | Hybrid frame with lead-lock tape |
US5763945A (en) * | 1996-09-13 | 1998-06-09 | Micron Technology, Inc. | Integrated circuit package electrical enhancement with improved lead frame design |
US5907184A (en) | 1998-03-25 | 1999-05-25 | Micron Technology, Inc. | Integrated circuit package electrical enhancement |
JP3499392B2 (ja) * | 1997-02-12 | 2004-02-23 | 沖電気工業株式会社 | 半導体装置 |
US5923081A (en) | 1997-05-15 | 1999-07-13 | Micron Technology, Inc. | Compression layer on the leadframe to reduce stress defects |
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US5780923A (en) | 1997-06-10 | 1998-07-14 | Micron Technology, Inc. | Modified bus bar with Kapton™ tape or insulative material on LOC packaged part |
JPH1187572A (ja) * | 1997-09-10 | 1999-03-30 | Oki Electric Ind Co Ltd | 樹脂封止半導体装置およびその製造方法 |
US6043558A (en) * | 1997-09-12 | 2000-03-28 | Micron Technology, Inc. | IC packages including separated signal and power supply edge connections, systems and devices including such packages, and methods of connecting such packages |
US6124150A (en) | 1998-08-20 | 2000-09-26 | Micron Technology, Inc. | Transverse hybrid LOC package |
US6455354B1 (en) * | 1998-12-30 | 2002-09-24 | Micron Technology, Inc. | Method of fabricating tape attachment chip-on-board assemblies |
US6452845B1 (en) | 1999-01-07 | 2002-09-17 | Micron Technology, Inc. | Apparatus for testing redundant elements in a packaged semiconductor memory device |
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US7202112B2 (en) | 2004-10-22 | 2007-04-10 | Tessera, Inc. | Micro lead frame packages and methods of manufacturing the same |
US20200343168A1 (en) * | 2019-04-25 | 2020-10-29 | Stmicroelectronics, Inc. | Lead stabilization in semiconductor packages |
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JPS5922349A (ja) * | 1982-07-29 | 1984-02-04 | Fujitsu Ltd | 半導体装置 |
US4711700A (en) * | 1985-07-03 | 1987-12-08 | United Technologies Corporation | Method for densifying leadframe conductor spacing |
JPS62181453A (ja) * | 1987-01-23 | 1987-08-08 | Hitachi Ltd | 半導体記憶装置 |
JPH0724274B2 (ja) * | 1987-04-24 | 1995-03-15 | 株式会社日立製作所 | 半導体装置及びその製造方法 |
JP2706077B2 (ja) * | 1988-02-12 | 1998-01-28 | 株式会社日立製作所 | 樹脂封止型半導体装置及びその製造方法 |
JP2702219B2 (ja) * | 1989-03-20 | 1998-01-21 | 株式会社日立製作所 | 半導体装置及びその製造方法 |
KR0158868B1 (ko) * | 1988-09-20 | 1998-12-01 | 미다 가쓰시게 | 반도체장치 |
JPH02146758A (ja) * | 1988-11-28 | 1990-06-05 | Nec Corp | 樹脂封止型半導体装置 |
EP0917198B1 (en) * | 1989-06-30 | 2003-05-07 | Texas Instruments Incorporated | Semiconductor device packaging process |
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-
1992
- 1992-03-12 KR KR1019920004046A patent/KR100234824B1/ko not_active IP Right Cessation
- 1992-03-17 DE DE69227334T patent/DE69227334T2/de not_active Expired - Fee Related
- 1992-03-17 EP EP92104617A patent/EP0504821B1/en not_active Expired - Lifetime
-
1994
- 1994-02-18 US US08/198,389 patent/US5406028A/en not_active Expired - Lifetime
-
1995
- 1995-02-07 US US08/384,836 patent/US5466888A/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
US5466888A (en) | 1995-11-14 |
DE69227334T2 (de) | 1999-07-01 |
EP0504821B1 (en) | 1998-10-21 |
KR100234824B1 (ko) | 1999-12-15 |
DE69227334D1 (de) | 1998-11-26 |
EP0504821A2 (en) | 1992-09-23 |
US5406028A (en) | 1995-04-11 |
EP0504821A3 (en) | 1994-11-02 |
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