KR960705353A - 표면 장착용 반도체 장치 제조 방법 및 표면 장착용 반도체 장치(Method of manufacturing a semiconductor device for surface mounting. and semiconductor device for surface mounting) - Google Patents

표면 장착용 반도체 장치 제조 방법 및 표면 장착용 반도체 장치(Method of manufacturing a semiconductor device for surface mounting. and semiconductor device for surface mounting)

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Publication number
KR960705353A
KR960705353A KR1019960701653A KR19960701653A KR960705353A KR 960705353 A KR960705353 A KR 960705353A KR 1019960701653 A KR1019960701653 A KR 1019960701653A KR 19960701653 A KR19960701653 A KR 19960701653A KR 960705353 A KR960705353 A KR 960705353A
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KR
South Korea
Prior art keywords
semiconductor device
manufacturing
slice
lead region
semiconductor
Prior art date
Application number
KR1019960701653A
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English (en)
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KR100380701B1 (ko
Inventor
데커 로날드
고데프리두스 헨리쿠스 마스 라파엘
요하네스 피터 마르티누스 페르스레이젠 게라르두스
Original Assignee
요트.게.아. 롤페즈
필립스 일렉트로닉스 엔.브이.
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Application filed by 요트.게.아. 롤페즈, 필립스 일렉트로닉스 엔.브이. filed Critical 요트.게.아. 롤페즈
Publication of KR960705353A publication Critical patent/KR960705353A/ko
Application granted granted Critical
Publication of KR100380701B1 publication Critical patent/KR100380701B1/ko

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    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
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    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
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    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
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Abstract

본 발명은 표면 장착용 반도체 장치(1)의 제조방법에 관한다. 본 발명에 따라 반도체 장치는 반도체 재료의 슬라이스상에 반도체 장치가 있는 동안 패키지되며, 패키지리드는 반도체 재료로부터 형성된다. 본 발명에 따른 방법에서, 반도체 장치는 리드 프레임, 본딩 와이어, 또는 금속 패키지 리드의 필요 없이도 제조된다. 포토리소그래피, 에칭과 같은 웨이퍼 레벨에서의 IC 기술 덕택에 본 발명에 따른 방법은 반도체 장치를 매우 작은 치수로 만들 수 있다. 부가해서, 수많은 패키지 리드를 가진 집적 회로는 추가의 단계없이도 간단한 방법으로 제조될 수 있다. 본 발명에 따른 방법은 그래서 비교적 저렴하다.

Description

표면 장착용 반도체 장치 제조 방법 및 표면 장착용 반도체 장치(Method of manufacturing a semiconductor device for surface mounting, and semiconductor device for surface mounting)
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제6도는 본 발명에 따른 방법에 의해 여러 제조 단계를 제조되는 다이오드 반도체 장치의 단면도이다.

Claims (10)

  1. 표면 장착용 반도체 장치 제조방법에 있어서, 반도체 재료의 슬라이스는 그 두 측면의 제1측면에서 반도체 소자와 리드 영역을 구비하며, 상기 제1측면에서 반도체 소자의 리드 영역 사이에 콘덕터 트랙이 제공되며 상기 슬라이스의 제1측면은 코팅되어 있으며, 상기 리드 영역은 상기 반도체소자로부터 분리되어 있으며, 상기 슬라이스는 패키지 리드를 갖는 개개의 반도체 장치로 재분할되며 상기 패키지 리드는 리드 영역이 존재하는 슬라이스 부분을 포함하는 것을 특징으로 하는 표면 장착용 반도체 장치 제조 방법.
  2. 제1항에 있어서, 상기 제1측면은 절연층을 구비하며 상기 절연층위에는 콘덕터 트랙이 제공되며, 그후 상기 코팅이 제공되며 계속해서 상기 슬라이스는 슬라이스의 제2측면의 전체 영역에 걸쳐 벌크 감소 처리가 실시되며, 상기 리드 영역은 상기 재료가 상기 제2측면으로부터 선택적으로 상기 슬라이스로부터 제거되어 상기 반도체 소자로부터 분리되며, 상기 절연층은 이동한 스토퍼층으로서 사용되는 것을 특징으로 하는 표면 장착용 반도체 장치 제조 방법.
  3. 제2항에 있어서, 상기 반도체 재료는 실리콘을 포함하며, 실리콘 산화층은 절연층으로서 제공되는 것을 특징으로 하는 반도체 제조 방법.
  4. 제3항에 있어서, 상기 제2측면상 금을 함유한 층이 제공되며 상기 금을 함유한 층은 포토리소그래피 기술로 패턴화 되며, 계속해서 상기 리드 영역과 반도체 소자는 반도체 재료의 에칭제거를 통해 분리되며, 상기 금을 함유한 패턴화된 층은 에칭 마스크로서 사용되는 것을 특징으로 하는 표면 장착용 반도체 장치 제조 방법.
  5. 제4항에 있어서, 실리콘 에칭은 KOH로 실시되는 것을 특징으로 하는 표면 장착용 반도체 장치 제조 방법.
  6. 제1항 내지 제5항 중 어느 한 항에 있어서, 상기 코팅은 절연 덮개판을 구비하는 것을 특징으로 하는 표면 장착용 반도체 장치 제조 방법.
  7. 제6항에 있어서, 상기 절연 덮개판과 같은 유리판을 갖는 코팅으로서 UV 경화 접착제가 제공되며, 그 후 상기 접착제는 유리판을 통해 UV 방사로 경화되는 것을 특징으로 하는 표면 장착용 반도체 장치 제조 방법.
  8. 제1항 내지 제7항 중 어느 한 항에 있어서, 상기 반도체 소자 및/또는 리드 영역은 제1측면과 결합하는 접촉 영역을 구비하며 1019/㎤ 이상의 도판트 원자량을 포함하는 것을 특징으로 하는 표면 장착용 반도체 장치 제조 방법.
  9. 제8항에 있어서, 제1측면으로부터 제2측면으로 연장하는 리드 영역 1019/㎤ 도판트 원자량을 구비하는 것을 특징으로 하는 표면 장착용 반도체 장치 제조 방법.
  10. 표면 장착용 반도체 장치에 있어서, 상기 반도체 장치는 덮개판을 구비하며 그 위에 반도체 재료 본체와 리드 영역이 각각 그들의 두 측면중 제1측면을 구비하며, 상기 본체는 제1측면에서 반도체 소자를 구비하며 이 반도체 소자는 콘덕터 트랙을 거쳐 패키지 리드의 제1측면에 접속되며, 제1측면에 마주하는 패키지 리드인 제2측면은 한 평면에 놓이는 것을 특징으로 하는 표면 장착용 반도체 장치.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019960701653A 1994-07-26 1995-07-05 표면장착용반도체장치제조방법및표면장착용반도체장치 KR100380701B1 (ko)

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EP0721661A1 (en) 1996-07-17
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