ATE225985T1 - Herstellungsmethode eines oberflächen- montierbaren bauteils und dieser selbst - Google Patents

Herstellungsmethode eines oberflächen- montierbaren bauteils und dieser selbst

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Publication number
ATE225985T1
ATE225985T1 AT95921959T AT95921959T ATE225985T1 AT E225985 T1 ATE225985 T1 AT E225985T1 AT 95921959 T AT95921959 T AT 95921959T AT 95921959 T AT95921959 T AT 95921959T AT E225985 T1 ATE225985 T1 AT E225985T1
Authority
AT
Austria
Prior art keywords
itself
production
mount component
semiconductor
package leads
Prior art date
Application number
AT95921959T
Other languages
English (en)
Inventor
Ronald Dekker
Henricus Godefridus Rafae Maas
Martinus Pieter Joh Versleijen
Original Assignee
Koninkl Philips Electronics Nv
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Koninkl Philips Electronics Nv filed Critical Koninkl Philips Electronics Nv
Application granted granted Critical
Publication of ATE225985T1 publication Critical patent/ATE225985T1/de

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    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
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    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Manufacture Of Macromolecular Shaped Articles (AREA)
  • Die Bonding (AREA)
  • Wire Bonding (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
AT95921959T 1994-07-26 1995-07-05 Herstellungsmethode eines oberflächen- montierbaren bauteils und dieser selbst ATE225985T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP94202182 1994-07-26
PCT/IB1995/000539 WO1996003772A2 (en) 1994-07-26 1995-07-05 Method of manufacturing a semiconductor device for surface mounting, and semiconductor device for surface mounting

Publications (1)

Publication Number Publication Date
ATE225985T1 true ATE225985T1 (de) 2002-10-15

Family

ID=8217069

Family Applications (2)

Application Number Title Priority Date Filing Date
AT02077552T ATE350765T1 (de) 1994-07-26 1995-07-05 Verfahren zur herstellung einer halbleitervorrichtunng und eine halbleitervorrichtung
AT95921959T ATE225985T1 (de) 1994-07-26 1995-07-05 Herstellungsmethode eines oberflächen- montierbaren bauteils und dieser selbst

Family Applications Before (1)

Application Number Title Priority Date Filing Date
AT02077552T ATE350765T1 (de) 1994-07-26 1995-07-05 Verfahren zur herstellung einer halbleitervorrichtunng und eine halbleitervorrichtung

Country Status (7)

Country Link
US (1) US5753537A (de)
EP (2) EP0721661B1 (de)
KR (1) KR100380701B1 (de)
AT (2) ATE350765T1 (de)
DE (2) DE69528515T2 (de)
TW (1) TW345728B (de)
WO (1) WO1996003772A2 (de)

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100372136B1 (ko) * 1995-05-10 2003-03-15 코닌클리케 필립스 일렉트로닉스 엔.브이. 반도체디바이스및그제조에적합한캐리어로드
EP0860876A3 (de) * 1997-02-21 1999-09-22 DaimlerChrysler AG Anordnung und Verfahren zur Herstellung von CSP-Gehäusen für elektrische Bauteile
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DE19818036B4 (de) * 1998-04-22 2005-05-19 Siemens Ag Verfahren zur Herstellung eines elektrotechnischen Bauteils mit einer kunststoffpassivierten Oberfläche, derartiges Bauteil und Anwendung dieses Bauteils
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KR100380701B1 (ko) 2003-07-22
DE69528515T2 (de) 2003-04-24
ATE350765T1 (de) 2007-01-15
EP1251557A2 (de) 2002-10-23
EP0721661B1 (de) 2002-10-09
DE69535361T2 (de) 2007-10-04
EP0721661A1 (de) 1996-07-17
US5753537A (en) 1998-05-19
KR960705353A (ko) 1996-10-09
EP1251557B1 (de) 2007-01-03
DE69535361D1 (de) 2007-02-15
DE69528515D1 (de) 2002-11-14
WO1996003772A2 (en) 1996-02-08
WO1996003772A3 (en) 1996-04-18
EP1251557A3 (de) 2003-04-09

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