KR950702068A - 반도체 소자용 패키지(package for semiconductor chip) - Google Patents

반도체 소자용 패키지(package for semiconductor chip)

Info

Publication number
KR950702068A
KR950702068A KR1019940704399A KR19940704399A KR950702068A KR 950702068 A KR950702068 A KR 950702068A KR 1019940704399 A KR1019940704399 A KR 1019940704399A KR 19940704399 A KR19940704399 A KR 19940704399A KR 950702068 A KR950702068 A KR 950702068A
Authority
KR
South Korea
Prior art keywords
layer
power supply
package according
ground
ground layer
Prior art date
Application number
KR1019940704399A
Other languages
English (en)
Inventor
겐이찌로 미야하라
Original Assignee
쓰지 가오루
가부시끼가이샤 도꾸야마
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 쓰지 가오루, 가부시끼가이샤 도꾸야마 filed Critical 쓰지 가오루
Publication of KR950702068A publication Critical patent/KR950702068A/ko

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    • H01L23/053—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body
    • H01L23/057—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body the leads being parallel to the base
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Abstract

본 발명에 의하면, (a) 전원층, 접지층 및 신호층이 절연층을 포함하는 중간층을 통하여 적층되어 있으며, (b) 전원층 및 접지층은, 상기 중간층으로부터 노출되어서 형성되어 있는 내부 리드영역과 외부 리드영역 및 이들 2개의 영역에 끼이면서 이 중간층에 덮인 통전영역으로부터 구성되고, 그리고 (c) 전원층 및 접지층의 각각의 통전영역의 전역의, 평면상을 이룬 통전부재로 실질적으로 구성되어 있는 것을 특징으로 하는 반도체 소자 탑재용 패키지가 제공된다. 이 패키지는 전원층 및 접지층의 자기 인덕턴스가 낮으며, 그리고 이들의 층이 이루는 콘덴서의 용량이 크기 때문에, 전원계의 노이즈가 작다.

Description

반도체 소자용 패키지(PACKAGE FOR SEMICONDUCTOR CHIP)
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제2도는, 본 발명의 패키지의 전원층 또는 접지층의 대표예를 나타내는 모식적인 평면도,
제3도는, 전원층 또는 접지층의 내부 리드영역, 외부 리드영역 및 통전영역을 설명하기 위한 도면.

Claims (22)

  1. (a) 전원층, 접지층 및 신호층이 절연층을 포함하는 중간층을 통하여 적층되어 있으며, (b) 전원층 및 접지층은, 상기 중간층으로부터 노출시켜서 형성되어 있는 내부 리드영역과 외부 리드영역 및 이들 2개의 영역에 끼이면서 이 중간층에 덮인 통전영역으로부터 구성되고, 그리고 (c) 전원층 및 접지층의 각각의 통전영역의 전역은, 평면상을 이룬 통전부재로 실질적으로 구성되어 있는 것을 특징으로 하는 반도체 소자 탑재용 패키지.
  2. 제1항에 있어서, 전원층 및 접지층의 각각의 통전영역은, 그 면적의 90% 이상이 통전부재로 구성되어 있는 패키지.
  3. 제1항에 있어서, 신호층 및 접지층의 자기 인턱턴스가 2nH 이하인 패키지.
  4. 제1항에 있어서, 전원층 및 접지층이 중간층을 통하여 인접하여 적층되어 있는 패키지.
  5. 제4항에 있어서, (i) 접지층, 전원층, 신호층의 순으로, (ii) 전원층, 접지층, 신호층의 순으로, 또는, (iii) 접지층, 전원층, 접지층, 신호층의 순으로 적층되어 있는 패키지.
  6. 제4항에 있어서, 전원층과 접지층과의 중간층이 세라믹 절연층과 무기의 접착제층으로 이루어지는 패키지.
  7. 제6항에 있어서, 세라믹 절연층의 두께가 30㎛ 이상인 패키지.
  8. 제6항에 있어서, 전원층과 세라믹 절연층 및 접지층과 세라믹 절연층과의 접착력이 90°필박리강도에서 1kg/cm 이상인 패키지
  9. 제4항에 있어서, 전원층과 접지층과의 중간층이 유기 접착제층 및 그안에 존재하는 절연층으로 이루어지는 패키지.
  10. 제9항에 있어서, 절연층이 세라믹 박판 또는 절연성 수지 필림인 패키지.
  11. 제9항에 있어서, 절연층의, 양표면이 금속산화물피막 또는 절연성 수지 피막으로 덮인 금속판인 패키지.
  12. 제9항에 있어서, 전원층과 접지층이 이루는 콘덴서의 용량이 100pF 이상인 패키지.
  13. 제9항에 있어서, 전원층과 중간층 및 접지층과 중간층의 접착강도가 90°필박리강도에서 1kg/cm 이상인 패키지.
  14. 제4항에 있어서, 전원층과 접지층의 중간층이 접착제층만으로 실질적으로 구성되어 있는 패키지.
  15. 제14항에 있어서, 전원층과 접지층이 이루는 콘덴서의 용량이 100pF 이상인 패키지.
  16. 제14항에 있어서, 전원층과 중간층 및 접지층과 중간층의 접착 강도가 90°필박리강도에서 1kg/cm 이상인 패키지.
  17. 제4항에 있어서, 전원층과 접지층의 중간층이, 이들의 층의 통전영역에 존재하는 통전부재가 적어도 어느 것의 표면에 형성된 절연층 및 접착제층으로 이루어지는 패키지.
  18. 제17항에 있어서, 절연층이 금속산화물피막 또는 절연성 수지피막인 패키지.
  19. 제17항에 있어서, 전원층과 접지층이 이루는 콘덴서의 용량이 110pF 이상인 패키지.
  20. 제17항에 있어서, 전원층과 중간층 및 접지층과 중간층의 접착강도가 90°필박리강도에서 1kg/cm 이상인 패키지.
  21. 제1항에 있어서, 기체를 형성하고, 적어도 그 일면상에 전원층 또는 접지층이 적층되어 있는 패키지.
  22. 제1항에 있어서, 반도체 소자가 탑재된후, 실질적으로 수지봉함되지 않고 이용되는 패키지.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019940704399A 1993-04-06 1994-04-06 반도체 소자용 패키지(package for semiconductor chip) KR950702068A (ko)

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JP93-79675 1993-04-06
JP7967593 1993-04-06
JP31538293 1993-12-15
JP93-315382 1993-12-15
PCT/JP1994/000571 WO1994023448A1 (en) 1993-04-06 1994-04-06 Package for semiconductor chip

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US5629559A (en) 1997-05-13

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