KR910000757B1 - 반도체 장치 - Google Patents

반도체 장치 Download PDF

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Publication number
KR910000757B1
KR910000757B1 KR1019870014022A KR870014022A KR910000757B1 KR 910000757 B1 KR910000757 B1 KR 910000757B1 KR 1019870014022 A KR1019870014022 A KR 1019870014022A KR 870014022 A KR870014022 A KR 870014022A KR 910000757 B1 KR910000757 B1 KR 910000757B1
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South Korea
Prior art keywords
metal layer
alloy
semiconductor device
aluminum
thickness
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KR1019870014022A
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English (en)
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KR880008444A (ko
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오사무 우수다
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가부시기가이샤 도시바
아오이 죠이찌
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Publication of KR880008444A publication Critical patent/KR880008444A/ko
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Publication of KR910000757B1 publication Critical patent/KR910000757B1/ko

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Wire Bonding (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

내용 없음.

Description

반도체 장치
제1도는 종래의 반도체 단면도로서, 동계의 접합와이어를 접합하기전 상태도.
제2도는 종래의 반도체 단면도로서, 동계의 접합와이어를 접합한후의 상태도.
제3도는 본 발명의 일실시예시 반도체 장치의 단면도로서, 동계의 접합와이어를 접합하기전 상태도.
제4도는 본 발명의 일실시예를 나타내는 반도체 장치의 단면도로서, 동계의 접합와이어를 접합한 후의 상태도.
* 도면의 주요부분에 대한 부호의 설명
11 : 리드후레임 12 : 도전성 페스트
13 : 반도체 소자 14 : 절연막
21 : 전극 패드
본 발명은 동계(銅系)의 와이어를 접합와이어로서 사용하는 반도체 장치에 관하며, 특히 전극 패드(Pad)의 구조의 개량에 관한 것이다.
종래, 접합와이어로서 동 또는 동합금을 사용하는 반도체 장치에서는, 전극 패드(접합 전극)으로서, 알미늄 또는 알미늄 합금을 사용하고 있다. 제1도는 종래의 반도체 장치의 단면도로서, 상기 동계의 와이어를 사용하여 와이어 접합을 하기전의 상태를 나타낸다. 제2도는 이 반도체 장치의 단면도로서, 상기 동계의 와이어를 사용하여 와이어 접합을 이룬 다음의 상태를 나타낸다.
도면 중 부호 11은 리드후레임으로, 이 리드후레임 위에는 은 페스트 등의 도전성 페스트(12)를 통하여 반도체 소자(13)를 고정착설하고 있다. 이 반도체 소자(13)의 표면위의 소정개소에는 절연막(14)이 형성되어 있으며, 반도체 소자의 표면중 상기 절연막을 형성하지 않은 곳과 상기 절연막 위에는, 알미늄 또는 알미늄 합금의 금속층으로 된 전극 패드(15)가 형성되어 있다.
상기 전극 패드(15)위에, 제2도에서와 같이 동계의 접합와이어(16)를 결합하고 있다. 이 접합와이어는 전극 패드보다도 단단하다.
그러므로 와이어(16)를 와이어 접합할 때, 그 밀음압력보다도 전극 패드가 제4도에서와 같이 변형하여 접합와이어는 전극 패드를 지나치게 넘어서 반도체 소자(13)에 집적 접하고 마는 경우가 있다.
이러한 상태에서는 결합부의 전기적 특성을 변화하거나, 고운중에 방치한 경우에 반도체 장치의 전기적 특성이 변동하는 등의 치명적인 불량이 발생하기 쉽다.
또 굳은 와이어를 반도체 소자(13)를 직접 압압하는 결과, 반도체 소자에 이그러짐을 주게 되므로, 온도 사이클 등의 온도변화가 있으면, 반도체 소자와 와이어 등에 열팽창계수의 차로 인하여 반도체 소자에 클럭이 발생하기 쉽게 된다.
또 상기 전극 패드(15)의 凹凸부(17)는, 전극 패드의 패턴형성시 타부위에 비하여 부식하기 쉽고, 반도체 소자에까지 미치게 되므로 이 부식부에 기인한 동작불량이 반도체 장치의 사용중에 발생하기 쉽다.
본 발명의 제1목적은, 와이어 접합시에 저지할 반도체 장치를 제공함에 있다. 본 발명의 제2목적은, 와이어 접합시에 와이어가 반도체 소자를 직접 압압함이 없이 따라서 반도체 소자에 이그러짐이 없는 반도체 장치를 제공함에 있으며, 제3의 목적은 적극 패드의 凹凸부의 부식 개소가 반도체 소자에 도달하지 않는 반도체 장치를 제공하는데 있다.
상기 본 발명의 목적을 달성하기 위하여 본 발명은, 반도체 소자와, 이 소자위에 형성된 전극 패드와 이 전극 패드위에 와이어 접합된 상기 전극 패드와 외부 리드 등을 접착하기 위한 동계의 와이어 등을 구비한 반도체 장치에 있어서, 상기 전극 패드는, 상기 반도체 소자위에 형성되고 반도체와 반도체의 저항치 조절(ohmic-contact)이 가능하고 상기 반도체 소자의 기능에 악영향을 주지 않는 제일 금속층과, 이 제1금속층위에 형성되고 와이어 결합시의 압압력에 대항할 수 있는 경도(硬度)를 갖는 제2금속층과 이 제2금속층위에 형성되고 동계의 와이어로 접합이 가능한 조성을 갖는 제3의 금속층등으로 기본적 구성을 이루고 있는 반도체 장치인 것이다.
상기와 같이 본 발명에서는, 3층구조의 전극 패드로 하고, 그중 제2의 금속층을 보다 굳은 금속으로 형성하여 변형하지 않도록 하였으므로 와이어 접합시에 전극패드의 제3의 금속층이 변형해도 와이어는 이 제2금속층에서 머물고 전극 패드를 제치고 반도체 소자에 직접 접하지 않게 된다.
그러므로 접착부의 전기적 특성의 변화나 고온 방지시에 있어서의 반도체 소자의 전기적 특성의 변동을 확실하게 저지할 수 있다.
또 와이어는 제2금속층의 위치에서 정지하게 되므로 와이어는 반도체 소자에 이그러짐을 주는 일도 없고 온도가 변화한때의 반도체 소자의 클럭의 발생을 방지할 수 있을 뿐 아니라 전극 패드의 凹凸부의 부식은, 상기 제2의 금속층으로 저지되므로 부식한 곳이 반도체 소자 표면에까지 진행하지 않아 반도체 사용중의 불량이란 사고도 방지할 수가 있다.
이하 본 발명의 실시예를 도면에 따라 설명한다.
한편 제1도 및 제2도의 반도체 장치와 같은 개소에는 같은 부호를 붙인다. 도시한 반도체 장치는, 리드후레임(11)위에 도전성 페스트(12)를 이용하여 반도체 소자(13)를 고정착설하고 있으며, 이 반도체 소자의 표면위에는, 소정개소에 절연막(14)이 형성되어 있다.
반도체 소자의 표면중 절연막을 형성하고 있지 않은 곳 및 상기 절연막위에 본 발명에 관한 전극 패드(21)가 형성되어 있다.
이 전극 패드(21)는, 기본적으로 3층의 금속층으로 되며, 제1의 금속층은, 상기 반도체 소자위에 형성하고 반도체와 저항치 조절이 가능하고, 상기 반도체 소자의 기능에 악영향을 주지 않는 것이다.
여기서 반도체 소자의 기능에 악영향을 주지 않는다함은, 금속층중의 합금원소 혹은 불순물이 반도체 소자내로 침입하여 그 전기적 기능을 열등화시키는 일이 없다는 의미이다.
상기 제1의 금속층(18)은, 알미늄, 알미늄합금, 금 및 합금금군에서 선택된 1의 금속이 적합하다. 알미늄합금으로서, 알미늄을 60중량% 이상 함유하고 있으면 된다.
상기 알미늄 또는 알미늄 합금으로 된 제1의 금속층의 적합한 두께는 0.1-2.5㎛이다. 금합금으로서는 금을 60중량% 이상 포함하고 있으면 되고, 상기 금 또는 금합금으로 된 제1의 금속층의 적합한 두께는 0.2-2.5㎛이다.
상기와 같이 제1의 합금층의 적합한 두께의 범위를 정한 것은 지나치게 얇으면 제2의 금속층의 확산으로 저항조절이 불량해지고, 또 지나치게 두꺼우면 제2의 금속층의 변화가 발생하기 때문이다. 이 제1의 금속층 위에는, 제2의 금속층(19)이 형성되며, 이 제2의 금속층은, 와이어 결합시의 압압력에 의하여도 변하지 않는 경도를 갖는다.
이 굳기는 통상 알미늄, 또는 알미늄 합금이상의 것이 적합하다.
상기 제2의 금속박의 적합한 금속으로서는, 바나듐, 바나듐합금, 니켈, 니켈합금, 치탄, 치탄합금, 탄탈, 탄탈합금의 군에서 선택된 1의 금속을 둘 수 있다.
바나듐합금, 탄탈합금으로서는, 바나듐 또는 탄탈을 60중량% 또는 그 이상 첨가한 것이 좋다. 바나듐, 바나듐합금, 탄탈 또는 탄탈합금으로 된 제2의 금속층의 적합한 두께는 0.05-1㎛이다.
니켈합금으로서는, 60중량% 이상의 40중량% 이하의 크롬일 40중량% 이하의 코발트로 선택된 1종 또는 2종의 금속과를 포함한 합금을 들 수 있다. 니켈 또는 니켈합금으로 된 제2의 금속층의 적합한 두께는 300-10000 엉스트롬(Angstrom)이다.
치탄합금으로서는, 치탄을 60중량% 또는 그 이상 첨가한 것이 좋다. 치탄 또는 치탄합금으로 된 제2의 합금층의 적합한 두께는 300-1000 엉스트롬이다.
상기와 같이 제2의 금속층의 적합한 두께의 범위를 결정한 것은 과얇으면 소망한 경도를 얻을 수 없고 또 과두터우면 가공이 곤란하기 때문이다.
이 제2의 금속층위에는 제3의 금속층(20)이 형성되며, 이 제3의 금속층은 동계의 와이어로 접착가능한 조성을 갖는다. 제3의 금속층의 적합한 금속은 알미늄, 알미늄합금, 금 및 금합금의 군에서 선택된 1의 합금이다.
알미늄합금으로서는 알미늄을 60중량% 이상 포함하고 있으면 된다. 알미늄 또는 알미늄 합금의 금속박의 적합한 두께는 0.5-5.0㎛이다.
금합금으로서는, 금을 60중량% 이상 포함하고 있으면 된다. 금 또는 금합금의 금속층의 적합한 두께는 0.2-2.5㎛이다. 상기와 같이 제3의 합금층의 적합한 두께의 범위를 정한 것은, 지나치게 얇으면 제2의 금속층의 산화가 발생하기 쉽고, 또 지나치게 두터우면 가공이 곤란하기 때문이다.
이들중 특히 적합한 실시상태는, 제1의 금속층은 막두께 0.1-2.5㎛의 알미늄 또는 알미늄 합금이고, 제2의 금속층은 막두께 0.1-0.8㎛의 바나듐 또는 바나듐합금이고, 제3의 금속층은 막두께 0.5-5.0㎛의 알미늄 또는 알미늄 합금이다.
상기 전극 패드(21)의 형성은 반도체 소자의 표면 및 절연막위에 제1내지 제3의 금속층을 순차 중착형성한 다음 잇칭(Etching) 가공을 하여 패터님함으로서 이루어진다.
와이어 접착공정은 상기 리드후레임(11)을 200-450℃의 온도로 가열하고, 이 상태에서 제4도에 표시한 바와 같이 상기 제3의 금속층(20)위에, 열압착 또는 초음파에 의한 진동 등에 의하여 동계 접착 와이어(16)을 접착한다.
이 구성에 의하면, 와이어 접착시에 있어서, 연한 제3의 금속층(20)은 와이어(16)의 압부력에 의하여 변형하나, 굳은 제2의 금속층(19)은 변형하지 않고, 제1의 금속층(18)까지는 변형이 미치지 않는다. 그러므로 와이어가 반도체 소자(13)와 접함이 없이, 또 반도체 소자에 이그러짐을 전혀 주지 않는다. 그러므로 반도체 소자의 전기적 특성의 변화나 반도체 소자의 클럭 발생을 저지할 수가 있다.
또, 제2의 금속층은, 전극 패드(21)의 패터닝 형성시에, 제2의 금속층으로 부식의 진행을 방지함으로, 제1의 금속층은 부식하지 않고 전기적 불량도 발생하지 않을 뿐 아니라 고온방지 시험에서도 전기적 특성의 변화가 대체로 없다.
또 본 발명의 전기패드는, 상기 3층의 금속층외에 다시 그 표면 혹은 내부에 별도의 층을 형성하여 4층 이상의 구성이어도 무방하다.
다음에 본 발명에 관한 제1도 및 제2도에 표시한 반도체 장치를 실제로 만들어 그 불량율을 제1도 및 제2도에 표시한 반도체 장치의 불량발생율과 비교한바, 이 경우 본발명의 전극패드는 제1의 금속층이 막두께 0.5㎛의 알미늄, 제2의 금속층이 막두께 0.3㎛의 바나듐, 제3의 금속층이 막두께 2.5㎛의 알미늄으로 된다.
또 종래의 반도체 장치의 전극 패드는, 막두께 2.5㎛의 알미늄 단일층으로 된다.
이들 반도체 장치에 대하여, 고온(150℃)와 저온(-45℃) 등을 순차 반복열 사이클 시험을 하여, 양자를 비교한 바, 종래의 반도체 장치에서는, 400사이클로 25%가 불량했으며, 600사이클에서 80%가 불량했었다.
이에 대하여 본 발명에 관한 반도체 장치에서는, 400사이클은 물론 600사이클에서도 불량은 발생하지 않는다.
또 접착와이어를 접합할때의 하중을 지금까지의 2배(300그럼)로 하여 접착하여 반도체 장치를 제작하고 그 불량 발생율을 조사한 바, 종래의 구조의 것은 30-50%이었으나, 이에 대하여 본 발명에 관한 장치에서는 불량발생율 0.1%이하이었다.

Claims (10)

  1. 반도체 소자와 이 소자위에 형성된 전극 패드와 이 전극 패드 위에 와이어 접착된 상기 전극 패드와 외부리드 등을 접속하기 위한 동계의 와이어 등을 구비한 반도체 장치에 있어서, 상기 전극 패드는 상기 반도체 소자위에 형성되고, 반도체와 저항치 조절이 가능하고, 상기 반도체 소자의 기능에 악영향을 주지 않는 제1의 금속층과 제1의 금속층 위에 형성되고 와이어 접착시의 압압력에 대항할 수 있는 정도를 갖는 바나듐 또는 바나듐합금으로 된 제2의 금속층과, 이 제2금속층위에 형성되며, 동계의 와이어로 접착이 가능한 조성을 갖는 제3의 금속층등으로 기본적으로 구성되어 있는 반도체 장치.
  2. 제1항에 있어서, 상기 제1의 금속층은 알미늄, 알미늄합금, 금 및 금합금의 군에서 선택된 하나의 금속인 것을 특징으로 하는 반도체 장치.
  3. 제2항에 있어서, 상기 알미늄 또는 알미늄합금으로 된 제1의 금속층의 두께는 0.1-2.5㎛임을 특징으로 하는 반도체 장치.
  4. 제2항에 있어서, 상기 금 또는 금합금으로 된 제1의 금속층의 두께는 0.2-2.5㎛임을 특징으로 하는 반도체 장치.
  5. 제1항에 있어서, 바나듐, 바나듐합금으로 된 제2의 금속층의 두께는 0.05-1㎛임을 특징으로 하는 반도체 장치.
  6. 제1항에 있어서, 제3의 금속층은 알미늄, 알미늄합금, 금 및 금합금의 군에서 선택된 하나의 합금임을 특징으로 하는 반도체 장치.
  7. 제6항에 있어서, 알미늄 또는 알미늄합금으로 된 제3의 금속층의 두께는 0.1-5.0㎛임을 특징으로 하는 반도체 장치.
  8. 제6항에 있어서, 금 또는 금합금의 금속층의 두께는 0.2-2.5㎛임을 특징으로 하는 반도체 장치.
  9. 제1항 기재에 있어서, 제1의 금속층은 막두께 0.1-2.5㎛의 알미늄 또는 알미늄 합금이고, 제2의 금속층은 막두께 0.1-0.8㎛의 바나듐 또는 바나듐합금이고, 제3의 금속층은 막두께 0.5-5.0㎛의 알미늄 또는 알미늄합금임을 특징으로 하는 반도체 장치.
  10. 제1항에 있어서, 상기 전극 패드는 제1 내지 제3의 금속층을 순차 증착형성한 다음 가공을 하여 패터닝 함으로써 형성되는 것을 특징으로 하는 반도체 장치.
KR1019870014022A 1986-12-12 1987-12-09 반도체 장치 KR910000757B1 (ko)

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JP61-294902 1986-12-12
JP61294902A JPS63148646A (ja) 1986-12-12 1986-12-12 半導体装置

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KR880008444A (ko) 1988-08-31
DE3787709D1 (de) 1993-11-11
CN87107402A (zh) 1988-06-22
DE3787709T2 (de) 1994-04-21
EP0271110A3 (en) 1989-02-22
US5060051A (en) 1991-10-22
CN1020029C (zh) 1993-03-03
EP0271110A2 (en) 1988-06-15
JPH0482183B2 (ko) 1992-12-25
EP0271110B1 (en) 1993-10-06
JPS63148646A (ja) 1988-06-21

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