WO2012005073A1 - 半導体装置、半導体パッケージ及びそれらの製造方法 - Google Patents

半導体装置、半導体パッケージ及びそれらの製造方法 Download PDF

Info

Publication number
WO2012005073A1
WO2012005073A1 PCT/JP2011/063030 JP2011063030W WO2012005073A1 WO 2012005073 A1 WO2012005073 A1 WO 2012005073A1 JP 2011063030 W JP2011063030 W JP 2011063030W WO 2012005073 A1 WO2012005073 A1 WO 2012005073A1
Authority
WO
WIPO (PCT)
Prior art keywords
semiconductor device
wire
bonding
bonding pad
layer
Prior art date
Application number
PCT/JP2011/063030
Other languages
English (en)
French (fr)
Inventor
前田　晃
山田　朗
浩次 山崎
裕史 堀部
広瀬　哲也
Original Assignee
三菱電機株式会社
ルネサスエレクトロニクス株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 三菱電機株式会社, ルネサスエレクトロニクス株式会社 filed Critical 三菱電機株式会社
Priority to JP2012523803A priority Critical patent/JPWO2012005073A1/ja
Publication of WO2012005073A1 publication Critical patent/WO2012005073A1/ja

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
    • H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
    • H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
    • H01L2224/02165—Reinforcing structures
    • H01L2224/02166—Collar structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05075—Plural internal layers
    • H01L2224/0508—Plural internal layers being stacked
    • H01L2224/05082—Two-layer arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05556—Shape in side view
    • H01L2224/05559—Shape in side view non conformal layer on a patterned surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05624—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/4501—Shape
    • H01L2224/45012—Cross-sectional shape
    • H01L2224/45015—Cross-sectional shape being circular
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45147—Copper (Cu) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4845—Details of ball bonds
    • H01L2224/48451—Shape
    • H01L2224/48453—Shape of the interface with the bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/485—Material
    • H01L2224/48505—Material at the bonding interface
    • H01L2224/48599—Principal constituent of the connecting portion of the wire connector being Gold (Au)
    • H01L2224/486—Principal constituent of the connecting portion of the wire connector being Gold (Au) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/48617—Principal constituent of the connecting portion of the wire connector being Gold (Au) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950 °C
    • H01L2224/48624—Aluminium (Al) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/485—Material
    • H01L2224/48505—Material at the bonding interface
    • H01L2224/48799—Principal constituent of the connecting portion of the wire connector being Copper (Cu)
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85053—Bonding environment
    • H01L2224/85054—Composition of the atmosphere
    • H01L2224/85065—Composition of the atmosphere being reducing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/852—Applying energy for connecting
    • H01L2224/85201—Compression bonding
    • H01L2224/85205—Ultrasonic bonding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8536—Bonding interfaces of the semiconductor or solid state body
    • H01L2224/85375—Bonding interfaces of the semiconductor or solid state body having an external coating, e.g. protective bond-through coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01014—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01022—Titanium [Ti]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01024—Chromium [Cr]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01027—Cobalt [Co]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01028—Nickel [Ni]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01042—Molybdenum [Mo]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0105—Tin [Sn]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01073—Tantalum [Ta]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01074—Tungsten [W]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/049—Nitrides composed of metals from groups of the periodic table
    • H01L2924/0494—4th Group
    • H01L2924/04941—TiN
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/157—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2924/15738—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950 C and less than 1550 C
    • H01L2924/15747—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/20—Parameters
    • H01L2924/201—Temperature ranges
    • H01L2924/20106—Temperature range 200 C=<T<250 C, 473.15 K =<T < 523.15K
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/20—Parameters
    • H01L2924/206—Length ranges
    • H01L2924/20657—Length ranges larger or equal to 6000 microns less than 7000 microns
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/20—Parameters
    • H01L2924/207—Diameter ranges
    • H01L2924/20753—Diameter ranges larger or equal to 30 microns less than 40 microns

Definitions

  • the present invention relates to a semiconductor device in which an electrode for wire bonding is formed in the vicinity of an active element such as a microcomputer or a power transistor, a semiconductor package, and a manufacturing method thereof.
  • wire bonds such as aluminum (Al), gold (Au), and copper (Cu) have been used as methods for electrically connecting electrodes of a semiconductor element and a substrate electrode or electrodes of another semiconductor element.
  • Au wires are mainly used for narrow pitch electrodes (small pads) due to the mechanical properties of the wires, but Cu wires have also been applied to reduce costs. Since Cu has a relatively high mechanical strength among wire materials, a Cu film is formed on the surface of the electrode layer mainly composed of Al as an electrode (bonding pad) on the semiconductor element side as a measure for reducing damage to the semiconductor element.
  • Patent Document 1 a base layer mainly composed of Al, a barrier layer, and a bonding layer for bonding to a bonding wire on a semiconductor element Have been proposed (see, for example, Japanese Patent Laid-Open No. 2002-76051 (Patent Document 2)).
  • JP 63-164329 A Japanese Patent Laid-Open No. 2002-76051
  • Patent Document 1 when a Cu film having a high mechanical strength is formed on the bonding pad surface, damage to the semiconductor element is reduced, but the bonding is difficult because the pad surface is not easily deformed during wire bonding. It has been a problem that the surface oxide film of the pad is hardly broken and the initial bondability is lowered.
  • the present invention has been made to solve the above-described problems, and an object of the present invention is to have an electrode (bonding pad) capable of Cu wire bond bonding having good initial bondability and high reliability.
  • An semiconductor device, a semiconductor package, and a manufacturing method thereof are provided.
  • the semiconductor device according to the present invention is arranged only in the active element, the electrode mainly composed of aluminum electrically connected to the active element, and the central part of the electrode, and has a mechanical strength higher than that of copper.
  • a relaxation film is arranged only in the active element, the electrode mainly composed of aluminum electrically connected to the active element, and the central part of the electrode, and has a mechanical strength higher than that of copper.
  • damage to a semiconductor element during bonding can be reduced, and a bonding wire and a bonding pad can be favorably bonded.
  • the semiconductor device includes a semiconductor element 3 including an active element (not shown), an insulating layer 4, and a bonding pad 8 as an electrode.
  • An insulating layer 4 is formed on the semiconductor element 3.
  • a bonding pad 8 that is electrically connected to the active element is formed on the insulating layer 4.
  • On the bonding pad 8, a coating layer 15 in which an opening 16 defining the upper surface of the bonding pad 8 is formed is disposed.
  • the bonding pad 8 is an electrode mainly composed of aluminum, and is a pad electrode to which the Cu wire 1 shown in FIG. 1 is wire bonded.
  • the bonding pad 8 includes a first wiring layer 5, a stress relaxation film 6, and a second wiring layer 7.
  • the first wiring layer 5 and the second wiring layer 7 are each a conductor layer mainly composed of aluminum.
  • the first wiring layer 5 is formed on the insulating layer 4.
  • a stress relaxation film 6 is formed on the first wiring layer.
  • a second wiring layer 7 is formed on the stress relaxation film 6.
  • the stress relaxation film 6 is disposed only at the center of the bonding pad 8 in plan view.
  • the stress relaxation film 6 has a mechanical strength (Mohs hardness) equal to or higher than copper (that is, the Mohs hardness of the stress relaxation film 6 is larger than the Mohs hardness of copper).
  • the covering layer 15 is disposed on the second wiring layer 7.
  • the semiconductor device according to the present invention shown in FIG. 1 includes a stress relaxation film 6 having a mechanical strength equal to or higher than that of copper only at the central portion of the bonding pad 8, so that it is made of Al when bonding the Cu wire 1 as will be described later. Good initial bondability can be secured without hindering deformation of the surface of the bonding pad 8.
  • a semiconductor element 3 in which an active element (not shown) is formed by a conventionally known method is prepared.
  • the semiconductor element 3 may include, for example, a semiconductor substrate and an active element formed on the semiconductor substrate.
  • This active element may be an element constituting, for example, a microcomputer or a power transistor.
  • an insulating layer 4 is formed on the upper surface of the semiconductor element 3 by a CVD method, a thermal oxidation method, or the like.
  • a first wiring layer 5 made of Al is formed thereon by sputtering or the like.
  • the stress relaxation film 6 is formed on the first wiring layer 5.
  • any conventionally known method can be used.
  • a resist film having an opening pattern in a region where the stress relaxation film 6 shown in FIG. 1 is to be formed is formed on the first wiring layer 5 using a photolithography method. Then, a conductor layer (not shown) made of titanium (Ti) or the like having a mechanical strength of copper or higher is formed by sputtering or the like on the inside of the opening pattern and on the resist film. Subsequently, the resist film is removed using a chemical solution or the like. As a result, the portion of the conductor layer formed on the resist film is removed together with the resist film (lift-off). In this way, the stress relaxation film 6 can be formed only in the central portion of the bonding pad 8 in plan view.
  • the second wiring layer 7 is formed by sputtering or the like so as to cover the stress relaxation film 6 and the exposed upper surface of the first wiring layer 5.
  • a resist film (not shown) is formed on the second wiring layer 7 by using a photolithography method.
  • An opening pattern corresponding to the planar shape of the bonding pad 8 is formed in the resist film.
  • the second wiring layer 7 and the first wiring layer 5 are partially removed to form a bonding pad 8 having a predetermined planar shape. Thereafter, the resist film is removed.
  • a film to be the coating layer 15 is formed on the second wiring layer 7 using a CVD method or the like.
  • a resist film having an opening pattern formed in a region to be the opening 16 shown in FIG. 1 is formed using a photolithography method or the like.
  • the resist film is removed.
  • the covering layer 15 having the opening 16 can be formed. In this way, the semiconductor device according to the present invention shown in FIG. 1 can be obtained.
  • a frame 23 (see FIG. 4) including the conductive portion 22 is prepared.
  • the semiconductor device 20 manufactured by the above manufacturing method is disposed adjacent to the frame 23 (specifically, at a predetermined position on the frame 23).
  • the frame 23 and the semiconductor device 20 may be connected and fixed to each other by a connection layer or the like.
  • a plurality of bonding pads 8 having the cross-sectional structure shown in FIG. 1 are formed on the upper surface of the semiconductor device 20.
  • a plurality of conductive portions 22 are formed on the frame 23 so as to surround a region where the semiconductor device 20 is disposed.
  • a semiconductor package according to the present invention can be obtained by connecting the bonding pad 8 of the semiconductor device 20 and the conductive portion 22 with the Cu wire 1.
  • the ball portion 2 is formed by heating and melting an end portion of the Cu wire 1 as a joint portion of the Cu wire 1.
  • the surface of the ball portion 2 is brought into contact with the surface of the bonding pad 8.
  • a tool of a wire bonding apparatus (wire bonder) is brought into contact with the ball portion 2, and a load is applied and ultrasonic waves are applied so as to press the ball portion 2 toward the bonding pad 8.
  • the surface oxide film between the surface of the ball portion 2 of the Cu wire 1 and the surface of the bonding pad 8 can be mechanically broken by plastic deformation. Then, the surface oxide film of the surfaces of the ball part 2 and the bonding pad 8 is destroyed, and thermal diffusion occurs in the parts (bonding regions) in contact with each other, so that the alloy layer 11 shown in FIGS. It is formed. Then, the bonding pad 8 and the ball portion 2 of the Cu wire 1 are connected and fixed in a state where the Cu wire 1 is pushed into the semiconductor element 3 as shown in FIGS.
  • the Cu wire 1 can be wire-bonded (bonded) to the bonding pad 8.
  • the semiconductor element 3 is caused by pressing the Cu wire 1 toward the semiconductor element 3 (wire bonding).
  • the stress applied to the semiconductor element 3 can be reduced (that is, the stress relaxation film 6 can be used as a protective layer of the semiconductor element 3).
  • the waste material 10 (see FIG. 2) formed as a result of wire bonding includes an alloy layer resulting from the stress relaxation film 6. The possibility of being For this reason, it is possible to avoid the occurrence of a problem that cracks are generated due to the presence of the alloy layer in the waste material 10.
  • a mask having an opening pattern having the same shape as the opening 16 (see FIG. 1) is formed on the bonding pad 8 on the semiconductor element 3, and the surface of the bonding pad 8 and the upper surface of the mask are formed by a sputtering apparatus or the like.
  • a Cu layer (not shown) having a predetermined thickness can be formed. Thereafter, the Cu layer can be formed only on the surface of the bonding pad 8 by removing the mask.
  • the heating temperature is set to 200 ° C. or higher and the constituent material of the bonding pad 8 in a high vacuum or an atmosphere of nitrogen, hydrogen, or a mixed gas thereof (that is, an environment in which the Cu layer or the like is less likely to be oxidized than a normal air atmosphere)
  • An alloy layer (not shown) made of a Cu—Al alloy may be formed on the surface of the bonding pad 8 by performing a heat treatment with a melting point or lower.
  • the semiconductor device 20 including the bonding pad 8 is disposed adjacent to the frame 23 including the conductive portion 22 (for example, at a predetermined position on the frame 23).
  • the conductive portion 22 is connected by a Cu wire 1 as a conductive wire.
  • the semiconductor device according to the present invention is provided with the stress relaxation film 6 having a mechanical strength equal to or higher than that of copper only in the central portion when viewed in plan as shown in FIG.
  • a second wiring layer 7 containing Al is formed so as to cover the stress relaxation film 6. Therefore, as shown in FIGS. 2 and 3, when the Cu wire 1 is bonded to the bonding pad 8, deformation of the surface of the bonding pad 8 made of Al is not hindered and good initial bonding property is ensured.
  • the semiconductor device according to the present invention includes the stress relaxation film 6 having a mechanical strength equal to or higher than that of copper at only the center portion of the bonding pad 8, the stress from the Cu wire 1 is reduced when the Cu wire is bonded. The damage to the semiconductor element 3 is reduced without being directly applied to the semiconductor element 3.
  • the semiconductor device according to the present invention includes the stress relaxation film 6 having a mechanical strength higher than that of copper only at the center of the bonding pad 8, the waste material 10 (see FIG. 2) when the Cu wire 1 is bonded. It is unlikely that a part of the stress relaxation film 6 is included in the above. That is, since there is a low possibility that a fragment of the stress relaxation film 6 is contained in the waste material 10 composed of the first wiring layer 5 and the second wiring layer 7, interfacial delamination (the stress relaxation film 6 of the stress relaxation film 6 is formed). The possibility that separation at the interface between the fragment and the other part of the waste 10 will occur is low. As a result, long-term reliability can be ensured in the semiconductor device 20 and the semiconductor package 24 using the semiconductor device.
  • the insulating layer 104 is formed on the semiconductor element 103.
  • a bonding pad 108 is formed on the insulating layer 104.
  • a coating layer 115 having an opening 116 is formed on the bonding pad 108.
  • the bonding pad 108 is formed on the first wiring layer 105 formed on the insulating layer 104, the barrier metal layer 106 formed on the entire surface of the first wiring layer 105, and the barrier metal layer 106.
  • the second wiring layer 107 is included.
  • the bonding step (the step of connecting the bonding pad 108 and the Cu wire 101) to be described later with respect to the semiconductor package manufacturing method of the comparative example is basically the same as the bonding step in the semiconductor package manufacturing method according to the present invention described above.
  • a frame (not shown) including a conductive part is prepared.
  • a semiconductor device including the bonding pad shown in FIG. 5 is prepared.
  • the semiconductor device is disposed adjacent to the frame (for example, on the frame).
  • a semiconductor package according to the comparative example can be obtained by connecting the bonding pad 108 of the semiconductor device and the conductive portion with a bonding wire.
  • the connection between the bonding pad of the semiconductor device and the bonding wire (Cu wire) is performed as follows. First, the ball portion 102 is formed by heating and melting the joint portion of the Cu wire 101. Then, the ball portion 102 is brought into contact with the bonding pad 108. Thereafter, the tool 109 of the wire bonding apparatus (wire bonder) is brought into contact with the ball portion 102 as shown in FIG. 6 and a load is applied in the direction of the arrow 118. At the same time, by applying ultrasonic waves in the direction of the arrow 119 (see FIG. 6), the surface oxide films on the ball portion surface 102a and the bonding pad surface 108a are mechanically destroyed by plastic deformation.
  • the waste 110 basically includes a waste 107 b from the first wiring layer 107, a finely crushed barrier metal layer 106 b, and a waste 105 b from the second wiring layer 105.
  • the wastes 105b and 107b have the same components, the same mechanical characteristics, and are relatively soft.
  • the crushed barrier layer 106b is relatively hard as compared with the wastes 105b and 107b. Therefore, as shown in FIG.
  • a crack 112 is generated at the interface between the region made of the waste 105b and the waste 107b in the waste 110 and the region made of the barrier metal layer 106b. As the crack 112 progresses, the bonding strength between the bonding pad and the Cu wire 101 decreases. Whether or not the crack 112 has occurred is that the fracture position when the Cu wire 101 is pulled is the interface between the Cu wire 101 and the ball portion 102 or the interface between the insulating layer 104 and the ball portion 102. Can be judged. In particular, since the alloy layer 111 grows after the heat treatment, the above determination becomes easy.
  • the crack as shown in FIG. 8 shown in the comparative example does not occur in the connection between the bonding pad 8 of the semiconductor device 20 and the Cu wire 1.
  • the ball portion 2 is harder than the first wiring layer 5 and the second wiring layer 7, the waste 10 shown in FIG. 2 is generated during wire bonding.
  • the stress relaxation film 6 has a mechanical strength (Mohs's hardness) larger than that of Cu and is disposed only at the center portion of the bonding pad 8, the Cu wire 1 is pressed toward the semiconductor element 3 side. The stress to be applied can be prevented from being directly applied to the semiconductor element 3, and the stress relaxation film 6 is not crushed finely during wire bonding.
  • the waste material 10 is basically composed of the waste material from the first wiring layer 5 and the waste material from the second wiring layer 7, and the region where the stress relaxation film 6 is finely crushed and the first wiring layer. 5 and the area formed by the waste from the second wiring layer 7 does not occur.
  • the semiconductor element 3 according to the present invention may be obtained by die-bonding a lead frame made of Cu or the like using solder or the like.
  • the electrodes on the semiconductor element 3 side and the lead frame side (frame 23 side) are joined together by wires (that is, the bonding pad 8 side on the semiconductor element 3 side and the copper solder 22 on the frame 23 side twice).
  • the semiconductor element 3 side is generally referred to as primary bonding
  • the frame side is generally referred to as secondary bonding.
  • only the semiconductor element 3 side (primary bonding side) is described in detail.
  • Example 1 As the Cu wire, TPCW manufactured by Tanaka Electronics Co., Ltd. having a diameter ⁇ of 30 ⁇ m and a Cu purity of 99.99% was prepared. In addition, a TEG chip manufactured by Hitachi Ultra LSI Co., Ltd. was prepared as a semiconductor element.
  • the TEG chip is a 10 mm ⁇ ⁇ t 0.25 mm (length 10 mm ⁇ width 10 mm ⁇ thickness 0.25 mm) chip having a Daisy pattern with an opening of ⁇ 70 ⁇ m at a pitch of 150 ⁇ m.
  • TiN titanium nitride
  • a TiN layer having a thickness of about 70 nm may be inserted between SiO 2 and Al—Si in order to improve the adhesion strength.
  • the TiN layer may be formed of two layers of Ti and TiN.
  • the diameter of the opening 16 is 70 ⁇ m, whereas in the center (between the Al—Si layer and the Al—Si layer).
  • a chip on which TiN was formed as the stress relaxation film 6 having a diameter of 30 ⁇ m was prepared.
  • a Cu frame prepared by applying 5 ⁇ m of silver plating to oxygen-free copper having a thickness of 0.5 mm was prepared.
  • M10-374FS alloy composition: Sn-5Sb: wt%, melting point: about 240 ° C.
  • a solder paste on the surface of the Cu frame has a 12 mm square opening (12 mm long ⁇ 12 mm wide opening pattern) thickness of 0.2 mm.
  • Printed with a stainless steel mask .
  • the chip semiconductor element
  • the chip can be die-bonded to the surface of the Cu frame by heating the Cu frame on a hot plate set at 280 ° C. for 40 seconds.
  • the Cu frame to which the chip was connected was washed for 5 minutes while applying ultrasonic waves with acetone. In this manner, die bond samples of Examples and Comparative Examples are obtained.
  • Test method As a device (bonder) used for bonding the Cu wire 1 to a bonding pad of a chip (semiconductor element) in the die bond sample, for example, a full auto wire bond FB-880 manufactured by Kaijo Corporation can be used.
  • the die bond sample mentioned above is mounted on this apparatus, and Cu wire is set. Then, wire bonding was performed at a setting of a wire length of 6 mm and a loop height of 100 ⁇ m while spraying a mixed gas of 4 vol% hydrogen and nitrogen at a rate of 5 L / min near the bonding tool.
  • the bonding conditions (specifically, such that the break mode does not cause the ball to peel off) can be obtained.
  • the time was set to instantaneously full power, and wire bonding was performed in full auto.
  • the bonding temperature at this time was 220 ° C.
  • the bonding pad structure of the semiconductor device according to the present invention has low damage to the semiconductor element and has good initial bondability and long-term reliability.
  • Example 2 In the evaluation of Example 1, the same experiment was performed by changing TiN of the stress relaxation film 6 to Ti, tungsten, chromium, molybdenum, platinum, tantalum, and nickel. As a result, the same effect was confirmed.
  • the present invention is particularly advantageously applied to a semiconductor device and a semiconductor package for bonding a Cu wire.

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)

Abstract

　良好な初期接合性と、高い信頼性とを有するＣｕワイヤボンド接合が可能な電極（ボンディングパッド）を有する半導体装置、半導体パッケージ及びそれらの製造方法が得られる。半導体装置は、能動素子と、上記能動素子と電気的に接続されたアルミニウムを主成分とする電極（８）と、上記電極（８）の中央部のみに配置され、機械的強度が銅以上の応力緩和膜（６）とを備える。このようにすれば、ボンディングの際の能動素子へのダメージを少なくすることができ、ボンディングワイヤであるＣｕワイヤとボンディングパッドである電極との良好な接合をすることができる。

Description

半導体装置、半導体パッケージ及びそれらの製造方法
　この発明は、マイコンやパワートランジスタなど能動素子近傍にワイヤボンド用の電極が形成された半導体装置、半導体パッケージ及びそれらの製造方法に関するものである。
　従来、半導体素子の電極と基板電極、または別の半導体素子の電極同士を電気的に繋ぐ方法として、アルミニウム（Ａｌ）、金（Ａｕ）、銅（Ｃｕ）などのワイヤボンドが用いられてきた。特に狭いピッチの電極（小パッド）には、ワイヤの機械的性質などからＡｕワイヤが主に用いられるが、コスト低減のためのＣｕワイヤも適用されてきている。Ｃｕはワイヤ材の中で比較的機械的強度が高いため、半導体素子へのダメージ低減策として、半導体素子側の電極（ボンディングパッド）としてＡｌを主成分とした電極層の表面にＣｕ膜を形成した構成（例えば特開昭６３－１６４３２９号公報（特許文献１）参照）や、半導体素子上に、Ａｌを主成分とした下地層と、バリア層と、ボンディングワイヤと接合するための接合層とがこの順に形成されたボンディングパッドが提案されている（例えば特開２００２－７６０５１号公報（特許文献２）参照）。
特開昭６３－１６４３２９号公報 特開２００２－７６０５１号公報
　ところが、特許文献１に示したように、ボンディングパッド表面に機械的強度の高いＣｕ膜を形成した場合、半導体素子へのダメージは低減されるが、ワイヤボンド時にパッド表面が変形しにくいことからボンディングパッドの表面酸化膜が破れにくく、初期接合性が低下することが問題になっていた。
　また、特許文献２に示したような、機械的強度の高いバリア層を接合層と下地層との間に挿入した場合は、初期接合性をある程度維持しながら半導体素子へのダメージは低減されるが、ワイヤボンディング時に排斥されるボンディングパッドの中に、軟らかい接合層および下地層と硬いバリア層とが混在することになる。そのため、機械的強度差が大きいバリア層と下地および接合層との界面に亀裂が生じる。そして、これが起点となって、下地層まで亀裂（クラック）が進展して、半導体装置の長期信頼性が低下することが問題となっていた。
　本発明は、上記課題を解決するためになされたものであり、この発明の目的は、良好な初期接合性と、高い信頼性とを有するＣｕワイヤボンド接合が可能な電極（ボンディングパッド）を有する半導体装置、半導体パッケージ及びそれらの製造方法を提供することである。
　この発明に従った半導体装置は、能動素子と、上記能動素子と電気的に接続されたアルミニウムを主成分とする電極と、上記電極の中央部のみに配置され、機械的強度が銅以上の応力緩和膜とを備える。
　本発明により、ボンディングの際の半導体素子へのダメージを少なくすることができ、ボンディングワイヤとボンディングパッドとの良好な接合をすることができる。
本発明による半導体装置の実施の形態を示す断面模式図である。 本発明による半導体装置の実施の形態を示す断面模式図である。 本発明による半導体装置の実施の形態を示す断面模式図である。 本発明による半導体パッケージの実施の形態を示す模式図である。 比較例による半導体装置を示す断面模式図である。 比較例による半導体装置を示す断面模式図である。 比較例による半導体装置を示す断面模式図である。 比較例による半導体装置を示す断面模式図である。
　以下、図面に基づいて本発明の実施の形態を説明する。なお、以下の図面において同一または相当する部分には、同一の参照符号を付し、その説明は繰り返さない。
　（実施の形態）
　図１を用いて、本発明による半導体装置の構造を説明する。
　本発明による半導体装置は、能動素子（図示せず）を含む半導体素子３と、絶縁層４と、電極としてのボンディングパッド８とを備える。半導体素子３の上に絶縁層４が形成されている。上記絶縁層４の上に、上記能動素子と電気的に接続されるボンディングパッド８が形成されている。ボンディングパッド８上に、当該ボンディングパッド８の上部表面を規定する開口部１６が形成された被覆層１５が配置されている。ボンディングパッド８は、アルミニウムを主成分とする電極であり、図１に示したＣｕワイヤ１がワイヤボンディングされるパッド電極である。ボンディングパッド８は、第１配線層５と、応力緩和膜６と、第２配線層７とを含む。第１配線層５および第２配線層７は、それぞれアルミニウムを主成分とする導電体層である。第１配線層５は、上記絶縁層４上に形成されている。上記第１配線層の上に、応力緩和膜６が形成されている。応力緩和膜６上には第２配線層７が形成されている。応力緩和膜６は、平面視においてボンディングパッド８の中央部にのみ配置される。応力緩和膜６は、その機械的強度（モース硬度）が銅以上となっている（つまり応力緩和膜６のモース硬度は、銅のモース硬度より大きくなっている）。第２配線層７上に上記被覆層１５が配置されている。
　図１に示した本発明による半導体装置は、ボンディングパッド８の中央部のみに銅以上の機械的強度を有する応力緩和膜６を備えているため、後述するようにＣｕワイヤ１接合時にＡｌからなるボンディングパッド８の表面の変形を妨げず、良好な初期接合性を確保できる。
　図１を用いて、半導体装置の製造方法を説明する。
　まず、従来周知の方法により能動素子（図示せず）が形成された半導体素子３を準備する。半導体素子３は、たとえば半導体基板と、当該半導体基板に形成された能動素子とを含んでいてもよい。この能動素子は、たとえばマイコン、パワートランジスタなどを構成する素子であってもよい。そして、半導体素子３の上部表面上にＣＶＤ法や熱酸化法などにより絶縁層４を形成する。その上に、スパッタリング法などによりＡｌからなる第１配線層５を形成する。次に、第１配線層５上に応力緩和膜６を形成する。応力緩和膜６を形成するための方法として、従来周知の任意の方法を用いることができる。たとえば、第１配線層５上に、図１に示した応力緩和膜６が形成されるべき領域に開口パターンを有するレジスト膜を、フォトリソグラフィ法を用いて形成する。そして、スパッタリング法などにより、機械的強度が銅以上であるチタン（Ｔｉ）などからなる導電体層（図示せず）を、上記開口パターン内部およびレジスト膜上に形成する。続いて、薬液などを用いてレジスト膜を除去する。この結果、レジスト膜上に形成されていた導電体層の部分がレジスト膜とともに除去される（リフトオフ）。このようにして、ボンディングパッド８の平面視における中央部のみに応力緩和膜６を形成することができる。
　その後、応力緩和膜６上および第１配線層５の露出した上部表面を覆うように、スパッタリング法などにより第２配線層７を形成する。この第２配線層７上に、フォトリソグラフィ法を用いてレジスト膜（図示せず）を形成する。当該レジスト膜には、ボンディングパッド８の平面形状に対応する開口パターンが形成されている。このレジスト膜をマスクとして用いて、だ２配線層７および第１配線層５を部分的に除去することにより、所定の平面形状を有するボンディングパッド８を形成する。その後、レジスト膜を除去する。
　さらに、第２配線層７上に、被覆層１５となるべき膜を、ＣＶＤ法などを用いて形成する。この膜上に、図１に示した開口部１６となる領域に開口パターンが形成されたレジスト膜をフォトリソグラフィ法などを用いて形成する。そして、当該レジスト膜をマスクとして用いて、開口パターン内において露出している上記膜を部分的に除去する。この結果、上記膜において図１に示す開口部１６が形成される。その後、レジスト膜を除去する。この結果、開口部１６を有する被覆層１５を形成することができる。このようにして、図１に示した本発明による半導体装置を得ることができる。
　次に、図１～図４を用いて、図１に示した半導体装置を用いた、本発明による半導体パッケージの製造方法を説明する。
　まず、導電部２２を含むフレーム２３（図４参照）を準備する。次に、上記の製造方法により作製された半導体装置２０を上記フレーム２３に隣接して（具体的にはフレーム２３上の所定の位置に）配置する。なお、フレーム２３と半導体装置２０とは、互いに接続層などにより接続固定されていてもよい。半導体装置２０の上部表面には、図１に示した断面構造のボンディングパッド８が複数形成されている。また、フレーム２３には、半導体装置２０を配置する領域を囲むように、複数の導電部２２が形成されている。上記半導体装置２０のボンディングパッド８と上記導電部２２とを、Ｃｕワイヤ１で接続することにより、本発明による半導体パッケージを得ることができる。
　次に、本発明による半導体装置による効果をより詳しく説明するため、上記半導体装置のボンディングパッド８とＣｕワイヤ１との接続工程を以下に説明する。図２のように、Ｃｕワイヤ１の接合部として、Ｃｕワイヤ１の端部を加熱溶融することによってボール部２を形成する。このボンディングパッド８の表面にボール部２の表面を接触させる。この後、ワイヤボンド装置（ワイヤボンダ）のツールをボール部２に接触させ、ボール部２をボンディングパッド８側に押圧するように荷重を加えるとともに超音波を印加する。この結果、Ｃｕワイヤ１のボール部２の表面と、ボンディングパッド８の表面との表面酸化膜を塑性変形により機械的に破壊できる。そして、ボール部２とボンディングパッド８との表面のうち上記表面酸化膜が破壊され、互いに接触した部分（接合領域）において、熱拡散が起きることにより、図２および図３に示す合金層１１が形成される。そして、Ｃｕワイヤ１が図２および図３に示すように半導体素子３側に押し込まれた状態で、ボンディングパッド８とＣｕワイヤ１のボール部２とが接続固定される。
　このようにして、Ｃｕワイヤ１をボンディングパッド８にワイヤボンディング（接合）することができる。このとき、応力緩和膜６がボンディングパッド８の平面視における中央部に予め形成されているため、Ｃｕワイヤ１を半導体素子３側に押圧する（ワイヤボンディングを行なう）ことに起因して半導体素子３に加わる応力の値を小さくできる（つまり、応力緩和膜６を半導体素子３の保護層として利用できる）。また、ボンディングパッド８の中央部のみに応力緩和膜６が形成されているので、ワイヤボンディングの結果として形成される排斥物１０（図２参照）に、応力緩和膜６に起因する合金層が含まれる可能性を低くできる。このため、当該排斥物１０において、上記合金層の存在に起因して亀裂が発生するといった問題が起きることを避けることができる。
　なお、上記半導体素子３上のボンディングパッド８上に、開口部１６（図１参照）と同様形状の開口パターンを有するマスクを形成し、スパッタ装置などでボンディングパッド８の表面およびマスクの上部表面上に所定厚さのＣｕ層（図示せず）を形成することができる。その後、マスクを除去することにより、ボンディングパッド８の表面上のみにＣｕ層を形成できる。
　このとき、当該Ｃｕ層の形成に先立って、逆電極スパッタやアルゴンプラズマなどで、ボンディングパッド８の表面の酸化膜を除去する工程を実施することが望ましく、Ｃｕ層の成膜時の真空度が高い方がより望ましい。この後、高真空または窒素や水素、またはこれらの混合ガス雰囲気下（つまりＣｕ層などが通常の大気雰囲気より酸化しにくい環境下）で、加熱温度を２００℃以上かつボンディングパッド８の構成材料の融点以下とした熱処理を行なうことにより、ボンディングパッド８の表面にＣｕ－Ａｌ合金からなる合金層（図示せず）を形成してもよい。
　次に、図３および図４を用いて、半導体パッケージ２４の構造を説明する。
　本発明による半導体パッケージ２４は、導電部２２を含むフレーム２３に隣接して（たとえばフレーム２３上の所定の位置に）、ボンディングパッド８を含む半導体装置２０が配置されており、ボンディングパッド８と上記導電部２２とが導電線としてのＣｕワイヤ１で接続されている。
　ここで、本発明による半導体装置は、図１に示すように平面視した場合の中央部のみに銅以上の機械的強度を有する応力緩和膜６を備えている。また、応力緩和膜６の上を覆うようにＡｌを含む第２配線層７が形成されている。このため、図２および図３に示すようにＣｕワイヤ１をボンディングパッド８に接合する時に、Ａｌからなるボンディングパッド８の表面の変形を妨げず、良好な初期接合性を確保する。
　また、本発明による半導体装置は、ボンディングパッド８の中央部のみに銅以上の機械的強度を有する応力緩和膜６を備えているため、Ｃｕワイヤ接合時にＣｕワイヤ１からの応力が絶縁層４や半導体素子３に直接的に加えられることがなく、半導体素子３へのダメージを低減する。
　さらに、本発明による半導体装置は、ボンディングパッド８の中央部のみに銅以上の機械的強度を有する応力緩和膜６を備えているため、Ｃｕワイヤ１の接合時に、排斥物１０（図２参照）などの中に応力緩和膜６の一部が含まれる可能性が低い。つまり、第１配線層５及び第２配線層７からなる排斥物１０の内部に応力緩和膜６の断片が含有される可能性が低いため、排斥物１０内部において界面剥離（応力緩和膜６の断片と排斥物１０の他の部分との界面における剥離）が起きる可能性が低い。この結果、半導体装置２０および当該半導体装置を用いた半導体パッケージ２４において長期信頼性を確保することができる。
　以下、比較例と対比しながら本発明による半導体装置の効果をより具体的に説明する。
　まず、図５を用いて、比較例の半導体装置の構造を説明する。
　比較例の半導体装置では、半導体素子１０３の上に絶縁層１０４が形成されている。上記絶縁層１０４の上にはボンディングパッド１０８が形成されている。ボンディングパッド１０８上には、開口部１１６を有する被覆層１１５が形成されている。ボンディングパッド１０８は、絶縁層１０４上に形成された第１配線層１０５と、上記第１配線層１０５の上に、全面にわたって形成されたバリアメタル層１０６と、上記バリアメタル層１０６の上に形成された第２配線層１０７とを含む。
　図６～図８を参照して、図５に示した比較例の半導体装置を用いた、比較例の半導体パッケージの製造方法を説明する。
　比較例の半導体パッケージの製造方法について後述するボンディング工程（ボンディングパッド１０８とＣｕワイヤ１０１との接続工程）は、既に述べた本発明による半導体パッケージの製造方法におけるボンディング工程と基本的に同様である。まず、導電部を含むフレーム（図示せず）を準備する。次に、図５に示したボンディングパッドを備える半導体装置を準備する。そして、当該半導体装置を上記フレームに隣接して（たとえばフレーム上に）配置する。上記半導体装置のボンディングパッド１０８と上記導電部とをボンディングワイヤで接続することにより、比較例による半導体パッケージを得ることができる。
　上記半導体装置のボンディングパッドとボンディングワイヤ（Ｃｕワイヤ）との接続は以下のように行なう。まず、Ｃｕワイヤ１０１の接合部を加熱溶融することによってボール部１０２を形成する。そして、当該ボール部１０２をボンディングパッド１０８と接触させる。この後、ワイヤボンド装置（ワイヤボンダ）のツール１０９を、図６のようにボール部１０２に接触させ、矢印１１８の方向に荷重を加える。また同時に、矢印１１９（図６参照）の方向に超音波を印加することにより、ボール部表面１０２ａとボンディングパッド表面１０８ａとの表面酸化膜を塑性変形により機械的に破壊する。そして、ボール部表面１０２ａとボンディングパッド表面１０８ａとの接合領域において熱拡散が起きることにより、図７に示す合金層１１１が形成される。そして、Ｃｕワイヤ１０１が図７および図８に示すように半導体素子１０３側に押し込まれた状態、ボンディングパッドとＣｕワイヤ１０１とが接続固定される。このようにして、Ｃｕワイヤ１０１をボンディングパッドにワイヤボンディング（接合）することができる。このとき、ボール部１０２は、第１配線層１０７よりも硬いため、図７に示す排斥物１１０が生じる。またこの際、バリアメタル層１０６は破壊され、そのまま残存するバリアメタル層１０６ａと、ボール部１０２近傍にある細かく破砕されたバリアメタル層１０６ｂと、排斥物１１０に巻き込まれたバリアメタル層１０６ｃとに大きく分離することになる。排斥物１１０は、基本的に第１配線層１０７からの排斥物１０７ｂと、細かく破砕されたバリアメタル層１０６ｂと、第２配線層１０５からの排斥物１０５ｂとからなる。この際、排斥物１０５ｂ、１０７ｂは成分が同一であり、機械的特性も同じで比較的軟らかい。一方、破砕されたバリア層１０６ｂは上記排斥物１０５ｂ、１０７ｂなどに比べて相対的に硬い。そのため、図８に示すように排斥物１１０内の排斥物１０５ｂおよび排斥物１０７ｂからなる領域と、バリアメタル層１０６ｂからなる領域との界面でクラック１１２が発生する。そして、当該クラック１１２が進展していくことで、ボンディングパッドとＣｕワイヤ１０１との接合強度が低下する。なお、クラック１１２が発生しているかどうかは、Ｃｕワイヤ１０１を引っ張った時の破断位置が、Ｃｕワイヤ１０１とボール部１０２との界面であるか、絶縁層１０４とボール部１０２との界面であるかで判断することができる。特に熱処理後は合金層１１１が成長するため、上記のような判断が容易となる。
　一方、本発明による半導体パッケージ２４では、半導体装置２０のボンディングパッド８とＣｕワイヤ１との接続において、比較例で示した図８のようなクラックは発生しない。本発明において、ボール部２は、第１配線層５及び第２配線層７よりも硬いため、ワイヤボンディング時には図２に示す排斥物１０が生じる。また、応力緩和膜６は、機械的強度（モース硬度）がＣｕよりも大きく、ボンディングパッド８の中央部のみに配置されているので、Ｃｕワイヤ１が半導体素子３側に押圧されることに起因する応力が半導体素子３に直接的に加えられることを抑制できるとともに、応力緩和膜６はワイヤボンディング時に細かく破砕されない。よって、ワイヤボンディング後（接合後）の応力緩和膜６は、細かく破砕されて排斥物１０内に巻き込まれることはない。それゆえ、排斥物１０は、基本的に第１配線層５からの排斥物と、第２配線層７からの排斥物とからなり、応力緩和膜６が細かく破砕された領域と第１配線層５および第２配線層７からの排斥物により構成される領域との界面も生じない。
　したがって、本発明による半導体装置のボンディングパッド構造を用いれば、半導体素子３へのダメージが低く、Ｃｕワイヤとボンディングパッドとの接合部における良好な初期接合性及び長期信頼性を有することが示された。
　なお、ハンドリング性を向上させるために、本発明による半導体素子３は、Ｃｕなどからなるリードフレームにはんだなどを用いてダイボンドしたものを用いてもよい。通常、半導体素子３側とリードフレーム側（フレーム２３側）の各電極同士をワイヤで接合する（すなわち、半導体素子３側のボンディングパッド８側とフレーム２３側の銅でん部２２との２回、ワイヤボンドを行なう。この場合、半導体素子３側を一次ボンディング、フレーム側を２次ボンディングと称することが一般的である）。しかし、本発明の効果は、半導体素子３側で顕著に得られるため、上述した実施の形態においては、半導体素子３側（１次ボンディング側）についてのみ詳細に述べている。
　（実施例１）
　（試料）
　Ｃｕワイヤとして、直径φ：３０μｍ、Ｃｕ純度９９．９９％の、田中電子工業株式会社製のＴＰＣＷを用意した。また、半導体素子として、日立超ＬＳＩ株式会社製のＴＥＧチップを用意した。ＴＥＧチップは、１５０μｍピッチでφ７０μｍ開口のＤａｉｓｙパターンを有する１０ｍｍ□×ｔ０．２５ｍｍ（縦１０ｍｍ×横１０ｍｍ×厚さ０．２５ｍｍ）のチップである。当該チップに形成されているボンディングパッド８は、ＳｉＯ２／Ａｌ－Ｓｉ／窒化チタン（ＴｉＮ）／Ａｌ―Ｓｉ＝１５０／１００／５００／１００／１０００ｎｍという積層構造を有する。なお、今回の実験では形成していないが、ＳｉＯ２とＡｌ－Ｓｉとの間には、密着強度を向上させるために、約７０ｎｍの厚みのＴｉＮ層を挿入してもよい。さらに、ＴｉＮ層は、ＴｉとＴｉＮの２層から形成されてもよい。
　上述したチップについて、実施例の試料として、図１に示すように、開口部１６の径が７０μｍであるのに対して、中央部に（上記Ａｌ－Ｓｉ層とＡｌ－Ｓｉ層との間に）直径３０μｍの応力緩和膜６としての上記ＴｉＮを形成したチップを準備した。
　また、比較例の試料として、図５に示すように、開口部１１６よりも大きい範囲でバリアメタル層１０６としてのＴｉＮを形成したチップを準備した。
　また、Ｃｕフレームとして、厚さ０．５ｍｍの無酸素銅に、銀めっきを５μｍ施したものを用意した。Ｃｕフレーム表面に、ソルダーペーストとして、例えばＭ１０－３７４ＦＳ（合金組成：Ｓｎ－５Ｓｂ：ｗｔ％、融点約２４０℃）を１２ｍｍ□開口（縦１２ｍｍ×横１２ｍｍの開口パターン）を有する厚さ０．２ｍｍのステンレスマスクで印刷した。そして、当該ソルダーペースト表面上にチップ（半導体素子）を搭載後、２８０℃に設定されたホットプレート上でＣｕフレームを４０秒間加熱することにより、チップをＣｕフレーム表面にダイボンドすることができる。その後、チップが接続されたＣｕフレームをアセトンで超音波をかけながら５分間洗浄した。このようにして、実施例および比較例のダイボンドサンプルを得る。
　（試験方法）
　上記ダイボンドサンプルにおけるチップ（半導体素子）のボンディングパッドに、上記Ｃｕワイヤ１をボンディングするために用いる装置（ボンダ）として、例えば株式会社カイジョー製の、フルオートワイヤボンドＦＢ－８８０を使うことが出来る。この装置に、上述したダイボンドサンプルを載せ、また、Ｃｕワイヤをセットする。そして、４体積％水素と窒素との混合ガスを５Ｌ／ｍｉｎで、ボンディングツール近傍に吹き付けながら、ワイヤ長６ｍｍ、ループ高さ１００μｍの設定でワイヤボンディングを行なった。なお、チップのボンディングパッドに接続されたＣｕワイヤにピンセットで応力をかけて破断させたときに、破断モードがボール剥がれにならないような良好な接合が得られるように、ボンディングの条件（具体的には超音波パワーと荷重）をあわせ、時間については瞬時にフルパワーとなるように設定して、フルオートでワイヤボンディングを行なった。このときのボンディング温度を２２０℃とした。
　そして、上記実施例および比較例の試料について、上記で設定した条件で、Ｃｕワイヤ１を５０本、それぞれ対応するボンディングパッド８へ５０箇所接続した。その後、２５箇所についてはワイヤプルテストを実施して破断モードを確認した。また、残り２５箇所については、それぞれの接合部断面を、樹脂に埋め込み後研摩し、電子顕微鏡で５０００倍にて観察した。
　（結果）
　実施例の試料については、ワイヤプルテストを行った２５箇所は全てネック切れで良好なモードであることを確認した。また、断面観察を行った２５箇所全てにおいて、図８に示したようなクラックが発生していないことを確認した。
　一方、比較例の試料については、ワイヤプルテストを行った２５箇所について、２０箇所がボール界面剥がれと問題がある破断モードであった。また、断面観察を行った２０箇所について、図８に示したようなクラック１１２が発生していることを確認した。
　以上のことから、本発明による半導体装置のボンディングパッド構造が、半導体素子へのダメージが低く、良好な初期接合性及び長期信頼性を有することが示された。
　（実施例２）
　実施例１の評価において、応力緩和膜６のＴｉＮを、Ｔｉ、タングステン、クロム、モリブデン、白金、タンタル、ニッケルに変えて、同様の実験を行った。その結果、同様の効果を確認した。
　今回開示された実施の形態および実施例はすべての点で例示であって制限的なものではないと考えられるべきである。本発明の範囲は上記した説明ではなくて請求の範囲によって示され、請求の範囲と均等の意味および範囲内でのすべての変更が含まれることが意図される。
　この発明は、Ｃｕワイヤを接合する半導体装置および半導体パッケージに対して特に有利に適用される。
　１，１０１　Ｃｕワイヤ、２，１０２　ボール部、３，１０３　半導体素子、４，１０４　絶縁層、５，１０５　第１配線層、６　応力緩和膜、７，１０７　第２配線層、８，１０８　ボンディングパッド、９　ツール、１０，１１０　排斥物、１１，１１１　合金層、１５，１１５　被覆層、１６，１１６　開口部、２０　半導体装置、２２　導電部、２３　フレーム、２４　半導体パッケージ、１０２ａ　ボール部表面、１０５ａ　残存する第１配線層、１０５ｂ　第１配線層からの排斥物、１０６　バリアメタル層、１０６ｂ　細かく破砕されたバリアメタル層、１０６ｃ　巻き込まれたバリアメタル層、１０７ａ　残存する第２配線層、１０７ｂ　第２配線層からの排斥物、１０８ａ　ボンディングパッド表面、１０９　ツール、１１２　クラック、１１８，１１９　矢印。

Claims (6)

  1. 　能動素子と、
    　前記能動素子と電気的に接続されたアルミニウムを主成分とする電極（８）と、
    　前記電極（８）の中央部のみに配置され、
    　機械的強度が銅以上の応力緩和膜（６）とを備えた、半導体装置。
  2. 　前記応力緩和膜（６）が、チタン、タングステン、クロム、モリブデン、白金、タンタル、ニッケル、またはこれらの合金のいずれかを含む、請求項１に記載の半導体装置。
  3. 　導電部（２２）を含むフレーム（２３）と、
    　前記フレーム（２３）に隣接して配置された請求項１に記載の半導体装置と、
    　前記半導体装置の前記電極（８）と前記導電部（２２）とを電気的に接続する導電線（１）とを備えた、半導体パッケージ。
  4. 　半導体基板上に能動素子を形成する工程と、
    　前記能動素子上にアルミニウムを主成分とする電極（８）を形成する工程とを備え、
    　前記電極（８）を形成する工程は、前記電極（８）の中央部のみに配置され、機械的強度が銅以上の応力緩和膜（６）を形成する工程を含む、半導体装置の製造方法。
  5. 　前記応力緩和膜（６）が、チタン、タングステン、クロム、モリブデン、白金、タンタル、ニッケル、またはこれらの合金のいずれかを含む、請求項４に記載の半導体装置の製造方法。
  6. 　導電部（２２）を含むフレーム（２３）を準備する工程と、
    　前記フレーム（２３）に隣接して、請求項４に記載の製造方法により製造された半導体装置（２０）を配置する工程と、
    　前記半導体装置（２０）の前記電極（８）と前記導電部（２２）とを導電線（１）で接続する工程とを備えた、半導体パッケージの製造方法。
PCT/JP2011/063030 2010-07-08 2011-06-07 半導体装置、半導体パッケージ及びそれらの製造方法 WO2012005073A1 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2012523803A JPWO2012005073A1 (ja) 2010-07-08 2011-06-07 半導体装置、半導体パッケージ及びそれらの製造方法

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2010-155715 2010-07-08
JP2010155715 2010-07-08

Publications (1)

Publication Number Publication Date
WO2012005073A1 true WO2012005073A1 (ja) 2012-01-12

Family

ID=45441059

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2011/063030 WO2012005073A1 (ja) 2010-07-08 2011-06-07 半導体装置、半導体パッケージ及びそれらの製造方法

Country Status (2)

Country Link
JP (1) JPWO2012005073A1 (ja)
WO (1) WO2012005073A1 (ja)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5591411B1 (ja) * 2013-07-03 2014-09-17 パイオニア株式会社 有機ｅｌ装置

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5882526A (ja) * 1981-11-11 1983-05-18 Toshiba Corp 半導体装置
JPS63148646A (ja) * 1986-12-12 1988-06-21 Toshiba Corp 半導体装置
JPH0494752U (ja) * 1990-12-29 1992-08-17
JPH08203953A (ja) * 1995-01-25 1996-08-09 Nissan Motor Co Ltd 半導体装置のボンディングパッド部の構造
JP2003258019A (ja) * 2002-03-07 2003-09-12 Seiko Epson Corp 半導体装置およびその製造方法
JP2010238946A (ja) * 2009-03-31 2010-10-21 Sanyo Electric Co Ltd 半導体装置及びその製造方法

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5882526A (ja) * 1981-11-11 1983-05-18 Toshiba Corp 半導体装置
JPS63148646A (ja) * 1986-12-12 1988-06-21 Toshiba Corp 半導体装置
JPH0494752U (ja) * 1990-12-29 1992-08-17
JPH08203953A (ja) * 1995-01-25 1996-08-09 Nissan Motor Co Ltd 半導体装置のボンディングパッド部の構造
JP2003258019A (ja) * 2002-03-07 2003-09-12 Seiko Epson Corp 半導体装置およびその製造方法
JP2010238946A (ja) * 2009-03-31 2010-10-21 Sanyo Electric Co Ltd 半導体装置及びその製造方法

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5591411B1 (ja) * 2013-07-03 2014-09-17 パイオニア株式会社 有機ｅｌ装置
WO2015001627A1 (ja) * 2013-07-03 2015-01-08 パイオニア株式会社 光学装置及び有機ｅｌ装置

Also Published As

Publication number Publication date
JPWO2012005073A1 (ja) 2013-09-02

Similar Documents

Publication Publication Date Title
JP6430007B2 (ja) 半導体装置および半導体装置の製造方法
JP5535469B2 (ja) 半導体装置の製造方法
KR100580970B1 (ko) 반도체장치
JP2010171386A (ja) 半導体装置及びその製造方法
WO2013018238A1 (ja) ボールボンディングワイヤ
WO2012049893A1 (ja) 高温半導体素子用平角状銀（Ａｇ）クラッド銅リボン
TWI599664B (zh) 用於功率模組封裝之金屬帶材
JP2014082367A (ja) パワー半導体装置
US20110192885A1 (en) Wirebonding process
JPH0964258A (ja) 大電力半導体デバイス
US8222736B2 (en) Semiconductor device with Al pad
TW200416915A (en) Wirebonding insulated wire
WO2007034791A1 (ja) 半田層及びこれを用いた放熱基板並びにその製造方法
EP1367644A1 (en) Semiconductor electronic device and method of manufacturing thereof
US20070212869A1 (en) Wire bonding method for preventing polymer cracking
JP3262657B2 (ja) ボンディング方法及びボンディング構造
WO2012005073A1 (ja) 半導体装置、半導体パッケージ及びそれらの製造方法
JP2007150342A (ja) 半導体装置およびその製造方法
JP2013118310A (ja) 半導体装置
JP2013183067A (ja) 半導体発光装置、半導体発光装置の製造方法、リードフレームおよびリードフレームの製造方法
JP4481065B2 (ja) 半導体装置の製造方法
JP2010205974A (ja) 半導体装置
TWI290761B (en) Semiconductor device and a method of manufacturing the same
JP5195715B2 (ja) 半導体装置の部品実装方法、及び半導体装置の実装部品
JPH1012670A (ja) 半導体素子、半導体装置、および半導体装置の検査方法

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 11803409

Country of ref document: EP

Kind code of ref document: A1

WWE Wipo information: entry into national phase

Ref document number: 2012523803

Country of ref document: JP

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 11803409

Country of ref document: EP

Kind code of ref document: A1