KR900010790A - 스태틱형 반도체메모리 - Google Patents

스태틱형 반도체메모리 Download PDF

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Publication number
KR900010790A
KR900010790A KR1019890019724A KR890019724A KR900010790A KR 900010790 A KR900010790 A KR 900010790A KR 1019890019724 A KR1019890019724 A KR 1019890019724A KR 890019724 A KR890019724 A KR 890019724A KR 900010790 A KR900010790 A KR 900010790A
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KR
South Korea
Prior art keywords
signal
write
bit line
pair
detection signal
Prior art date
Application number
KR1019890019724A
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English (en)
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KR930000635B1 (ko
Inventor
마사타케 마츠이
가츠히코 사토
다카히로 하마노
Original Assignee
아오이 죠이치
가부시키가이샤 도시바
다케다이 마사다카
도시바 마이크로일렉트로닉스 가부시키가이샤
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Application filed by 아오이 죠이치, 가부시키가이샤 도시바, 다케다이 마사다카, 도시바 마이크로일렉트로닉스 가부시키가이샤 filed Critical 아오이 죠이치
Publication of KR900010790A publication Critical patent/KR900010790A/ko
Application granted granted Critical
Publication of KR930000635B1 publication Critical patent/KR930000635B1/ko

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
    • G11C11/418—Address circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
    • G11C11/419—Read-write [R-W] circuits

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Static Random-Access Memory (AREA)
  • Dram (AREA)

Abstract

내용 없음

Description

스태틱형 반도체메모리
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본 발명의 1실시예에 따른 SRAM의 일부를 나타낸 구성 설명도, 제3도는 제1도중 비트선 이퀄라이즈ㆍ프리차지신호발생회로의 일례를 나타낸 회로도, 제4도는 제1도중 기록데이터버퍼회로의 일례를 나타낸 회로도.

Claims (2)

  1. 워드선에 의해 선택적으로 제어되어 상보적인 기억데이터를 비트선쌍으로 출력하는 스태틱형 메모리셀(MC1, MC2,…)이 격자형상으로 배열된 메모리셀 어레이(MA)와, 어드레스신호의 천이를 검출해서 일정한 길이의 단안정펄스인 어드레스천이검출신호를 출력하는 어드레스천이검출신호(ADT), 상기 어드레스천이검출신호에 동기해서 활성화되는 프리차지신호 및, 기록중이 아닌 때에는 어드레스천이검출신호에 동기해서 활성화되는 이퀄라이즈신호를 별개로 출력하는 비트선 이퀄라이즈 프리차지신호발생회로(11), 상기 프리차지신호가 게이트에 입력되고 드레인ㆍ소오스간이 비트선 프리차지전원과 상기비트선쌍간에 접속된 비트선 프리차지용 MOS트랜지스터쌍(Q5, Q6), 상기 이퀄라이즈신호가 게이트에 입력되고 드레인ㆍ소오스간이 상기 비트선쌍간에 접속된 비트선 이퀄라이즈용 MOS트랜지스터(Q7), 기록시에 활성화되는 내부기록신호가 게이트에 부여되고 기록데이터선쌍과 비트선쌍간에 접속된 기록트랜지스터쌍(Q12, Q13) 및, 기록시에 상기 기록데이터선쌍에 상보적인 데이터를 부여하는 기록데이터버퍼회로(12)를 구비하여 구성된 것을 특징으로 하는 스태틱형 반도체메모리.
  2. 제1항에 있어서, 상기 기록데이터버퍼회로(12)는 독출시에 상기 기록데이터선쌍으로 하이레벨의 전위를 부여하여 기록데이터선상을 리셋트시키고, 기록시에는 상기 기록데이터선쌍으로 상보적인 데이터를 부여하며, 기록시에 어드레스천이검출신호(øATD)가 발생된 때에는 그 어드레스천이검출신호(øATD)에 에 동기해서 상기 기록데이터선쌍을 일정기간 리셋트시키는 것을 특징으로 하는스태틱형 반도체메모리.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019890019724A 1988-12-28 1989-12-27 스태틱형 반도체메모리 KR930000635B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP63333618A JPH07118196B2 (ja) 1988-12-28 1988-12-28 スタティック型半導体メモリ
JP88-333618 1988-12-28

Publications (2)

Publication Number Publication Date
KR900010790A true KR900010790A (ko) 1990-07-09
KR930000635B1 KR930000635B1 (ko) 1993-01-28

Family

ID=18268065

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Application Number Title Priority Date Filing Date
KR1019890019724A KR930000635B1 (ko) 1988-12-28 1989-12-27 스태틱형 반도체메모리

Country Status (3)

Country Link
US (1) US5091889A (ko)
JP (1) JPH07118196B2 (ko)
KR (1) KR930000635B1 (ko)

Families Citing this family (52)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2892757B2 (ja) * 1990-03-23 1999-05-17 三菱電機株式会社 半導体集積回路装置
JP2531829B2 (ja) * 1990-05-01 1996-09-04 株式会社東芝 スタティック型メモリ
JP2963504B2 (ja) * 1990-07-23 1999-10-18 沖電気工業株式会社 半導体記憶装置
US5297090A (en) * 1990-12-13 1994-03-22 Sgs-Thomson Microelectronics, Inc. Semiconductor memory with column decoded bit line equilibrate
US5305268A (en) * 1990-12-13 1994-04-19 Sgs-Thomson Microelectronics, Inc. Semiconductor memory with column equilibrate on change of data during a write cycle
US5258952A (en) * 1990-12-14 1993-11-02 Sgs-Thomson Microelectronics, Inc. Semiconductor memory with separate time-out control for read and write operations
WO1992022070A1 (en) * 1991-05-30 1992-12-10 Integrated Device Technology, Inc. Static memories and methods of reading static memories
US5228106A (en) * 1991-05-30 1993-07-13 Integrated Device Technology, Inc. Track-and-regenerate amplifiers and memories using such amplifiers
KR940003408B1 (ko) * 1991-07-31 1994-04-21 삼성전자 주식회사 어드레스 천이 검출회로(atd)를 내장한 반도체 메모리 장치
KR950005095Y1 (ko) * 1992-03-18 1995-06-22 문정환 양방향성 그로벌 비트 라인을 갖는 dram
JP3072871B2 (ja) * 1992-03-19 2000-08-07 株式会社東芝 半導体メモリ装置
KR970011971B1 (ko) * 1992-03-30 1997-08-08 삼성전자 주식회사 반도체 메모리 장치의 비트라인 프리차아지회로
US5508964A (en) * 1993-01-08 1996-04-16 Texas Instruments Incorporated Write recovery time minimization for Bi-CMOS SRAM
JP3358030B2 (ja) * 1993-01-22 2002-12-16 日本テキサス・インスツルメンツ株式会社 半導体メモリ装置及びその初期化方法
KR970003810B1 (ko) * 1993-04-14 1997-03-22 삼성전자 주식회사 어드레스 천이 검출회로를 내장하는 불휘발성 반도체 집적회로
US5506808A (en) * 1993-09-14 1996-04-09 Fujitsu Limited Semiconductor memory device and method for reading data
US5369316A (en) * 1993-11-22 1994-11-29 United Microelectronics Corporation Advanced output buffer with reduced voltage swing at output terminal
JP3088232B2 (ja) * 1994-01-11 2000-09-18 沖電気工業株式会社 半導体記憶回路
JPH07312084A (ja) * 1994-05-18 1995-11-28 Toshiba Corp キャッシュメモリ内蔵メモリ装置
US5487038A (en) * 1994-08-15 1996-01-23 Creative Integrated Systems, Inc. Method for read cycle interrupts in a dynamic read-only memory
US5530677A (en) * 1994-08-31 1996-06-25 International Business Machines Corporation Semiconductor memory system having a write control circuit responsive to a system clock and/or a test clock for enabling and disabling a read/write latch
KR0127216B1 (ko) * 1994-11-24 1998-04-02 문정환 반도체 메모리장치
US5572473A (en) * 1994-11-29 1996-11-05 Sony Corporation Of Japan Bit line conditioning circuit for random access memory
US5559752A (en) * 1995-08-14 1996-09-24 Alliance Semiconductor Corporation Timing control circuit for synchronous static random access memory
KR0177763B1 (ko) * 1995-11-13 1999-04-15 김광호 비트라인 프리차아지회로
JP3277112B2 (ja) * 1996-01-31 2002-04-22 株式会社東芝 半導体記憶装置
KR100225947B1 (ko) * 1996-06-27 1999-10-15 김영환 라이트 리커버리 보장 회로
US5717633A (en) * 1997-02-11 1998-02-10 Artisan Components, Inc. Low power consuming memory sense amplifying circuitry
US5886929A (en) * 1997-04-21 1999-03-23 Artisan Components, Inc. High speed addressing buffer and methods for implementing same
US5889715A (en) * 1997-04-23 1999-03-30 Artisan Components, Inc. Voltage sense amplifier and methods for implementing the same
US5968192A (en) * 1997-05-09 1999-10-19 Artisan Components, Inc. Programmable universal test interface and method for making the same
US6044481A (en) * 1997-05-09 2000-03-28 Artisan Components, Inc. Programmable universal test interface for testing memories with different test methodologies
US5881008A (en) * 1997-09-12 1999-03-09 Artisan Components, Inc. Self adjusting pre-charge delay in memory circuits and methods for making the same
US5965925A (en) * 1997-10-22 1999-10-12 Artisan Components, Inc. Integrated circuit layout methods and layout structures
US5940337A (en) * 1997-10-23 1999-08-17 Integrated Silicon Solution, Inc. Method and apparatus for controlling memory address hold time
US5999482A (en) * 1997-10-24 1999-12-07 Artisan Components, Inc. High speed memory self-timing circuitry and methods for implementing the same
US5930178A (en) * 1997-11-17 1999-07-27 International Business Machines Corporation Bitline voltage stabilization device and method
US6016390A (en) * 1998-01-29 2000-01-18 Artisan Components, Inc. Method and apparatus for eliminating bitline voltage offsets in memory devices
KR100271806B1 (ko) * 1998-07-18 2000-11-15 김영환 반도체 메모리의 라이트 리커버리 시간 제어회로 및 제어방법
JP2000268576A (ja) * 1999-03-16 2000-09-29 Toshiba Microelectronics Corp 半導体記憶装置
KR100384775B1 (ko) 2000-11-23 2003-05-22 주식회사 하이닉스반도체 쿼드 데이터 레이트 싱크로노스 에스램의 리드/라이트를위한 워드라인 및 비트라인 구동 방법 및 그 회로
JP2003233989A (ja) * 2002-02-07 2003-08-22 Fujitsu Ltd 半導体記憶装置及びプリチャージ方法
US6826113B2 (en) * 2003-03-27 2004-11-30 International Business Machines Corporation Synchronous dynamic random access memory device having memory command cancel function
US7480774B2 (en) * 2003-04-01 2009-01-20 International Business Machines Corporation Method for performing a command cancel function in a DRAM
KR100630714B1 (ko) * 2004-11-10 2006-10-04 삼성전자주식회사 트위스트 비트 라인들에 센싱 스트레스를 효과적으로 줄수 있는 프리차아지부를 갖는 메모리 장치, 그 웨이퍼번-인 테스트 방법 및 프리차아지부의 배치 방법
CN101593553B (zh) * 2008-05-29 2012-04-18 奇景光电股份有限公司 控制静态随机存取存储器预先充电行为的控制装置及方法
US7800959B2 (en) * 2008-09-19 2010-09-21 Freescale Semiconductor, Inc. Memory having self-timed bit line boost circuit and method therefor
US8382756B2 (en) * 2008-11-10 2013-02-26 Ellipse Technologies, Inc. External adjustment device for distraction device
US8120975B2 (en) * 2009-01-29 2012-02-21 Freescale Semiconductor, Inc. Memory having negative voltage write assist circuit and method therefor
KR102408572B1 (ko) * 2015-08-18 2022-06-13 삼성전자주식회사 반도체 메모리 장치
WO2022269492A1 (en) 2021-06-22 2022-12-29 Untether Ai Corporation Low-power static random access memory
WO2022269493A1 (en) * 2021-06-22 2022-12-29 Untether Ai Corporation Low-power static random access memory

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS592996B2 (ja) * 1976-05-24 1984-01-21 株式会社日立製作所 半導体記憶回路
JPS6057156B2 (ja) * 1978-05-24 1985-12-13 株式会社日立製作所 半導体メモリ装置
JPS5794982A (en) * 1980-12-02 1982-06-12 Nec Corp Memory circuit
JPS60179993A (ja) * 1984-02-27 1985-09-13 Toshiba Corp ランダムアクセスメモリ
JPH0770214B2 (ja) * 1986-11-14 1995-07-31 三菱電機株式会社 半導体記憶装置
JPH0766665B2 (ja) * 1988-03-31 1995-07-19 株式会社東芝 半導体記憶装置

Also Published As

Publication number Publication date
JPH02177196A (ja) 1990-07-10
US5091889A (en) 1992-02-25
JPH07118196B2 (ja) 1995-12-18
KR930000635B1 (ko) 1993-01-28

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