WO1992022070A1 - Static memories and methods of reading static memories - Google Patents

Static memories and methods of reading static memories Download PDF

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Publication number
WO1992022070A1
WO1992022070A1 PCT/US1992/004200 US9204200W WO9222070A1 WO 1992022070 A1 WO1992022070 A1 WO 1992022070A1 US 9204200 W US9204200 W US 9204200W WO 9222070 A1 WO9222070 A1 WO 9222070A1
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vcc
line
node
vss
step
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PCT/US1992/004200
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French (fr)
Inventor
Michael Anthony Ang
David J. Pilling
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Integrated Device Technology, Inc.
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    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing, power reduction
    • G11C11/417Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing, power reduction for memory cells of the field-effect type
    • G11C11/419Read-write [R-W] circuits

Abstract

The bit lines (BL, BL) of a static memory (110A) are biased dynamically at the power supply voltage VCC or at least closer to VCC than the mid-point between VCC and the reference voltage VSS. Such biasing provides a better read-disturb immunity, higher speed, and reduced power consumption. Such biasing allows to obtain fast a high differential voltage on the bit lines (BL, BL) during a read and thus allows, in some embodiments, to eliminate a pre-amplifier amplifying the bit line (BL, BL) differential voltage.

Description

STATIC MEMORIES AND METHODS OF READING STATIC MEMORIES

*t

5 CROSS-REFERENCE TO RELATED APPLICATIONS

This application is related to, and incorporates by reference, U.S. Patent Application Serial Number 07/709,923 filed May 30, 1991, entitled "Track-and- Regenerate Sense Amplifiers and Memories Using Such 10 Amplifiers" filed by the same inventors.

BACKGROUND OF THE INVENTION

This invention relates to memories, and more particularly to biasing the bit lines in a static memory. Figure 1 is a circuit diagram of one column of an

15 array of four-transistor memory cells in a static random access memory ("SRAM") . For simplicity, only two memory cells 110A and HOB are shown, and only one memory cell 110A is shown in detail. A resistor 114 and an NMOS transistor 116 are connected in series between a power

20 supply voltage VCC (5.0V, for example) and a reference voltage VSS (0.0V, for example). A resistor 120 and an NMOS transistor 122 are connected in series between VCC and VSS. Node N at the drain of transistor 116 is connected to the gate of transistor 122. Node N at the

25 drain of transistor 122 is connected to the gate of transistor 116. Nodes N and N are connected to respective complementary outputs 124, 126 of cell 110A through respective NMOS pass transistors 130, 134.

Bit lines BL and BL are biased statically near 2.5V

30 by respective transistors 136 and 138. When memory cell 110A is read, the row-address decoder ("X-decoder", not shown) drives word line WL-A high. Pass transistors 130 and 134 turn on. Bit lines BL and BL sense the voltages on the respective nodes N and Ε . The column decoder

35 ("Y-decoder", not shown) drives line 140 high (5.0V), turning on NMOS transistors 142 and 144. A high bandwidth, low gain pre-amplifier 150 amplifies the differential voltage fi.e.. the voltage difference) on bit lines BL and BL. The differential voltage is typically within ±0.3V and represents the state of memory cell 110A. The sign of the differential voltage represents the state of the stored information (either a binary 1 or a binary 0) . A sense amplifier 160 amplifies the output of pre¬ amplifier 150 providing a CMOS level signal on a memory output 170.

During successive reads of memory cells in opposing states in a given column, a memory cell may inadvertently toggle. Suppose, for example, that node N is high, and that in memory cell HOB the node corresponding to node N (not shown) is low. Suppose further that memory cell 110A is read immediately after memory cell HOB. Reading memory cell HOB leaves bit line BL at a low level. When cell HOA is read, the low level on BL may drive node N down sufficiently to toggle cell HOA. Toggling may also be caused by noise and unbalanced circuit elements. The differential voltage on the bit lines of about 0.3V opposing the internal state of the memory cell is sufficient to toggle a typical cell during a read operation. In order to improve the read-disturb immunity (that is, immunity to toggling during a read) , an equalizing transistor 180 is provided. Transistor 180 resistively shorts bit lines BL and BL during reads, thus limiting the differential voltage to a value below 0.3V. This, however, limits the differential voltage on the inputs of pre-amplifier 150. Pre-amplifier 150 becomes slower, or consumes more power, or both.

Thus there is a need for a memory with.a better read- disturb immunity, higher speed, and reduced power consumption.

SUMMARY OF THE INVENTION According to the invention, the bit lines in an SRAM are biased during a read at a voltage differing from VCC by less than the mid-point between VCC and VSS. In some embodiments, the bit lines are biased at VCC. In one example, VSS = 0.0V, VCC = 5.0V, and the bit lines are biased at 5.0V. The immunity of the memory cells to accidental toggling is increased because a higher voltage swing is required to pull the high node of the cell sufficiently low to toggle the cell. The higher bit line bias level reduces the bit line capacitance by reducing the junction capacitance associated with drain-body junctions of the pass transistors. Reduction in the bit line capacitance results in an increased memory speed and reduction of power consumption.

In some embodiments, bit lines are biased dynamically. In other words, the bit lines are charged to the bias voltage just before reading operations only. In particular, the biasing circuitry, including the equalizing transistor, is off when the pass transistors are on. Therefore, the voltage differentiation during a read is not opposed by the biasing circuitry. Hence the differential voltage of the bit lines increases with time and can reach high levels if it is allowed to proceed long enough. Thus the maximum differential voltage value can be changed simply by changing the operation frequency. The memory can hence be used in a large variety of operating conditions. Further, the pre-amplifier can be eliminated if a large differential voltage is used.

BRIEF DESCRIPTION OF THE DRAWINGS

Figure 1 is a circuit diagram of a portion of a prior art static random access memory.

Figure 2 is a circuit diagram of a portion of a memory of the present invention. Figure 3 shows timing diagrams for a reading operation of the memory of Figure 2. DESCRIPTION OF THE PREFERRED EMBODIMENTS

Improved immunity to accidental toggling, higher speed, lower power consumption and circuit simplicity are provided by dynamically biasing the bit lines at a higher voltage. In some embodiments, the bit lines are biased at

VCC.

Figure 2 illustrates a portion of a memory circuit in which the bit lines are biased at or near VCC. In order to read memory cell HOA, precharge signal PRECH is asserted low by circuitry 216 that is built from conventional logic. The precharging time period is shown as 310 in the timing diagram of Figure 3. PMOS transistors 220 and 222 at the opposite ends of bit line BL turn on, and bit line BL precharges dynamically to the bias level of VCC. Providing transistors 220 and 222 at both ends a bit line BL allows to precharge bit line BL fast and uniformly while avoiding oscillation on the bit line. Precharging occurs at the maximum rate of about 1.0V per nanosecond in one embodiment. Likewise, bit line BL precharges to VCC at the same maximum rate through PMOS transistors 224 and 226 at the opposite ends of BL.

Signal PRECH drives also the gates of PMOS transistors 230 and 232 at the opposite ends of bit lines BL and BL. Equalizing transistors 230 and 232 serve to equalize the voltages on bit lines BL and BL during precharge and to speed up precharge. All the other bit lines (not shown) are similarly precharged to VCC. Then PRECH becomes high, and transistors 220, 222, 224, 226, 230 and 232 turn off. Bit lines BL and BL are at VCC. The row address decoder ("X-decoder", not shown) drives word line WL-A to VCC, and pass transistors 130 and 134 turn on. The time period shown as 311 in Figure 3 begins. Depending on the state of memory cell HOA, the voltage at bit line BL or bit line BL goes down. In the example of Figure 3, the voltage of bit line BL goes down. The voltage at bit line BL at the end of period 311 depends on the length of period 311. The column decoder ("Y-decoder", not shown) drives line 240 low (in one embodiment to about 0.0V). Y-decode PMOS transistors 242 and 244 turn on so as to connect bit lines BL and BL to respective inputs of sense amplifier 260. In one embodiment, the differential voltage on bit lines BL and BL reaches in magnitude about 1.0V by the end of 5-nanosecond period 311. No pre¬ amplifier is needed.

The length of period 311 is controlled by word line WL. Period 311 ends when word line WL goes down. If desired, a larger differential voltage can be achieved after a longer period 311. The appropriate differential voltage is achieved fast because transistors 220, 222, 224, 226, 230 and 232 are off and so they do not oppose the voltage differentiation. Thus the maximum value of the differential voltage can be changed simply by changing the operation frequency. The memory, therefore, can be used in a large variety of operating conditions. A larger maximum value of the differential voltage is desired, for example, if the memory is operated in a noisier conditions. The larger maximum value is achieved simply by lowering the memory frequency. No memory redesign, as would be required in prior art, is needed.

Suitable embodiments of sense amplifier 260 are disclosed in U.S. Patent Application entitled "Track-and- Regenerate Sense Amplifiers and Memories Using Such

Amplifiers" filed by the same inventors and on the same date as the present application and having Attorney Docket No. M-1616.

The read-disturb immunity is improved when the bias level of the bit lines is increased. For example, in some memories operated at VCC = 5.0V, VSS = 0.0V and a bias level of 5.0V, a differential voltage of 2.5V is necessary to toggle the memory cell. By contrast, in a similar memory cell operated at a bit line bias level of 2.5V, a differential voltage of 0.3V is sufficient to toggle the cell.

The read-disturb immunity improvement is illustrated by the following examples. Suppose VCC = 5.0V; node N is high, near 5.0V; complementary node N is low, near 0.0V; and bit lines BL and BL are at the bias level of 5.0V. During a read, the current through transistor 134 is insufficient to toggle memory cell HOA, because transistor 134 is smaller than transistor 122 (over three times smaller in some embodiments) , and transistor 134 has a smaller current handling capability hence acting as a current limiter. In order to toggle memory cell HOA, the voltage on BL must drop by about 2.5V in some embodiments, that is to about 2.5V, so as to drive node N sufficiently low, decreasing the transconductance of transistor 122. If the bias level were lower, a smaller voltage drop on BL could toggle cell HOA. Consider further the example of a write on cell HOB immediately followed by a read on cell HOA. Suppose that, in memory cell HOA, node N is low and node N is high. Suppose that, during the write on cell HOB, bit line BL is 5.0V, and bit line BL is 0.0V. If, during reads, the bit line bias level is 2.5V, node N may be pulled down excessively by the read operation due to a residual differential voltage on the bit lines from the preceding write, and cell HOA may toggle. The higher the bias level, the less likely the cell is to toggle during the read.

Write operations occur as in prior art with transistors 220, 222, 224, 226, 230 and 232 off.

The higher bit line bias level and dynamic precharge of bit lines permit to obtain a large differential voltage fast during a read and to save power. Generally, the differential voltage is due more to the conducting transistor 116 or 122 pulling one of the bit lines down rather than to one of the resistors 114 and 120 pulling the other bit line up. This is because resistors 114 and 120 are large. The higher the bias level, the larger the voltage drop between the bit lines and the sources of transistors 116 and 122, and the faster one of the bit lines discharges through the conducting transistor 116 or 122. Further, since transistors 220, 222, 224, 226, 230 and 232 are off, they do not oppose the voltage differentiation. Thus, while a high differential voltage is obtained fast, the power consumption is low. The differential voltage can reach 5.0V if the voltage differentiation occurs long enough. If the differential voltage is allowed to become sufficiently high, a pre¬ amplifier is unnecessary, and further amplifier 260 can be made faster, or to consume less power, or both. The memory circuit becomes smaller, faster, simpler, and it consumes less power.

In some embodiments, the use of PMOS transistors as Y-decode transistors 242 and 244 results in a higher gain than the use of Y-decode NMOS transistors 142 and 144 in Figure 1 because the absolute value of the gate-to-source voltage VGS of transistors 242 and 244 is higher during read operations. Suppose, for example, that VCC = 5.0V and VSS = 0.0V. In Figure 2, line 240 is at 0.0V during a read. When bit line BL is 5.0V, VGS of transistor 242 is -5.0V. By contrast, in Figure 1, line 140 is 5.0V, and when bit line BL is at 2.5V, VGS of transistor 142 is 2.5V. Assuming that transistors 142 and 242 have the same size, that the threshold voltage of transistor 142 is 1.0V, the threshold voltage of transistor 242 is -1.0V, the drain-to-source voltages are 0.2V and the current carrier mobility of transistor 242 is one half that of transistor 142, it can be shown that the drain current of transistor 242 is about 1.4 times greater than the drain current of transistor 142. The increased current gain allows to make sense amplifier 260 faster, or reduce its power consumption, or both.

The higher bit line bias level reduces the bit line capacitance. A major component of the bit line capacitance is the junction capacitance associated with drain-body junctions of the pass transistors such as transistors 130 and 134. Respective drains 130a and 134a of transistors 130 and 134 are at the voltages of the respective bit lines BL, BL. The bodies of the pass transistors are at some low voltage (0.0V in some embodiments) , so the drain-body junctions are reverse- biased. The higher the bit line voltage, the larger the depletion region at the drain-body junction, and the smaller the capacitance. Reduction in the capacitance results in an increased memory speed and a reduction of dynamic power consumption. The power consumption is further reduced by precharging bit lines BL and BL dynamically just before driving word line WL-A high rather than statically. Further, transistors 230 and 232 are off during write operations and so they do not oppose the write circuitry (not shown) . As a result, write operations are faster and consume less power.

In one embodiment, the transistor sizes are as follows. Transistors 220, 222, 224, 226, 230 and 232 each have the width/length dimension of 10 μm/0.9 μm. Transistors 116 and 122 each have the width/length dimension of 6 μm/0.9 μm. Transistors 130 and 134 each have the width/length dimension of 1.8 μm/1.1 wα. Resistors 114 and 120 are each between 109 and 1012 ohm. In that embodiment, voltage VCC is 5.0V, and VSS is 0.0V. While the invention has been described with respect to the embodiments set forth above, other embodiments and variations not described herein are within the scope of the invention. For example, the invention is not limited by any specific values of VSS, VCC or the bit line bias voltage. In some embodiments, the bias voltage is VCC, or a voltage greater than VSS + 0.5 x (VCC - VSS), or at least VSS + 0.6 X (VCC - VSS), or at least VSS + 0.8 X (VCC - VSS) , or at least VSS + 0.9 X (VCC - VSS) . In some embodiments, VCC is below VSS. The bias voltage is closer to VCC than the midpoint between VCC and VSS. In other words, the bias voltage differs from VCC by less than 0.5 X IVCC - VSSI (one half of the absolute value of the difference between VCC and VSS) . In some embodiments, the bias voltage is VCC, or it differs from VCC by less than 0.4 X IVCC - VSS|. In some embodiments, the bias voltage differs from VCC by less than 0.3 X |VCC - VSS| . In some embodiments, the bias voltage differs from VCC by less than 0.1 X |VCC - VSS| . Other bias voltage ranges are possible.

Further, the invention is not limited to the four- transistor memory cell. For example, the higher bit line bias levels are advantageously used in six-transistor memory cells. Six-transistor cells are described generally in C. A. Holt, Electronic Circuits (John Wiley & Sons, 1978), pages 293, 294 hereby incorporated by reference herein. Other embodiments and variations not described herein are within the scope of the invention, as defined by the following claims.

Claims

CLAIMSWhat is claimed is:
1. A method of reading a static memory cell comprising the steps of: connecting said memory cell to a power supply voltage VCC and to a reference voltage VSS; charging a first line to a predetermined voltage, said predetermined voltage differing from VCC by less than 0.5 X |VCC - VSS|; electrically connecting said first line to a first node of said memory cell, the voltage on said first node determining the state of said memory cell; and sensing the state of said first line.
2. The method of Claim 1 wherein said charging step comprises the steps of: electrically connecting said first line to a source of power; charging said first line from said source of power to said predetermined voltage; and electrically disconnecting the charged irst line from said source of power before said sensing step.
3. The method of Claim 1 wherein said predetermined voltage differs from VCC by less than 0.4 X [VCC - VSS|.
4. The method of Claim l wherein said predetermined voltage differs from VCC by less than 0.3 X |VCC - VSS| .
5. The method of Claim 1 wherein said predetermined voltage differs from VCC by less than 0.2 X |VCC - VSS| .
6. The method of Claim 1 wherein said predetermined voltage differs from VCC by less than 0.1 X |VCC - VSSl.
7. The method of Claim 1 wherein: VCC is greater than VSS; and said predetermined voltage is at most VCC.
8. The method of Claim 7 wherein: VCC is 5.0V;
VSS is 0.0V; and said predetermined voltage is at least 3.5V and at most 5.0V.
9. The method of Claim 8 wherein said predetermined voltage is about 5.0V.
10. The method of Claim 1 further comprising the steps of: charging a second line to said predetermined voltage; and electrically connecting said second line to a second node of said memory cell, the state of said second node being complementary to the state of said first node; wherein said sensing step comprises the step of sensing the differential voltage on said first and second lines.
11. The method of Claim 10 wherein: said step of charging a first line comprises the step of dynamically precharging said first line to said predetermined voltage before said step of electrically connecting said first line to a first node; and said step of charging a second line comprises the step of dynamically precharging said second line to said predetermined voltage before said step of electrically connecting said second line to a second node.
12. The method of Claim 11 further comprising the step of electrically connecting said first and second lines to each other during said step of precharging said first line and said step of precharging said second line.
13. The method of Claim 10 wherein said memory cell comprises: a first resistor having a first terminal connected to said first node and having a second terminal; a first MOS transistor having a current carrying electrode Dl connected to said first node, having a current carrying electrode SI, and having a gate electrode Gl connected to said second node; a second resistor having a first terminal connected to said second node and having a second terminal; a second MOS transistor having a current carrying electrode D2 connected to said second node, having a current carrying electrode S2, and having a gate G2 connected to said first node; and wherein said step of connecting said memory cell comprises the steps of: connecting the second terminals of said first and second resistors to said power supply voltage VCC; and connecting said electrodes Si and S2 to said reference voltage VSS.
14. A method of reading a static memory that comprises an array of memory cells, wherein said memory is powered by a power supply voltage VCC and said memory is connected to a reference voltage VSS, said method comprising the steps of: selecting a memory cell in said array; charging two bit lines BL and BL to a predetermined voltage that differs from VCC by less than 0.5 X IVCC - VSSI ; electrically connecting said bit line BL to a first node of the selected memory cell, a state of said first node defining the state of the selected memory cell; electrically connecting said bit line BL to a second node of the selected memory cell, said second node being complementary to said first node; and sensing the differential voltage on said bit lines BL and BL.
15. The method of Claim 14 wherein said charging step comprises the steps of: turning on a precharge circuitry; precharging said bit lines BL and BL to said predetermined voltage by said precharge circuitry; and turning off said precharge circuitry when said bit lines BL and BL have been precharged to said predetermined voltage.
16. The method of Claim 15 wherein: said precharge circuitry comprises an equalizing transistor interconnecting said bit lines BL and BL; said step of turning on a precharge circuitry comprises the step of turning on said equalizing transistor; and said step of turning off said precharge circuitry comprises the step of turning off said equalizing transistor.
17. The method of Claim 14, wherein: VSS is below VCC; and said predetermined voltage is at least VSS + 0.7 X (VCC - VSS) and at most VCC.
18. The method of Claim 17 wherein: VSS is 0.0V; and said predetermined voltage is at least 0.8 X VCC.
19. A static memory comprising: a memory cell having two states; means for coupling said cell to a power supply voltage VCC; means for coupling said cell to a reference voltage VSS; a first line; means for charging said first line to a predetermined voltage closer to VCC than 0.5 X |VCC - VSSI ; means for electrically connecting the charged first line to said memory cell; and means for sensing the state of said first line.
20. The memory of Claim 19 wherein said predetermined voltage differs from VCC by at most 0.7 X
Figure imgf000016_0001
21. The memory of Claim 19 further comprising: a second line; means for charging said second line to said predetermined voltage; and means for electrically connecting the charged second line to said memory cell; wherein said sensing means comprises an amplifier for amplifying a differential voltage on said first and second lines.
22. The memory of Claim 21 wherein: VCC is above VSS; and said sensing means further comprises: a first PMOS transistor having one current carrying electrode connected to said first line and another current carrying electrode connected to a first input of said amplifier; a second PMOS transistor having one current carrying electrode connected to said second line and another current carrying electrode connected to a second input of said amplifier; and means for connecting the gates of said first and second PMOS transistors to said reference voltage VSS.
23. The memory of Claim 19 wherein said memory cell e of an array of memory cells in said memory.
PCT/US1992/004200 1991-05-30 1992-05-28 Static memories and methods of reading static memories WO1992022070A1 (en)

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Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4975879A (en) * 1989-07-17 1990-12-04 Advanced Micro Devices, Inc. Biasing scheme for FIFO memories
US5043945A (en) * 1989-09-05 1991-08-27 Motorola, Inc. Memory with improved bit line and write data line equalization
US5047985A (en) * 1988-02-19 1991-09-10 Sony Corporation Static random access memory device having a high speed read-out and precharging arrangement
US5047984A (en) * 1989-05-09 1991-09-10 Nec Corporation Internal synchronous static RAM
US5058667A (en) * 1990-11-20 1991-10-22 Ramsower Vernon O Reciprocating water well pump
US5075891A (en) * 1987-11-27 1991-12-24 Sony Corporation Memory with a variable impedance bit line load circuit
US5091889A (en) * 1988-12-28 1992-02-25 Kabushiki Kaisha Toshiba Semiconductor memory having an operation margin against a write recovery time

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5075891A (en) * 1987-11-27 1991-12-24 Sony Corporation Memory with a variable impedance bit line load circuit
US5047985A (en) * 1988-02-19 1991-09-10 Sony Corporation Static random access memory device having a high speed read-out and precharging arrangement
US5091889A (en) * 1988-12-28 1992-02-25 Kabushiki Kaisha Toshiba Semiconductor memory having an operation margin against a write recovery time
US5047984A (en) * 1989-05-09 1991-09-10 Nec Corporation Internal synchronous static RAM
US4975879A (en) * 1989-07-17 1990-12-04 Advanced Micro Devices, Inc. Biasing scheme for FIFO memories
US5043945A (en) * 1989-09-05 1991-08-27 Motorola, Inc. Memory with improved bit line and write data line equalization
US5058667A (en) * 1990-11-20 1991-10-22 Ramsower Vernon O Reciprocating water well pump

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