KR890007387A - 반도체 장치의 제조공정 및 전도성 레벨간의 상호 접속방법 - Google Patents

반도체 장치의 제조공정 및 전도성 레벨간의 상호 접속방법 Download PDF

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KR890007387A
KR890007387A KR1019880013328A KR880013328A KR890007387A KR 890007387 A KR890007387 A KR 890007387A KR 1019880013328 A KR1019880013328 A KR 1019880013328A KR 880013328 A KR880013328 A KR 880013328A KR 890007387 A KR890007387 A KR 890007387A
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contact area
window
supplying
conductivity level
gap
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KR1019880013328A
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KR0134783B1 (ko
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프란시스쿠스 마리에 구트겐 빌헬무스
오신스키 가지미어즈
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이반 밀러 레르너
엔.브이.필립스 글로아이람펜파브리켄
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76804—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics by forming tapered via holes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02282—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process liquid deposition, e.g. spin-coating, sol-gel techniques, spray coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/314—Inorganic layers
    • H01L21/316—Inorganic layers composed of oxides or glassy oxides or oxide based glass

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Plasma & Fusion (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

내용 없음

Description

반도체 장치의 제조공정 및 전도성 레벨간의 상호 접속방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본 발명을 구체화시키는 방법을 사용하여 형성된 전도성 레벨간의 상호 접속을 도시하는 반도체 장치 일부의 상부 평면도.
제2 내지 6도는 본 발명을 구체화시키는 방법에 있어서 연속적인 여러 스텝을 나타내는 단면도.

Claims (11)

  1. 제1전도성 레벨이 접촉 영역을 가지도록 서브 스트레이트 바디의 표면상에 제1전도성 레벨을 공급하고, 제1전도성 레벨을 커버하도록 바디의 표면상에 비활성 물질을 공급하며, 윈도우의 주위와 접촉 영역과 접한 제1전도성 레벨의 측벽부 사이에 갭이 존재하도록 접촉 영역보다 큰 윈도우를 비활성 물질에서 개방시킴으로써 접촉 영역을 노출시키며, 상기 윈도우내에서 접촉 영역과 접촉하도록 비활성 물질의 최상부상에 제2전도성 레벨 부분을 공급하는 방법에 있어서, 윈도우를 개방시킨 후에 제2전도성 레벨을 공급하기 전에 윈도우의 주위와 접촉 영역간의 표면을 매끄럽게 하기 위해 갭에 물질을 공급하는 것을 특징으로 하는 전도성 레벨간의 상호 접속 방법.
  2. 제1전도성 레벨이 접촉 영역을 가지도록 서브 스트레이트 바디의 표면상에 제1전도성 레벨을 공급하고, 제1전도성 레벨을 커버하도록 바디의 표면상에 비활성 물질을 공급하며, 윈도우의 주위와 접촉 영역과 접한 제1전도성 레벨의 측벽부 사이에 갭이 존재하도록 접촉 영역보다 큰 윈도우를 비활성 물질에서 개방시킴으로써 접촉 영역을 노출시키며, 상기 윈도우내에서 접촉 영역과 접촉하도록 비활성 물질의 최상부상에 제2전도성 레벨 부분을 공급하는 방법에 있어서, 윈도우를 개방시킨 후에 제2전도성 레벨을 공급하기 전에 윈도우의 주위와 접촉 영역간의 표면을 매끄럽게 하기 위해 갭에 물질을 공급하는 것을 특징으로 하는 반도체장치 공정방법.
  3. 제1 또는 제2항에 있어서, 접촉 영역이 전도성 스트립상에 있고 상기 스트립의 연장된 측벽부에 의해 바운드되도록 하나 이상의 전도성 스트립으로서 제1전도성 레벨을 공급하고, 윈도우가 횡으로 확장되어 전도성 스트립보다 넓어지고, 전도성 스트립의 각각의 연장된 가장자리와 윈도우의 주위 사이에 갭이 존재하도록 윈도우를 개방시키며, 제1전도성 레벨의 전도성 스트립을 넘어 횡으로 확장되는 하나 이상의 전도성 스트립으로서 제2전도성 레벨을 공급하는 것을 특징으로 하는 전도성 레벨간의 상호 접속방법.
  4. 제1,2 또는 제3항에 있어서, 다른 절연물질로 표면을 커버하고, 접촉 영역을 노출시키도록 상기 절연물질로 에칭시킴으로써 갭에 물질을 공급하는 과정을 포함하는 것을 특징으로 하는 전도성 레벨간의 상호 접속방법.
  5. 제4항에 있어서, 표면으로의 유동성 및 응고성을 가지는 매개물을 인가함으로써 갭에 물질을 공급하는 과정을 포함하는 것을 특징으로 하는 전도성 레벨간의 상호 접속방법.
  6. 제5항에 있어서, 유동성 및 응고성을 가지는 매개물로서 용매속에 분산된 절연물질을 사용하며, 상기 용매를 증발시켜 상기 매개물을 응고시키는 과정을 포함하는 것을 특징으로 하는 전도성 레벨간의 상호 접속방법.
  7. 제6항에 있어서, 유동성 및 응고성을 가지는 매개물로서 스핀-온-글래스를 사용하는 것을 특징으로 하는 전도성 레벨간의 상호 접속방법.
  8. 상술한 어느 한 항에 있어서, 제1전도성 레벨상에서 에칭 중지층을 공급하는 것을 특징으로 하는 전도성 레벨간의 상호 접속방법.
  9. 제7항에 있어서, 에칭 중지층으로서 텅스텐-티타늄 합금을 사용하는 것을 특징으로 하는 전도성 레벨간의 상호 접속방법.
  10. 첨부된 도면을 참조로 설명된 바와같은 반도체 장치의 공정방법.
  11. 본 출원서에서 설명된 새로운 특성 또는 특성들의 조합.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019880013328A 1987-10-16 1988-10-13 반도체 장치의 제조 방법 및 도전 레벨층간의 상호 접속 방법 KR0134783B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
GB8724319A GB2211348A (en) 1987-10-16 1987-10-16 A method of forming an interconnection between conductive levels
GB8724319 1987-10-16

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KR890007387A true KR890007387A (ko) 1989-06-19
KR0134783B1 KR0134783B1 (ko) 1998-04-20

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US (1) US4965226A (ko)
EP (1) EP0312154B1 (ko)
JP (1) JP2578178B2 (ko)
KR (1) KR0134783B1 (ko)
DE (1) DE3886882T2 (ko)
GB (1) GB2211348A (ko)

Families Citing this family (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0416165B1 (de) * 1989-09-08 1994-12-14 Siemens Aktiengesellschaft Verfahren zur globalen Planarisierung von Oberflächen für integrierte Halbleiterschaltungen
US5166771A (en) * 1990-01-12 1992-11-24 Paradigm Technology, Inc. Self-aligning contact and interconnect structure
US5483104A (en) * 1990-01-12 1996-01-09 Paradigm Technology, Inc. Self-aligning contact and interconnect structure
JP2518435B2 (ja) * 1990-01-29 1996-07-24 ヤマハ株式会社 多層配線形成法
JPH0482263A (ja) * 1990-07-25 1992-03-16 Sharp Corp 半導体記憶装置
JP2640174B2 (ja) * 1990-10-30 1997-08-13 三菱電機株式会社 半導体装置およびその製造方法
JPH0645327A (ja) * 1991-01-09 1994-02-18 Nec Corp 半導体装置の製造方法
US5086017A (en) * 1991-03-21 1992-02-04 Industrial Technology Research Institute Self aligned silicide process for gate/runner without extra masking
JP2921773B2 (ja) * 1991-04-05 1999-07-19 三菱電機株式会社 半導体装置の配線接続構造およびその製造方法
CA2056456C (en) * 1991-08-14 2001-05-08 Luc Ouellet High performance passivation for semiconductor devices
US5245213A (en) * 1991-10-10 1993-09-14 Sgs-Thomson Microelectronics, Inc. Planarized semiconductor product
JP2771057B2 (ja) * 1991-10-21 1998-07-02 シャープ株式会社 半導体装置の製造方法
KR100220297B1 (ko) * 1991-12-02 1999-09-15 김영환 다층금속 배선구조의 콘택제조방법
JP2773530B2 (ja) * 1992-04-15 1998-07-09 日本電気株式会社 半導体装置の製造方法
DE4239075C1 (de) * 1992-11-20 1994-04-07 Itt Ind Gmbh Deutsche Verfahren zur globalen Planarisierung von Oberflächen integrierter Halbleiterschaltungen
JP2705513B2 (ja) * 1993-06-08 1998-01-28 日本電気株式会社 半導体集積回路装置の製造方法
US5438022A (en) 1993-12-14 1995-08-01 At&T Global Information Solutions Company Method for using low dielectric constant material in integrated circuit fabrication
US5451543A (en) * 1994-04-25 1995-09-19 Motorola, Inc. Straight sidewall profile contact opening to underlying interconnect and method for making the same
US5482897A (en) * 1994-07-19 1996-01-09 Lsi Logic Corporation Integrated circuit with on-chip ground plane
US5728453A (en) * 1995-12-28 1998-03-17 Advanced Micro Devices, Inc. Method of fabricating topside structure of a semiconductor device
US5663108A (en) * 1996-06-13 1997-09-02 Taiwan Semiconductor Manufacturing Company, Ltd. Optimized metal pillar via process
EP0849787A1 (de) * 1996-12-18 1998-06-24 Siemens Aktiengesellschaft Verfahren zur Herstellung einer intergrierten Schaltungsanordnung
US5863707A (en) * 1997-02-11 1999-01-26 Advanced Micro Devices, Inc. Method for producing ultra-fine interconnection features
US6323046B1 (en) * 1998-08-25 2001-11-27 Micron Technology, Inc. Method and apparatus for endpointing a chemical-mechanical planarization process
DE10145724A1 (de) 2001-09-17 2003-04-10 Infineon Technologies Ag Verfahren zum Herstellen einer Halbleiterstruktur unter Verwendung einer Schutzschicht und Halbleiterstruktur
JP2008031872A (ja) * 2006-07-26 2008-02-14 Yamaha Marine Co Ltd メタルガスケットによるシール構造

Family Cites Families (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1308496A (en) * 1970-09-18 1973-02-21 Plessey Co Ltd Semiconductor devices
US4185294A (en) * 1975-12-10 1980-01-22 Tokyo Shibaura Electric Co., Ltd. Semiconductor device and a method for manufacturing the same
JPS5836497B2 (ja) * 1975-12-23 1983-08-09 富士通株式会社 ハンドウタイソウチノセイゾウホウホウ
US4172004A (en) * 1977-10-20 1979-10-23 International Business Machines Corporation Method for forming dense dry etched multi-level metallurgy with non-overlapped vias
JPS56137656A (en) * 1980-03-31 1981-10-27 Chiyou Lsi Gijutsu Kenkyu Kumiai Multilayer wiring structure and its manufacture
JPS57170550A (en) * 1981-04-15 1982-10-20 Toshiba Corp Manufacture of semiconductor device
JPS57208160A (en) * 1981-06-18 1982-12-21 Fujitsu Ltd Semiconductor device
JPS582031A (ja) * 1981-06-29 1983-01-07 Toshiba Corp 半導体装置の製造方法
JPS5833865A (ja) * 1981-08-24 1983-02-28 Toshiba Corp 半導体記憶装置及びその製造方法
JPS58216445A (ja) * 1982-06-10 1983-12-16 Nec Corp 半導体装置およびその製造方法
JPS59112239A (ja) * 1982-11-18 1984-06-28 Kyowa Dengiyou:Kk 荷重変換器
JPS60245254A (ja) * 1984-05-21 1985-12-05 Hitachi Ltd 層間絶縁膜の形成方法
DE3421127A1 (de) * 1984-06-07 1985-12-12 Telefunken electronic GmbH, 7100 Heilbronn Verfahren zum herstellen einer halbleiteranordnung
US4619839A (en) * 1984-12-12 1986-10-28 Fairchild Camera & Instrument Corp. Method of forming a dielectric layer on a semiconductor device
JPS61164242A (ja) * 1985-01-17 1986-07-24 Seiko Epson Corp 半導体装置の製造方法
JPS61174650A (ja) * 1985-01-28 1986-08-06 Mitsubishi Electric Corp 半導体装置
FR2588417B1 (fr) * 1985-10-03 1988-07-29 Bull Sa Procede de formation d'un reseau metallique multicouche d'interconnexion des composants d'un circuit integre de haute densite et circuit integre en resultant
US4719125A (en) * 1985-10-11 1988-01-12 Allied Corporation Cyclosilazane polymers as dielectric films in integrated circuit fabrication technology
DE8613488U1 (de) * 1986-05-17 1987-10-22 Philips Patentverwaltung Gmbh, 2000 Hamburg Durchführungsanschluß für einen Kombibaustein
US4824521A (en) * 1987-04-01 1989-04-25 Fairchild Semiconductor Corporation Planarization of metal pillars on uneven substrates

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Publication number Publication date
GB8724319D0 (en) 1987-11-18
US4965226A (en) 1990-10-23
EP0312154A1 (en) 1989-04-19
JP2578178B2 (ja) 1997-02-05
DE3886882D1 (de) 1994-02-17
DE3886882T2 (de) 1994-06-30
JPH01129445A (ja) 1989-05-22
GB2211348A (en) 1989-06-28
KR0134783B1 (ko) 1998-04-20
EP0312154B1 (en) 1994-01-05

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