DE3886882D1 - Methode zur Ausbildung von Verbindungen zwischen leitenden Ebenen. - Google Patents
Methode zur Ausbildung von Verbindungen zwischen leitenden Ebenen.Info
- Publication number
- DE3886882D1 DE3886882D1 DE88202184T DE3886882T DE3886882D1 DE 3886882 D1 DE3886882 D1 DE 3886882D1 DE 88202184 T DE88202184 T DE 88202184T DE 3886882 T DE3886882 T DE 3886882T DE 3886882 D1 DE3886882 D1 DE 3886882D1
- Authority
- DE
- Germany
- Prior art keywords
- forming connections
- managerial
- levels
- managerial levels
- connections
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76804—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics by forming tapered via holes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
- H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02282—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process liquid deposition, e.g. spin-coating, sol-gel techniques, spray coating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/314—Inorganic layers
- H01L21/316—Inorganic layers composed of oxides or glassy oxides or oxide based glass
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Plasma & Fusion (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
GB8724319A GB2211348A (en) | 1987-10-16 | 1987-10-16 | A method of forming an interconnection between conductive levels |
Publications (2)
Publication Number | Publication Date |
---|---|
DE3886882D1 true DE3886882D1 (de) | 1994-02-17 |
DE3886882T2 DE3886882T2 (de) | 1994-06-30 |
Family
ID=10625442
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE3886882T Expired - Fee Related DE3886882T2 (de) | 1987-10-16 | 1988-10-03 | Methode zur Ausbildung von Verbindungen zwischen leitenden Ebenen. |
Country Status (6)
Country | Link |
---|---|
US (1) | US4965226A (de) |
EP (1) | EP0312154B1 (de) |
JP (1) | JP2578178B2 (de) |
KR (1) | KR0134783B1 (de) |
DE (1) | DE3886882T2 (de) |
GB (1) | GB2211348A (de) |
Families Citing this family (26)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE58908781D1 (de) * | 1989-09-08 | 1995-01-26 | Siemens Ag | Verfahren zur globalen Planarisierung von Oberflächen für integrierte Halbleiterschaltungen. |
US5166771A (en) * | 1990-01-12 | 1992-11-24 | Paradigm Technology, Inc. | Self-aligning contact and interconnect structure |
US5483104A (en) * | 1990-01-12 | 1996-01-09 | Paradigm Technology, Inc. | Self-aligning contact and interconnect structure |
JP2518435B2 (ja) * | 1990-01-29 | 1996-07-24 | ヤマハ株式会社 | 多層配線形成法 |
JPH0482263A (ja) * | 1990-07-25 | 1992-03-16 | Sharp Corp | 半導体記憶装置 |
JP2640174B2 (ja) * | 1990-10-30 | 1997-08-13 | 三菱電機株式会社 | 半導体装置およびその製造方法 |
JPH0645327A (ja) * | 1991-01-09 | 1994-02-18 | Nec Corp | 半導体装置の製造方法 |
US5086017A (en) * | 1991-03-21 | 1992-02-04 | Industrial Technology Research Institute | Self aligned silicide process for gate/runner without extra masking |
JP2921773B2 (ja) * | 1991-04-05 | 1999-07-19 | 三菱電機株式会社 | 半導体装置の配線接続構造およびその製造方法 |
CA2056456C (en) * | 1991-08-14 | 2001-05-08 | Luc Ouellet | High performance passivation for semiconductor devices |
US5245213A (en) * | 1991-10-10 | 1993-09-14 | Sgs-Thomson Microelectronics, Inc. | Planarized semiconductor product |
JP2771057B2 (ja) * | 1991-10-21 | 1998-07-02 | シャープ株式会社 | 半導体装置の製造方法 |
KR100220297B1 (ko) * | 1991-12-02 | 1999-09-15 | 김영환 | 다층금속 배선구조의 콘택제조방법 |
JP2773530B2 (ja) * | 1992-04-15 | 1998-07-09 | 日本電気株式会社 | 半導体装置の製造方法 |
DE4239075C1 (de) * | 1992-11-20 | 1994-04-07 | Itt Ind Gmbh Deutsche | Verfahren zur globalen Planarisierung von Oberflächen integrierter Halbleiterschaltungen |
JP2705513B2 (ja) * | 1993-06-08 | 1998-01-28 | 日本電気株式会社 | 半導体集積回路装置の製造方法 |
US5438022A (en) | 1993-12-14 | 1995-08-01 | At&T Global Information Solutions Company | Method for using low dielectric constant material in integrated circuit fabrication |
US5451543A (en) * | 1994-04-25 | 1995-09-19 | Motorola, Inc. | Straight sidewall profile contact opening to underlying interconnect and method for making the same |
US5482897A (en) * | 1994-07-19 | 1996-01-09 | Lsi Logic Corporation | Integrated circuit with on-chip ground plane |
US5728453A (en) * | 1995-12-28 | 1998-03-17 | Advanced Micro Devices, Inc. | Method of fabricating topside structure of a semiconductor device |
US5663108A (en) * | 1996-06-13 | 1997-09-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Optimized metal pillar via process |
TW347576B (en) * | 1996-12-18 | 1998-12-11 | Siemens Ag | Method to produce an integrated circuit arrangement |
US5863707A (en) * | 1997-02-11 | 1999-01-26 | Advanced Micro Devices, Inc. | Method for producing ultra-fine interconnection features |
US6323046B1 (en) * | 1998-08-25 | 2001-11-27 | Micron Technology, Inc. | Method and apparatus for endpointing a chemical-mechanical planarization process |
DE10145724A1 (de) * | 2001-09-17 | 2003-04-10 | Infineon Technologies Ag | Verfahren zum Herstellen einer Halbleiterstruktur unter Verwendung einer Schutzschicht und Halbleiterstruktur |
JP2008031872A (ja) * | 2006-07-26 | 2008-02-14 | Yamaha Marine Co Ltd | メタルガスケットによるシール構造 |
Family Cites Families (20)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB1308496A (en) * | 1970-09-18 | 1973-02-21 | Plessey Co Ltd | Semiconductor devices |
US4185294A (en) * | 1975-12-10 | 1980-01-22 | Tokyo Shibaura Electric Co., Ltd. | Semiconductor device and a method for manufacturing the same |
JPS5836497B2 (ja) * | 1975-12-23 | 1983-08-09 | 富士通株式会社 | ハンドウタイソウチノセイゾウホウホウ |
US4172004A (en) * | 1977-10-20 | 1979-10-23 | International Business Machines Corporation | Method for forming dense dry etched multi-level metallurgy with non-overlapped vias |
JPS56137656A (en) * | 1980-03-31 | 1981-10-27 | Chiyou Lsi Gijutsu Kenkyu Kumiai | Multilayer wiring structure and its manufacture |
JPS57170550A (en) * | 1981-04-15 | 1982-10-20 | Toshiba Corp | Manufacture of semiconductor device |
JPS57208160A (en) * | 1981-06-18 | 1982-12-21 | Fujitsu Ltd | Semiconductor device |
JPS582031A (ja) * | 1981-06-29 | 1983-01-07 | Toshiba Corp | 半導体装置の製造方法 |
JPS5833865A (ja) * | 1981-08-24 | 1983-02-28 | Toshiba Corp | 半導体記憶装置及びその製造方法 |
JPS58216445A (ja) * | 1982-06-10 | 1983-12-16 | Nec Corp | 半導体装置およびその製造方法 |
JPS59112239A (ja) * | 1982-11-18 | 1984-06-28 | Kyowa Dengiyou:Kk | 荷重変換器 |
JPS60245254A (ja) * | 1984-05-21 | 1985-12-05 | Hitachi Ltd | 層間絶縁膜の形成方法 |
DE3421127A1 (de) * | 1984-06-07 | 1985-12-12 | Telefunken electronic GmbH, 7100 Heilbronn | Verfahren zum herstellen einer halbleiteranordnung |
US4619839A (en) * | 1984-12-12 | 1986-10-28 | Fairchild Camera & Instrument Corp. | Method of forming a dielectric layer on a semiconductor device |
JPS61164242A (ja) * | 1985-01-17 | 1986-07-24 | Seiko Epson Corp | 半導体装置の製造方法 |
JPS61174650A (ja) * | 1985-01-28 | 1986-08-06 | Mitsubishi Electric Corp | 半導体装置 |
FR2588417B1 (fr) * | 1985-10-03 | 1988-07-29 | Bull Sa | Procede de formation d'un reseau metallique multicouche d'interconnexion des composants d'un circuit integre de haute densite et circuit integre en resultant |
US4719125A (en) * | 1985-10-11 | 1988-01-12 | Allied Corporation | Cyclosilazane polymers as dielectric films in integrated circuit fabrication technology |
DE8613511U1 (de) * | 1986-05-17 | 1987-10-15 | Philips Patentverwaltung Gmbh, 2000 Hamburg, De | |
US4824521A (en) * | 1987-04-01 | 1989-04-25 | Fairchild Semiconductor Corporation | Planarization of metal pillars on uneven substrates |
-
1987
- 1987-10-16 GB GB8724319A patent/GB2211348A/en not_active Withdrawn
-
1988
- 1988-10-03 EP EP88202184A patent/EP0312154B1/de not_active Expired - Lifetime
- 1988-10-03 DE DE3886882T patent/DE3886882T2/de not_active Expired - Fee Related
- 1988-10-13 JP JP63256045A patent/JP2578178B2/ja not_active Expired - Fee Related
- 1988-10-13 KR KR1019880013328A patent/KR0134783B1/ko not_active IP Right Cessation
-
1990
- 1990-01-16 US US07/465,560 patent/US4965226A/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
US4965226A (en) | 1990-10-23 |
GB8724319D0 (en) | 1987-11-18 |
JPH01129445A (ja) | 1989-05-22 |
GB2211348A (en) | 1989-06-28 |
EP0312154A1 (de) | 1989-04-19 |
KR890007387A (ko) | 1989-06-19 |
KR0134783B1 (ko) | 1998-04-20 |
DE3886882T2 (de) | 1994-06-30 |
EP0312154B1 (de) | 1994-01-05 |
JP2578178B2 (ja) | 1997-02-05 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition | ||
8327 | Change in the person/name/address of the patent owner |
Owner name: PHILIPS ELECTRONICS N.V., EINDHOVEN, NL |
|
8327 | Change in the person/name/address of the patent owner |
Owner name: KONINKLIJKE PHILIPS ELECTRONICS N.V., EINDHOVEN, N |
|
8320 | Willingness to grant licences declared (paragraph 23) | ||
8339 | Ceased/non-payment of the annual fee |