KR870001665A - Rom 제조방법 - Google Patents

Rom 제조방법 Download PDF

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Publication number
KR870001665A
KR870001665A KR1019860006213A KR860006213A KR870001665A KR 870001665 A KR870001665 A KR 870001665A KR 1019860006213 A KR1019860006213 A KR 1019860006213A KR 860006213 A KR860006213 A KR 860006213A KR 870001665 A KR870001665 A KR 870001665A
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KR
South Korea
Prior art keywords
gate
transistor
drain
substrate
source
Prior art date
Application number
KR1019860006213A
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English (en)
Other versions
KR930008007B1 (ko
Inventor
오·밀러 로버트
Original Assignee
아르레뜨 다낭제
톰슨 콤포넌츠-모스테크 코포레이션
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by 아르레뜨 다낭제, 톰슨 콤포넌츠-모스테크 코포레이션 filed Critical 아르레뜨 다낭제
Publication of KR870001665A publication Critical patent/KR870001665A/ko
Application granted granted Critical
Publication of KR930008007B1 publication Critical patent/KR930008007B1/ko

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B20/00—Read-only memory [ROM] devices
    • H10B20/27—ROM only
    • H10B20/30—ROM only having the source region and the drain region on the same level, e.g. lateral transistors
    • H10B20/38—Doping programmed, e.g. mask ROM
    • H10B20/387—Source region or drain region doping programmed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/082—Ion implantation FETs/COMs

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Memories (AREA)
  • Read Only Memory (AREA)
  • Circuits Of Receivers In General (AREA)
  • Complex Calculations (AREA)

Abstract

내용 없음.

Description

ROM 제조방법
제2도는 본 발명의 일실시예에 대한 횡단면도.
제3도는 본 발명의 또 다른 실시예에 대한 횡단면도.
* 도면의 주요부분에 대한 부호의 설명
12 : 기판 14 : 게이트
18 : 소스 20 : 드레인
26,28 : n-갭영역 30,32 : 트랜지스터
34 : 보론주입물

Claims (4)

  1. 실리콘 기판(12)상에 다수의 트랜지스터를 형서하되, 각각의 트랜지스터가 기판상에 형성된 게이트(14)와 기판에 형성되고 게이트로부터 떨어져 있는 소스(18) 및 드레인(20)을 구비하여, 소스와 들인 사이에 측면 갭을 형성하고 드레인과 게이트사이에 측면갭을 형성하는 단계와, 기판을 저도우즈 인 주입물로 처리하여, 각각의 트래지스터의 소스와 드레인을 게이트에 연결하는 n-갭영역(26,28)을 형성하는 단계와, 희망한 프로그램 코드에 따라서 선택된 트랜지스터(30)를 마스킹하는 단계와, 기판을 보론 주입물(34)로 처리하여, 마스크되지 않은 트랜지스터의 n-갭 영역을 역도핑하는 단계를 포함하며, 희망한 프로그램 코드에 따라서, 상기 마스크된 트랜지스터(30)는 장상 임계전압을 가지며, 마스크되지 않은 트랜지스터(32)는 정상보다 큰 임계전압을 갖는 것을 특징으로 하는 ROM 제조방법.
  2. 제1항에 있어서, 보론 주입물은 50 재지 75Kev의 에너지에서, 1014이온/㎠의 도우즈에서 주입되는 것을 특징으로 하는 ROM 제조방법.
  3. 제1항에 있어서, 보론 주입물은 n-캡 영역에서 P-형으로 바뀌는 것을 특징으로 하는 ROM 제조방법
  4. 실리콘 기판(12)상에 다수의 트랜지스터를 형성하되, 각각의 트랜지스터는 기판상에 형성된 게이트(14)와, 기판에 형성되고 상기 게이트로부터 떨어져 있는 소스(18) 및 드레인(20)을 구비하여, 소스와 게이트사이에 특면갭을 형성하고 드레인과 게이트 사이에 측면갭을 형성하는 단계와, 희망한 프로그램 코드에 따라서 선택된 트랜지스터(40)를 마스킹하는 단계와, 기판을 저 도우즈 인 주입물(44)로 처리하여,마스크되지 않은 트랜지스터에서 소스와 드레인을 게이트에 연결하는 n-갭영역(26),(28)을 형성하는 단게를 포함하며, 희망한 프로그램 코드에 따라서, 마스크되지 않은 트랜지스터(42)는 정상 임계 전압을 가지며, 마스크된 트랜지스터(40)는 정상보다 높은 임계전압을 갖는 것응 특징으로 하는 ROM 제조방법.
    ※ 참고사항 : 최초 출원내용에 의하여 공개하는 것임.
KR1019860006213A 1985-07-29 1986-07-29 Rom 제조방법 KR930008007B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US760206 1985-07-29
US06/760,206 US4649629A (en) 1985-07-29 1985-07-29 Method of late programming a read only memory

Publications (2)

Publication Number Publication Date
KR870001665A true KR870001665A (ko) 1987-03-17
KR930008007B1 KR930008007B1 (ko) 1993-08-25

Family

ID=25058426

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019860006213A KR930008007B1 (ko) 1985-07-29 1986-07-29 Rom 제조방법

Country Status (6)

Country Link
US (1) US4649629A (ko)
EP (1) EP0213983B1 (ko)
JP (1) JPH07120715B2 (ko)
KR (1) KR930008007B1 (ko)
AT (1) ATE60689T1 (ko)
DE (1) DE3677293D1 (ko)

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Also Published As

Publication number Publication date
EP0213983B1 (en) 1991-01-30
EP0213983A2 (en) 1987-03-11
JPH07120715B2 (ja) 1995-12-20
KR930008007B1 (ko) 1993-08-25
DE3677293D1 (de) 1991-03-07
US4649629A (en) 1987-03-17
ATE60689T1 (de) 1991-02-15
EP0213983A3 (en) 1987-07-01
JPS6285462A (ja) 1987-04-18

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