KR20070085776A - 건식 에칭 방법 및 건식 에칭 장치 - Google Patents

건식 에칭 방법 및 건식 에칭 장치 Download PDF

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Publication number
KR20070085776A
KR20070085776A KR1020077012669A KR20077012669A KR20070085776A KR 20070085776 A KR20070085776 A KR 20070085776A KR 1020077012669 A KR1020077012669 A KR 1020077012669A KR 20077012669 A KR20077012669 A KR 20077012669A KR 20070085776 A KR20070085776 A KR 20070085776A
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KR
South Korea
Prior art keywords
etching
gas
etched layer
layer
etched
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
KR1020077012669A
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English (en)
Korean (ko)
Inventor
미츠히로 오쿠네
히로유키 스즈키
Original Assignee
마츠시타 덴끼 산교 가부시키가이샤
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 마츠시타 덴끼 산교 가부시키가이샤 filed Critical 마츠시타 덴끼 산교 가부시키가이샤
Publication of KR20070085776A publication Critical patent/KR20070085776A/ko
Withdrawn legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
    • H01L21/32137—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas of silicon-containing layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3065—Plasma etching; Reactive-ion etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
    • H01J37/32—Gas-filled discharge tubes
    • H01J37/32009—Arrangements for generation of plasma specially adapted for examination or treatment of objects, e.g. plasma sources
    • H01J37/32082—Radio frequency generated discharge
    • H01J37/32091—Radio frequency generated discharge the radio frequency energy being capacitively coupled to the plasma

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Plasma & Fusion (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Analytical Chemistry (AREA)
  • Drying Of Semiconductors (AREA)
KR1020077012669A 2004-12-06 2005-12-06 건식 에칭 방법 및 건식 에칭 장치 Withdrawn KR20070085776A (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JPJP-P-2004-00352614 2004-12-06
JP2004352614A JP4629421B2 (ja) 2004-12-06 2004-12-06 ドライエッチング方法及びドライエッチング装置

Publications (1)

Publication Number Publication Date
KR20070085776A true KR20070085776A (ko) 2007-08-27

Family

ID=36577912

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020077012669A Withdrawn KR20070085776A (ko) 2004-12-06 2005-12-06 건식 에칭 방법 및 건식 에칭 장치

Country Status (5)

Country Link
US (2) US20080093338A1 (enExample)
JP (1) JP4629421B2 (enExample)
KR (1) KR20070085776A (enExample)
TW (1) TW200629403A (enExample)
WO (1) WO2006062085A1 (enExample)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2012087921A1 (en) * 2010-12-20 2012-06-28 Applied Materials, Inc. Methods for etching a substrate
US8492902B2 (en) 2010-09-27 2013-07-23 Samsung Electronics Co., Ltd. Multi-layer TSV insulation and methods of fabricating the same
KR20200011898A (ko) * 2018-07-25 2020-02-04 도쿄엘렉트론가부시키가이샤 플라즈마 처리 방법 및 플라즈마 처리 장치
KR20220119139A (ko) * 2019-12-23 2022-08-26 어플라이드 머티어리얼스, 인코포레이티드 반도체 애플리케이션들에 대해 재료 층을 에칭하기 위한 방법들

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20080060017A (ko) * 2006-12-26 2008-07-01 주식회사 하이닉스반도체 반도체 소자의 제조방법
JP5154260B2 (ja) * 2008-02-26 2013-02-27 パナソニック株式会社 ドライエッチング方法及びドライエッチング装置
TWI495009B (zh) * 2010-02-12 2015-08-01 Advanced Micro Fab Equip Inc A Plasma Etching Method with Silicon Insulating Layer
JP5943369B2 (ja) * 2011-02-09 2016-07-05 国立研究開発法人産業技術総合研究所 熱伝導積層膜部材及びその製造方法、これを用いた放熱部品及び放熱デバイス
US8691698B2 (en) * 2012-02-08 2014-04-08 Lam Research Corporation Controlled gas mixing for smooth sidewall rapid alternating etch process
US8951915B2 (en) 2012-09-11 2015-02-10 Infineon Technologies Ag Methods for manufacturing a chip arrangement, methods for manufacturing a chip package, a chip package and chip arrangements
SG10201703513WA (en) 2012-10-30 2017-06-29 Air Liquide Fluorocarbon molecules for high aspect ratio oxide etch
JP2015032597A (ja) * 2013-07-31 2015-02-16 日本ゼオン株式会社 プラズマエッチング方法
CN103820863A (zh) * 2014-02-25 2014-05-28 四川飞阳科技有限公司 石英衬底上多晶硅的刻蚀方法以及平面光波导的制作方法
KR102333443B1 (ko) 2014-10-24 2021-12-02 삼성전자주식회사 반도체 소자의 제조 방법
CN105752928B (zh) * 2014-12-16 2018-04-13 中芯国际集成电路制造(上海)有限公司 Mems器件的制作方法及mems器件
JP6492288B2 (ja) * 2015-10-01 2019-04-03 パナソニックＩｐマネジメント株式会社 素子チップの製造方法
JP6524419B2 (ja) * 2016-02-04 2019-06-05 パナソニックＩｐマネジメント株式会社 素子チップの製造方法
TW202425121A (zh) * 2022-08-25 2024-06-16 日商東京威力科創股份有限公司 蝕刻方法及電漿處理裝置
US20240395557A1 (en) * 2023-05-23 2024-11-28 Tokyo Electron Limited Systems and methods for semiconductor etching

Family Cites Families (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4647512A (en) * 1986-03-20 1987-03-03 The Perkin-Elmer Corporation Diamond-like carbon films and process for production thereof
US5423936A (en) * 1992-10-19 1995-06-13 Hitachi, Ltd. Plasma etching system
JP2666768B2 (ja) * 1995-04-27 1997-10-22 日本電気株式会社 ドライエッチング方法及び装置
US6071822A (en) * 1998-06-08 2000-06-06 Plasma-Therm, Inc. Etching process for producing substantially undercut free silicon on insulator structures
US6390019B1 (en) * 1998-06-11 2002-05-21 Applied Materials, Inc. Chamber having improved process monitoring window
JP2001057359A (ja) * 1999-08-17 2001-02-27 Tokyo Electron Ltd プラズマ処理装置
US6391788B1 (en) * 2000-02-25 2002-05-21 Applied Materials, Inc. Two etchant etch method
JP3920015B2 (ja) * 2000-09-14 2007-05-30 東京エレクトロン株式会社 Ｓｉ基板の加工方法
JP2002176182A (ja) * 2000-12-06 2002-06-21 Denso Corp 容量式力学量センサの製造方法
US20030003748A1 (en) * 2001-05-24 2003-01-02 Anisul Khan Method of eliminating notching when anisotropically etching small linewidth openings in silicon on insulator
DE60106011T2 (de) * 2001-07-23 2006-03-02 Infineon Technologies Ag Verfahren zur Bildung einer Isolierschicht und Verfahren zur Herstellung eines Grabenkondensators
JP3527901B2 (ja) * 2001-07-24 2004-05-17 株式会社日立製作所 プラズマエッチング方法
JP3971603B2 (ja) * 2001-12-04 2007-09-05 キヤノンアネルバ株式会社 絶縁膜エッチング装置及び絶縁膜エッチング方法
JP2003273086A (ja) * 2002-03-19 2003-09-26 Matsushita Electric Ind Co Ltd ドライエッチング方法および半導体製造装置
US20030228768A1 (en) * 2002-06-05 2003-12-11 Applied Materials, Inc. Dielectric etching with reduced striation
US6897154B2 (en) * 2002-06-14 2005-05-24 Applied Materials Inc Selective etching of low-k dielectrics
US6939811B2 (en) * 2002-09-25 2005-09-06 Lam Research Corporation Apparatus and method for controlling etch depth
US20040077178A1 (en) * 2002-10-17 2004-04-22 Applied Materials, Inc. Method for laterally etching a semiconductor structure
US6905616B2 (en) * 2003-03-05 2005-06-14 Applied Materials, Inc. Method of releasing devices from a substrate
JP4065213B2 (ja) * 2003-03-25 2008-03-19 住友精密工業株式会社 シリコン基板のエッチング方法及びエッチング装置
JP3972846B2 (ja) * 2003-03-25 2007-09-05 セイコーエプソン株式会社 半導体装置の製造方法
TWI249767B (en) * 2004-02-17 2006-02-21 Sanyo Electric Co Method for making a semiconductor device
JP4493516B2 (ja) * 2004-02-17 2010-06-30 三洋電機株式会社 半導体装置の製造方法
US7232762B2 (en) * 2004-06-16 2007-06-19 Taiwan Semiconductor Manufacturing Co., Ltd. Method for forming an improved low power SRAM contact

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8492902B2 (en) 2010-09-27 2013-07-23 Samsung Electronics Co., Ltd. Multi-layer TSV insulation and methods of fabricating the same
WO2012087921A1 (en) * 2010-12-20 2012-06-28 Applied Materials, Inc. Methods for etching a substrate
KR20200011898A (ko) * 2018-07-25 2020-02-04 도쿄엘렉트론가부시키가이샤 플라즈마 처리 방법 및 플라즈마 처리 장치
KR20220119139A (ko) * 2019-12-23 2022-08-26 어플라이드 머티어리얼스, 인코포레이티드 반도체 애플리케이션들에 대해 재료 층을 에칭하기 위한 방법들

Also Published As

Publication number Publication date
JP4629421B2 (ja) 2011-02-09
TW200629403A (en) 2006-08-16
US20120094500A1 (en) 2012-04-19
WO2006062085A1 (ja) 2006-06-15
US20080093338A1 (en) 2008-04-24
JP2006165164A (ja) 2006-06-22

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Legal Events

Date Code Title Description
PA0105 International application

Patent event date: 20070605

Patent event code: PA01051R01D

Comment text: International Patent Application

PG1501 Laying open of application
PC1203 Withdrawal of no request for examination
WITN Application deemed withdrawn, e.g. because no request for examination was filed or no examination fee was paid