JP4791956B2 - プラズマエッチングチャンバ内でポリシリコンゲート構造をエッチングするための方法、及び基板の異なるドープ済み材料の間のエッチング速度のマイクロローディングを減少させる方法 - Google Patents
プラズマエッチングチャンバ内でポリシリコンゲート構造をエッチングするための方法、及び基板の異なるドープ済み材料の間のエッチング速度のマイクロローディングを減少させる方法 Download PDFInfo
- Publication number
- JP4791956B2 JP4791956B2 JP2006508888A JP2006508888A JP4791956B2 JP 4791956 B2 JP4791956 B2 JP 4791956B2 JP 2006508888 A JP2006508888 A JP 2006508888A JP 2006508888 A JP2006508888 A JP 2006508888A JP 4791956 B2 JP4791956 B2 JP 4791956B2
- Authority
- JP
- Japan
- Prior art keywords
- etching
- silicon
- plasma
- chamber
- containing gas
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 238000005530 etching Methods 0.000 title claims description 108
- 238000000034 method Methods 0.000 title claims description 62
- 239000000758 substrate Substances 0.000 title claims description 53
- 229910021420 polycrystalline silicon Inorganic materials 0.000 title claims description 45
- 229920005591 polysilicon Polymers 0.000 title claims description 43
- 239000000463 material Substances 0.000 title claims description 11
- 229910052710 silicon Inorganic materials 0.000 claims description 112
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 111
- 239000010703 silicon Substances 0.000 claims description 111
- 239000011241 protective layer Substances 0.000 claims description 18
- 238000001020 plasma etching Methods 0.000 claims description 17
- 239000006227 byproduct Substances 0.000 claims description 11
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 claims description 10
- 230000015572 biosynthetic process Effects 0.000 claims description 7
- 230000009977 dual effect Effects 0.000 claims description 6
- 239000007787 solid Substances 0.000 claims description 6
- 239000007789 gas Substances 0.000 description 100
- 239000010410 layer Substances 0.000 description 58
- 230000008569 process Effects 0.000 description 36
- 235000012431 wafers Nutrition 0.000 description 25
- 239000004065 semiconductor Substances 0.000 description 17
- 239000000460 chlorine Substances 0.000 description 16
- 239000000203 mixture Substances 0.000 description 16
- 229910052581 Si3N4 Inorganic materials 0.000 description 14
- 229920002120 photoresistant polymer Polymers 0.000 description 14
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 14
- 229910003902 SiCl 4 Inorganic materials 0.000 description 10
- 238000002955 isolation Methods 0.000 description 8
- 229910052760 oxygen Inorganic materials 0.000 description 7
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 6
- 239000001301 oxygen Substances 0.000 description 6
- 230000008021 deposition Effects 0.000 description 5
- 238000006243 chemical reaction Methods 0.000 description 4
- 238000009616 inductively coupled plasma Methods 0.000 description 4
- 230000001681 protective effect Effects 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 229910003691 SiBr Inorganic materials 0.000 description 3
- SLLGVCUQYRMELA-UHFFFAOYSA-N chlorosilicon Chemical compound Cl[Si] SLLGVCUQYRMELA-UHFFFAOYSA-N 0.000 description 3
- 230000002708 enhancing effect Effects 0.000 description 3
- 229910052736 halogen Inorganic materials 0.000 description 3
- 150000002367 halogens Chemical class 0.000 description 3
- 229910052734 helium Inorganic materials 0.000 description 3
- 230000007246 mechanism Effects 0.000 description 3
- 235000012239 silicon dioxide Nutrition 0.000 description 3
- -1 further Substances 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 2
- 229910052794 bromium Inorganic materials 0.000 description 2
- 229910052799 carbon Inorganic materials 0.000 description 2
- 229910052801 chlorine Inorganic materials 0.000 description 2
- 238000001514 detection method Methods 0.000 description 2
- 229910052731 fluorine Inorganic materials 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 2
- 229910052757 nitrogen Inorganic materials 0.000 description 2
- 239000010453 quartz Substances 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- 230000004044 response Effects 0.000 description 2
- 238000000926 separation method Methods 0.000 description 2
- 239000002210 silicon-based material Substances 0.000 description 2
- 238000009966 trimming Methods 0.000 description 2
- 238000007740 vapor deposition Methods 0.000 description 2
- BSYNRYMUTXBXSQ-UHFFFAOYSA-N Aspirin Chemical compound CC(=O)OC1=CC=CC=C1C(O)=O BSYNRYMUTXBXSQ-UHFFFAOYSA-N 0.000 description 1
- WKBOTKDWSSQWDR-UHFFFAOYSA-N Bromine atom Chemical compound [Br] WKBOTKDWSSQWDR-UHFFFAOYSA-N 0.000 description 1
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 description 1
- MYMOFIZGZYHOMD-UHFFFAOYSA-N Dioxygen Chemical compound O=O MYMOFIZGZYHOMD-UHFFFAOYSA-N 0.000 description 1
- PXGOKWXKJXAPGV-UHFFFAOYSA-N Fluorine Chemical compound FF PXGOKWXKJXAPGV-UHFFFAOYSA-N 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 230000009471 action Effects 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- GDTBXPJZTBHREO-UHFFFAOYSA-N bromine Substances BrBr GDTBXPJZTBHREO-UHFFFAOYSA-N 0.000 description 1
- 239000013043 chemical agent Substances 0.000 description 1
- 239000007795 chemical reaction product Substances 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 230000001010 compromised effect Effects 0.000 description 1
- 239000000470 constituent Substances 0.000 description 1
- 239000008367 deionised water Substances 0.000 description 1
- 229910021641 deionized water Inorganic materials 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 229910001882 dioxygen Inorganic materials 0.000 description 1
- 238000010494 dissociation reaction Methods 0.000 description 1
- 230000005593 dissociations Effects 0.000 description 1
- 238000005553 drilling Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 239000011737 fluorine Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000001307 helium Substances 0.000 description 1
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 230000000670 limiting effect Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229920000642 polymer Polymers 0.000 description 1
- 239000000047 product Substances 0.000 description 1
- 230000002829 reductive effect Effects 0.000 description 1
- 238000007086 side reaction Methods 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 125000006850 spacer group Chemical group 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000005019 vapor deposition process Methods 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/3065—Plasma etching; Reactive-ion etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
- H01L21/28044—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
- H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
- H01L21/32137—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas of silicon-containing layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
- H01L21/823842—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Plasma & Fusion (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Chemical & Material Sciences (AREA)
- Drying Of Semiconductors (AREA)
- Electrodes Of Semiconductors (AREA)
- Element Separation (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Description
12…パッド酸化物
14…窒化シリコン層
16…下部反射防止膜
18…フォトレジスト層
20…開口部
22…開口部
24…トレンチ構造
30…シリコンウエハ
32…酸化物層
34…ポリシリコン層
36…窒化シリコン層
38…フォトレジスト層
40…開口部
42…開口部
100…切れ込み
102a…ゲート形状
102b…ゲート形状
102c…ゲート形状
110…ゲート
112…ゲート
120…エッチングチャンバ
122…ガス流入口
124…電極
126…半導体基板
128…静電チャック
130…流出口
132…処理ガス供給源
134…制御部
Claims (7)
- プラズマエッチングチャンバ内でポリシリコンゲート構造をエッチングするための方法であって、
エッチングされるポリシリコンフィルムを保護するパターンを設ける工程と、
プラズマを点火する工程と、
保護されていない前記ポリシリコンフィルムのほぼすべてをエッチングする工程と、
前記プラズマエッチングチャンバ内に設置された固体シリコン源から生じるシリコン含有ガスを導入しつつ、前記ポリシリコンフィルムの残りをエッチングする工程と、
を備え、
前記シリコン含有ガスは、SiH3CH3、SiH(CH3)3、および、テトラエチルオルトシリケート(TEOS)から選択される、方法。 - 請求項1に記載の方法であって、
前記固体シリコン源は、前記プラズマエッチングチャンバの上部電極に含まれている、方法。 - 請求項1に記載の方法であって、前記保護されていない前記ポリシリコンフィルムのほぼすべてをエッチングする工程は、
ハードマスクを除去するための第1のエッチングを行う工程と、
保護されていない前記ポリシリコンフィルムを除去するための第2のエッチングを行う工程と、を備える、方法。 - 請求項1に記載の方法であって、前記シリコン含有ガスを導入しつつ、前記ポリシリコンフィルムの残りをエッチングする工程は、
前記ポリシリコンゲート構造の基部における切れ込みの形成を防止する工程を備える、方法。 - 請求項1に記載の方法であって、前記シリコン含有ガスを導入する工程は、
保護されていない前記ポリシリコンフィルムのエッチングを終了させる工程と、
オーバーエッチングプラズマを点火する工程と、を備える、方法。 - 請求項1に記載の方法であって、さらに、
前記ポリシリコンフィルムのエッチングによって生成された副産物から保護層を形成する工程を備える、方法。 - 基板の異なるドープ済み材料の間のエッチング速度のマイクロローディングを減少させる方法であって、
チャンバ内でプラズマを点火する工程と、
前記基板のnドープポリシリコンゲートとpドープポリシリコンゲートとを含むデュアルドープゲート構造のエッチングを、前記nドープポリシリコンゲート及びpドープポリシリコンゲートを同時にエッチングするように実行する工程と、
前記デュアルドープゲート構造のエッチングによって生成された副産物から保護層を形成する工程と、
前記チャンバ内に設置された固体シリコン源から生じるシリコン含有ガスを供給して前記保護層を強化する工程と、
を備え、
前記シリコン含有ガスは、SiH 3 CH 3 、SiH(CH 3 ) 3 、および、テトラエチルオルトシリケート(TEOS)から選択される、方法。
Applications Claiming Priority (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/376,227 | 2003-03-03 | ||
US10/376,227 US7098141B1 (en) | 2003-03-03 | 2003-03-03 | Use of silicon containing gas for CD and profile feature enhancements of gate and shallow trench structures |
US10/607,612 | 2003-06-27 | ||
US10/607,612 US7186661B2 (en) | 2003-03-03 | 2003-06-27 | Method to improve profile control and N/P loading in dual doped gate applications |
PCT/US2004/005944 WO2004079783A2 (en) | 2003-03-03 | 2004-02-26 | Method to improve profile control and n/p loading in dual doped gate applications |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2011130622A Division JP2011211225A (ja) | 2003-03-03 | 2011-06-10 | デュアルドープゲートの用途におけるプロフィル制御とn/pローディングを改善する方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2006523381A JP2006523381A (ja) | 2006-10-12 |
JP4791956B2 true JP4791956B2 (ja) | 2011-10-12 |
Family
ID=32926284
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2006508888A Expired - Fee Related JP4791956B2 (ja) | 2003-03-03 | 2004-02-26 | プラズマエッチングチャンバ内でポリシリコンゲート構造をエッチングするための方法、及び基板の異なるドープ済み材料の間のエッチング速度のマイクロローディングを減少させる方法 |
JP2011130622A Pending JP2011211225A (ja) | 2003-03-03 | 2011-06-10 | デュアルドープゲートの用途におけるプロフィル制御とn/pローディングを改善する方法 |
Family Applications After (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2011130622A Pending JP2011211225A (ja) | 2003-03-03 | 2011-06-10 | デュアルドープゲートの用途におけるプロフィル制御とn/pローディングを改善する方法 |
Country Status (3)
Country | Link |
---|---|
US (2) | US7098141B1 (ja) |
JP (2) | JP4791956B2 (ja) |
CN (1) | CN100405551C (ja) |
Families Citing this family (32)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7098141B1 (en) * | 2003-03-03 | 2006-08-29 | Lam Research Corporation | Use of silicon containing gas for CD and profile feature enhancements of gate and shallow trench structures |
WO2004079783A2 (en) * | 2003-03-03 | 2004-09-16 | Lam Research Corporation | Method to improve profile control and n/p loading in dual doped gate applications |
US6893938B2 (en) * | 2003-04-21 | 2005-05-17 | Infineon Technologies Ag | STI formation for vertical and planar transistors |
US7060628B2 (en) * | 2004-03-19 | 2006-06-13 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method for fabricating a hard mask polysilicon gate |
US20050274691A1 (en) * | 2004-05-27 | 2005-12-15 | Hyun-Mog Park | Etch method to minimize hard mask undercut |
US7250373B2 (en) * | 2004-08-27 | 2007-07-31 | Applied Materials, Inc. | Method and apparatus for etching material layers with high uniformity of a lateral etch rate across a substrate |
CN100449693C (zh) * | 2004-11-04 | 2009-01-07 | 上海华虹(集团)有限公司 | 一种去除栅刻蚀横向凹槽的方法 |
US7682940B2 (en) | 2004-12-01 | 2010-03-23 | Applied Materials, Inc. | Use of Cl2 and/or HCl during silicon epitaxial film formation |
US20060166416A1 (en) * | 2005-01-27 | 2006-07-27 | International Business Machines Corporation | Addition of ballast hydrocarbon gas to doped polysilicon etch masked by resist |
JP2007036018A (ja) * | 2005-07-28 | 2007-02-08 | Toshiba Corp | 半導体装置の製造方法 |
US7481943B2 (en) * | 2005-08-08 | 2009-01-27 | Silverbrook Research Pty Ltd | Method suitable for etching hydrophillic trenches in a substrate |
KR100672721B1 (ko) * | 2005-12-29 | 2007-01-22 | 동부일렉트로닉스 주식회사 | 플래쉬 메모리의 제조방법 |
KR100720473B1 (ko) * | 2005-12-30 | 2007-05-22 | 동부일렉트로닉스 주식회사 | 반도체 트랜지스터의 제조 방법 |
US7674337B2 (en) | 2006-04-07 | 2010-03-09 | Applied Materials, Inc. | Gas manifolds for use during epitaxial film formation |
US7932181B2 (en) * | 2006-06-20 | 2011-04-26 | Lam Research Corporation | Edge gas injection for critical dimension uniformity improvement |
CN103981568A (zh) | 2006-07-31 | 2014-08-13 | 应用材料公司 | 形成含碳外延硅层的方法 |
KR100827538B1 (ko) * | 2006-12-28 | 2008-05-06 | 주식회사 하이닉스반도체 | 반도체 소자 및 그 제조 방법 |
KR20080086686A (ko) * | 2007-03-23 | 2008-09-26 | 주식회사 하이닉스반도체 | 반도체 소자의 제조방법 |
JP2009147000A (ja) * | 2007-12-12 | 2009-07-02 | Seiko Instruments Inc | 半導体装置の製造方法 |
CN101740373B (zh) * | 2008-11-14 | 2011-11-30 | 中芯国际集成电路制造(北京)有限公司 | 浅沟槽形成方法 |
US8404561B2 (en) * | 2009-05-18 | 2013-03-26 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for fabricating an isolation structure |
CN102194676B (zh) * | 2010-03-11 | 2013-06-12 | 中芯国际集成电路制造(上海)有限公司 | 制作半导体器件栅极的方法 |
CN102280375B (zh) * | 2010-06-08 | 2013-10-16 | 中国科学院微电子研究所 | 一种先栅工艺中叠层金属栅结构的制备方法 |
CN102427029A (zh) * | 2011-08-04 | 2012-04-25 | 上海华力微电子有限公司 | 一种用于栅极相关制程及其后续制程监控的测试器件结构的其制备工艺 |
JP5932599B2 (ja) | 2011-10-31 | 2016-06-08 | 株式会社日立ハイテクノロジーズ | プラズマエッチング方法 |
CN103779203B (zh) * | 2012-10-17 | 2016-11-02 | 株式会社日立高新技术 | 等离子蚀刻方法 |
JP6340338B2 (ja) * | 2015-03-30 | 2018-06-06 | 東京エレクトロン株式会社 | 薄膜の形成方法 |
JP6748354B2 (ja) * | 2015-09-18 | 2020-09-02 | セントラル硝子株式会社 | ドライエッチング方法及びドライエッチング剤 |
JP7037397B2 (ja) * | 2018-03-16 | 2022-03-16 | キオクシア株式会社 | 基板処理装置、基板処理方法、および半導体装置の製造方法 |
TWI759754B (zh) * | 2020-06-03 | 2022-04-01 | 台灣奈米碳素股份有限公司 | 製作半導體裝置的溝槽結構的乾式蝕刻製程 |
JP2022172753A (ja) * | 2021-05-07 | 2022-11-17 | 東京エレクトロン株式会社 | 基板処理方法および基板処理装置 |
GB202209674D0 (en) * | 2022-07-01 | 2022-08-17 | Spts Technologies Ltd | Control of trench profile angle in SiC semiconductors |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH04350932A (ja) * | 1991-05-29 | 1992-12-04 | Toshiba Corp | ドライエッチング方法 |
JPH08213368A (ja) * | 1995-02-08 | 1996-08-20 | Nippon Telegr & Teleph Corp <Ntt> | エッチング方法 |
JP2001093879A (ja) * | 1999-07-27 | 2001-04-06 | Applied Materials Inc | 基板上のシリコンエッチング方法 |
JP2001526462A (ja) * | 1997-12-05 | 2001-12-18 | アプライド マテリアルズ インコーポレイテッド | シリコンに高アスペクト比のトレンチを形成するための新規なエッチング方法 |
JP2003518738A (ja) * | 1999-12-20 | 2003-06-10 | アプライド マテリアルズ インコーポレイテッド | シリコンの金属マスクエッチング方法 |
Family Cites Families (59)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4490209B2 (en) | 1983-12-27 | 2000-12-19 | Texas Instruments Inc | Plasma etching using hydrogen bromide addition |
US4702795A (en) | 1985-05-03 | 1987-10-27 | Texas Instruments Incorporated | Trench etch process |
US4784720A (en) | 1985-05-03 | 1988-11-15 | Texas Instruments Incorporated | Trench etch process for a single-wafer RIE dry etch reactor |
DE3752259T2 (de) | 1986-12-19 | 1999-10-14 | Applied Materials | Bromine-Ätzverfahren für Silizium |
US4855015A (en) | 1988-04-29 | 1989-08-08 | Texas Instruments Incorporated | Dry etch process for selectively etching non-homogeneous material bilayers |
US5707486A (en) | 1990-07-31 | 1998-01-13 | Applied Materials, Inc. | Plasma reactor using UHF/VHF and RF triode source, and process |
US6251792B1 (en) | 1990-07-31 | 2001-06-26 | Applied Materials, Inc. | Plasma etch processes |
US5094712A (en) | 1990-10-09 | 1992-03-10 | Micron Technology, Inc. | One chamber in-situ etch process for oxide and conductive material |
US6171974B1 (en) | 1991-06-27 | 2001-01-09 | Applied Materials, Inc. | High selectivity oxide etch process for integrated circuit structures |
US6518195B1 (en) * | 1991-06-27 | 2003-02-11 | Applied Materials, Inc. | Plasma reactor using inductive RF coupling, and processes |
US5352617A (en) | 1992-04-27 | 1994-10-04 | Sony Corporation | Method for manufacturing Bi-CMOS transistor devices |
JP3111643B2 (ja) * | 1992-06-09 | 2000-11-27 | ソニー株式会社 | ドライエッチング方法 |
JP2746167B2 (ja) * | 1995-01-25 | 1998-04-28 | 日本電気株式会社 | 半導体装置の製造方法 |
US5820261A (en) | 1995-07-26 | 1998-10-13 | Applied Materials, Inc. | Method and apparatus for infrared pyrometer calibration in a rapid thermal processing system |
US5705433A (en) * | 1995-08-24 | 1998-01-06 | Applied Materials, Inc. | Etching silicon-containing materials by use of silicon-containing compounds |
US5705409A (en) * | 1995-09-28 | 1998-01-06 | Motorola Inc. | Method for forming trench transistor structure |
US5948283A (en) | 1996-06-28 | 1999-09-07 | Lam Research Corporation | Method and apparatus for enhancing outcome uniformity of direct-plasma processes |
US5753561A (en) | 1996-09-30 | 1998-05-19 | Vlsi Technology, Inc. | Method for making shallow trench isolation structure having rounded corners |
US6033969A (en) | 1996-09-30 | 2000-03-07 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method of forming a shallow trench isolation that has rounded and protected corners |
JP4436463B2 (ja) * | 1996-11-06 | 2010-03-24 | シーメンス アクチエンゲゼルシヤフト | 3つの独立制御電極を具備したエッチングチャンバ装置 |
US6309979B1 (en) | 1996-12-18 | 2001-10-30 | Lam Research Corporation | Methods for reducing plasma-induced charging damage |
JPH10189548A (ja) * | 1996-12-20 | 1998-07-21 | Sony Corp | ドライエッチング方法 |
US5670397A (en) * | 1997-01-16 | 1997-09-23 | Powerchip Semiconductor Corp. | Dual poly-gate deep submicron CMOS with buried contact technology |
US6479373B2 (en) | 1997-02-20 | 2002-11-12 | Infineon Technologies Ag | Method of structuring layers with a polysilicon layer and an overlying metal or metal silicide layer using a three step etching process with fluorine, chlorine, bromine containing gases |
US5674775A (en) | 1997-02-20 | 1997-10-07 | Taiwan Semiconductor Manufacturing Company, Ltd. | Isolation trench with a rounded top edge using an etch buffer layer |
US5807789A (en) * | 1997-03-20 | 1998-09-15 | Taiwan Semiconductor Manufacturing, Co., Ltd. | Method for forming a shallow trench with tapered profile and round corners for the application of shallow trench isolation (STI) |
US5728621A (en) | 1997-04-28 | 1998-03-17 | Chartered Semiconductor Manufacturing Pte Ltd | Method for shallow trench isolation |
US6090304A (en) | 1997-08-28 | 2000-07-18 | Lam Research Corporation | Methods for selective plasma etch |
TW434802B (en) | 1997-10-09 | 2001-05-16 | United Microelectronics Corp | Method of manufacturing shallow trench isolation |
US5801083A (en) | 1997-10-20 | 1998-09-01 | Chartered Semiconductor Manufacturing, Ltd. | Use of polymer spacers for the fabrication of shallow trench isolation regions with rounded top corners |
US6872322B1 (en) * | 1997-11-12 | 2005-03-29 | Applied Materials, Inc. | Multiple stage process for cleaning process chambers |
US6008131A (en) | 1997-12-22 | 1999-12-28 | Taiwan Semiconductor Manufacturing Company Ltd. | Bottom rounding in shallow trench etching using a highly isotropic etching step |
US6743688B1 (en) * | 1998-01-05 | 2004-06-01 | Advanced Micro Devices, Inc. | High performance MOSFET with modulated channel gate thickness |
US6037265A (en) | 1998-02-12 | 2000-03-14 | Applied Materials, Inc. | Etchant gas and a method for etching transistor gates |
JPH11340213A (ja) * | 1998-03-12 | 1999-12-10 | Hitachi Ltd | 試料の表面加工方法 |
JP2000091321A (ja) * | 1998-09-10 | 2000-03-31 | Hitachi Ltd | 表面処理方法および装置 |
US6245684B1 (en) | 1998-03-13 | 2001-06-12 | Applied Materials, Inc. | Method of obtaining a rounded top trench corner for semiconductor trench etch applications |
JP3252789B2 (ja) * | 1998-04-03 | 2002-02-04 | 日本電気株式会社 | エッチング方法 |
US6083815A (en) | 1998-04-27 | 2000-07-04 | Taiwan Semiconductor Manufacturing Company | Method of gate etching with thin gate oxide |
JP2000133633A (ja) | 1998-09-09 | 2000-05-12 | Texas Instr Inc <Ti> | ハ―ドマスクおよびプラズマ活性化エッチャントを使用した材料のエッチング方法 |
US6037266A (en) | 1998-09-28 | 2000-03-14 | Taiwan Semiconductor Manufacturing Company | Method for patterning a polysilicon gate with a thin gate oxide in a polysilicon etcher |
US6309926B1 (en) | 1998-12-04 | 2001-10-30 | Advanced Micro Devices | Thin resist with nitride hard mask for gate etch application |
US6218309B1 (en) | 1999-06-30 | 2001-04-17 | Lam Research Corporation | Method of achieving top rounding and uniform etch depths while etching shallow trench isolation features |
US6287974B1 (en) | 1999-06-30 | 2001-09-11 | Lam Research Corporation | Method of achieving top rounding and uniform etch depths while etching shallow trench isolation features |
US6228727B1 (en) | 1999-09-27 | 2001-05-08 | Chartered Semiconductor Manufacturing, Ltd. | Method to form shallow trench isolations with rounded corners and reduced trench oxide recess |
US6258676B1 (en) | 1999-11-01 | 2001-07-10 | Chartered Semiconductor Manufacturing Ltd. | Method for forming a shallow trench isolation using HDP silicon oxynitride |
US6174786B1 (en) | 1999-11-23 | 2001-01-16 | Lucent Technologies, Inc. | Shallow trench isolation method providing rounded top trench corners |
US6391729B1 (en) | 2000-03-09 | 2002-05-21 | Advanced Micro Devices, Inc. | Shallow trench isolation formation to eliminate poly stringer with controlled step height and corner rounding |
US6514378B1 (en) | 2000-03-31 | 2003-02-04 | Lam Research Corporation | Method for improving uniformity and reducing etch rate variation of etching polysilicon |
US6303413B1 (en) | 2000-05-03 | 2001-10-16 | Maxim Integrated Products, Inc. | Method of forming a shallow and deep trench isolation (SDTI) suitable for silicon on insulator (SOI) substrates |
US6358859B1 (en) | 2000-05-26 | 2002-03-19 | Taiwan Semiconductor Manufacturing Company | HBr silicon etching process |
US6313007B1 (en) | 2000-06-07 | 2001-11-06 | Agere Systems Guardian Corp. | Semiconductor device, trench isolation structure and methods of formations |
US6403432B1 (en) | 2000-08-15 | 2002-06-11 | Taiwan Semiconductor Manufacturing Company | Hardmask for a salicide gate process with trench isolation |
US6283131B1 (en) | 2000-09-25 | 2001-09-04 | Taiwan Semiconductor Manufacturing Company | In-situ strip process for polysilicon etching in deep sub-micron technology |
JP2002319571A (ja) * | 2001-04-20 | 2002-10-31 | Kawasaki Microelectronics Kk | エッチング槽の前処理方法及び半導体装置の製造方法 |
TW518719B (en) * | 2001-10-26 | 2003-01-21 | Promos Technologies Inc | Manufacturing method of contact plug |
US6703269B2 (en) * | 2002-04-02 | 2004-03-09 | International Business Machines Corporation | Method to form gate conductor structures of dual doped polysilicon |
US6784077B1 (en) * | 2002-10-15 | 2004-08-31 | Taiwan Semiconductor Manufacturing Co. Ltd. | Shallow trench isolation process |
US7098141B1 (en) * | 2003-03-03 | 2006-08-29 | Lam Research Corporation | Use of silicon containing gas for CD and profile feature enhancements of gate and shallow trench structures |
-
2003
- 2003-03-03 US US10/376,227 patent/US7098141B1/en not_active Expired - Lifetime
- 2003-06-27 US US10/607,612 patent/US7186661B2/en not_active Expired - Fee Related
-
2004
- 2004-02-26 JP JP2006508888A patent/JP4791956B2/ja not_active Expired - Fee Related
- 2004-02-26 CN CNB2004800118296A patent/CN100405551C/zh not_active Expired - Fee Related
-
2011
- 2011-06-10 JP JP2011130622A patent/JP2011211225A/ja active Pending
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH04350932A (ja) * | 1991-05-29 | 1992-12-04 | Toshiba Corp | ドライエッチング方法 |
JPH08213368A (ja) * | 1995-02-08 | 1996-08-20 | Nippon Telegr & Teleph Corp <Ntt> | エッチング方法 |
JP2001526462A (ja) * | 1997-12-05 | 2001-12-18 | アプライド マテリアルズ インコーポレイテッド | シリコンに高アスペクト比のトレンチを形成するための新規なエッチング方法 |
JP2001093879A (ja) * | 1999-07-27 | 2001-04-06 | Applied Materials Inc | 基板上のシリコンエッチング方法 |
JP2003518738A (ja) * | 1999-12-20 | 2003-06-10 | アプライド マテリアルズ インコーポレイテッド | シリコンの金属マスクエッチング方法 |
Also Published As
Publication number | Publication date |
---|---|
JP2006523381A (ja) | 2006-10-12 |
US7186661B2 (en) | 2007-03-06 |
CN100405551C (zh) | 2008-07-23 |
US20040175950A1 (en) | 2004-09-09 |
US7098141B1 (en) | 2006-08-29 |
JP2011211225A (ja) | 2011-10-20 |
CN1781185A (zh) | 2006-05-31 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP4791956B2 (ja) | プラズマエッチングチャンバ内でポリシリコンゲート構造をエッチングするための方法、及び基板の異なるドープ済み材料の間のエッチング速度のマイクロローディングを減少させる方法 | |
US7682980B2 (en) | Method to improve profile control and N/P loading in dual doped gate applications | |
KR101111924B1 (ko) | 이중층 레지스트 플라즈마 에칭 방법 | |
US6380095B1 (en) | Silicon trench etch using silicon-containing precursors to reduce or avoid mask erosion | |
US7368394B2 (en) | Etch methods to form anisotropic features for high aspect ratio applications | |
US7361607B2 (en) | Method for multi-layer resist plasma etch | |
US8658541B2 (en) | Method of controlling trench microloading using plasma pulsing | |
US20060043066A1 (en) | Processes for pre-tapering silicon or silicon-germanium prior to etching shallow trenches | |
US20070202700A1 (en) | Etch methods to form anisotropic features for high aspect ratio applications | |
US20060021704A1 (en) | Method and apparatus for etching Si | |
JP2005508078A (ja) | 高アスペクト比形態のエッチング方法 | |
US6955964B2 (en) | Formation of a double gate structure | |
KR20150043978A (ko) | 플라즈마 처리 방법 | |
JP7296912B2 (ja) | 基板処理方法及び基板処理装置 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20070223 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20091215 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20100312 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20101214 |
|
A601 | Written request for extension of time |
Free format text: JAPANESE INTERMEDIATE CODE: A601 Effective date: 20110311 |
|
A602 | Written permission of extension of time |
Free format text: JAPANESE INTERMEDIATE CODE: A602 Effective date: 20110318 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20110610 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20110705 |
|
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20110722 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20140729 Year of fee payment: 3 |
|
R150 | Certificate of patent or registration of utility model |
Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
LAPS | Cancellation because of no payment of annual fees |